@cpp-linter/clang-tidy-darwin-arm64 20.1.0 → 20.1.8

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (15) hide show
  1. package/README.md +2 -2
  2. package/bin/clang-tidy +2 -2
  3. package/lib/clang/20/include/__clang_cuda_intrinsics.h +8 -8
  4. package/lib/clang/20/include/amdgpuintrin.h +1 -1
  5. package/lib/clang/20/include/avx10_2_512convertintrin.h +24 -22
  6. package/lib/clang/20/include/avx10_2_512satcvtdsintrin.h +28 -24
  7. package/lib/clang/20/include/avx10_2_512satcvtintrin.h +84 -84
  8. package/lib/clang/20/include/avx10_2convertintrin.h +50 -62
  9. package/lib/clang/20/include/avx10_2minmaxintrin.h +0 -45
  10. package/lib/clang/20/include/avx10_2niintrin.h +0 -1666
  11. package/lib/clang/20/include/avx10_2satcvtdsintrin.h +52 -158
  12. package/lib/clang/20/include/avx10_2satcvtintrin.h +88 -200
  13. package/lib/clang/20/include/nvptxintrin.h +2 -1
  14. package/lib/clang/20/include/vecintrin.h +5 -0
  15. package/package.json +5 -5
package/lib/clang/20/include/avx10_2convertintrin.h CHANGED
@@ -63,22 +63,8 @@ _mm256_maskz_cvtx2ps_ph(__mmask16 __U, __m256 __A, __m256 __B) {
63
63
  _MM_FROUND_CUR_DIRECTION);
64
64
  }
65
65
 
66
- #define _mm256_cvtx_round2ps_ph(A, B, R) \
67
- ((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \
68
- (__v8sf)(A), (__v8sf)(B), (__v16hf)_mm256_undefined_ph(), \
69
- (__mmask16)(-1), (const int)(R)))
70
-
71
- #define _mm256_mask_cvtx_round2ps_ph(W, U, A, B, R) \
72
- ((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \
73
- (__v8sf)(A), (__v8sf)(B), (__v16hf)(W), (__mmask16)(U), (const int)(R)))
74
-
75
- #define _mm256_maskz_cvtx_round2ps_ph(U, A, B, R) \
76
- ((__m256h)__builtin_ia32_vcvt2ps2phx256_mask( \
77
- (__v8sf)(A), (__v8sf)(B), (__v16hf)(_mm256_setzero_ph()), \
78
- (__mmask16)(U), (const int)(R)))
79
-
80
- static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtbiasph_bf8(__m128i __A,
81
- __m128h __B) {
66
+ static __inline__ __m128i __DEFAULT_FN_ATTRS128
67
+ _mm_cvtbiasph_bf8(__m128i __A, __m128h __B) {
82
68
  return (__m128i)__builtin_ia32_vcvtbiasph2bf8_128_mask(
83
69
  (__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
84
70
  }
@@ -117,39 +103,39 @@ _mm256_maskz_cvtbiasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
117
103
  }
118
104
 
119
105
  static __inline__ __m128i __DEFAULT_FN_ATTRS128
120
- _mm_cvtbiassph_bf8(__m128i __A, __m128h __B) {
106
+ _mm_cvts_biasph_bf8(__m128i __A, __m128h __B) {
121
107
  return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask(
122
108
  (__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
123
109
  }
124
110
 
125
111
  static __inline__ __m128i __DEFAULT_FN_ATTRS128
126
- _mm_mask_cvtbiassph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
112
+ _mm_mask_cvts_biasph_bf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
127
113
  return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask(
128
114
  (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
129
115
  }
130
116
 
131
117
  static __inline__ __m128i __DEFAULT_FN_ATTRS128
132
- _mm_maskz_cvtbiassph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
118
+ _mm_maskz_cvts_biasph_bf8(__mmask8 __U, __m128i __A, __m128h __B) {
133
119
  return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_128_mask(
134
120
  (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
135
121
  (__mmask8)__U);
136
122
  }
137
123
 
138
124
  static __inline__ __m128i __DEFAULT_FN_ATTRS256
139
- _mm256_cvtbiassph_bf8(__m256i __A, __m256h __B) {
125
+ _mm256_cvts_biasph_bf8(__m256i __A, __m256h __B) {
140
126
  return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(
141
127
  (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)_mm_undefined_si128(),
142
128
  (__mmask16)-1);
143
129
  }
144
130
 
145
- static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_bf8(
131
+ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts_biasph_bf8(
146
132
  __m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
147
133
  return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(
148
134
  (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
149
135
  }
150
136
 
151
137
  static __inline__ __m128i __DEFAULT_FN_ATTRS256
152
- _mm256_maskz_cvtbiassph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
138
+ _mm256_maskz_cvts_biasph_bf8(__mmask16 __U, __m256i __A, __m256h __B) {
153
139
  return (__m128i)__builtin_ia32_vcvtbiasph2bf8s_256_mask(
154
140
  (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
155
141
  (__mmask16)__U);
@@ -195,39 +181,39 @@ _mm256_maskz_cvtbiasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
195
181
  }
196
182
 
197
183
  static __inline__ __m128i __DEFAULT_FN_ATTRS128
198
- _mm_cvtbiassph_hf8(__m128i __A, __m128h __B) {
184
+ _mm_cvts_biasph_hf8(__m128i __A, __m128h __B) {
199
185
  return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(
200
186
  (__v16qi)__A, (__v8hf)__B, (__v16qi)_mm_undefined_si128(), (__mmask8)-1);
201
187
  }
202
188
 
203
189
  static __inline__ __m128i __DEFAULT_FN_ATTRS128
204
- _mm_mask_cvtbiassph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
190
+ _mm_mask_cvts_biasph_hf8(__m128i __W, __mmask8 __U, __m128i __A, __m128h __B) {
205
191
  return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(
206
192
  (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)__W, (__mmask8)__U);
207
193
  }
208
194
 
209
195
  static __inline__ __m128i __DEFAULT_FN_ATTRS128
210
- _mm_maskz_cvtbiassph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
196
+ _mm_maskz_cvts_biasph_hf8(__mmask8 __U, __m128i __A, __m128h __B) {
211
197
  return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_128_mask(
212
198
  (__v16qi)__A, (__v8hf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
213
199
  (__mmask8)__U);
214
200
  }
215
201
 
216
202
  static __inline__ __m128i __DEFAULT_FN_ATTRS256
217
- _mm256_cvtbiassph_hf8(__m256i __A, __m256h __B) {
203
+ _mm256_cvts_biasph_hf8(__m256i __A, __m256h __B) {
218
204
  return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(
219
205
  (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)_mm_undefined_si128(),
220
206
  (__mmask16)-1);
221
207
  }
222
208
 
223
- static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvtbiassph_hf8(
209
+ static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_mask_cvts_biasph_hf8(
224
210
  __m128i __W, __mmask16 __U, __m256i __A, __m256h __B) {
225
211
  return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(
226
212
  (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)__W, (__mmask16)__U);
227
213
  }
228
214
 
229
215
  static __inline__ __m128i __DEFAULT_FN_ATTRS256
230
- _mm256_maskz_cvtbiassph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
216
+ _mm256_maskz_cvts_biasph_hf8(__mmask16 __U, __m256i __A, __m256h __B) {
231
217
  return (__m128i)__builtin_ia32_vcvtbiasph2hf8s_256_mask(
232
218
  (__v32qi)__A, (__v16hf)__B, (__v16qi)(__m128i)_mm_setzero_si128(),
233
219
  (__mmask16)__U);
@@ -270,40 +256,40 @@ _mm256_maskz_cvt2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
270
256
  (__v32qi)(__m256i)_mm256_setzero_si256());
271
257
  }
272
258
 
273
- static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvts2ph_bf8(__m128h __A,
274
- __m128h __B) {
259
+ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvts_2ph_bf8(__m128h __A,
260
+ __m128h __B) {
275
261
  return (__m128i)__builtin_ia32_vcvt2ph2bf8s_128((__v8hf)(__A), (__v8hf)(__B));
276
262
  }
277
263
 
278
264
  static __inline__ __m128i __DEFAULT_FN_ATTRS128
279
- _mm_mask_cvts2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
265
+ _mm_mask_cvts_2ph_bf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
280
266
  return (__m128i)__builtin_ia32_selectb_128(
281
- (__mmask16)__U, (__v16qi)_mm_cvts2ph_bf8(__A, __B), (__v16qi)__W);
267
+ (__mmask16)__U, (__v16qi)_mm_cvts_2ph_bf8(__A, __B), (__v16qi)__W);
282
268
  }
283
269
 
284
270
  static __inline__ __m128i __DEFAULT_FN_ATTRS128
285
- _mm_maskz_cvts2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
271
+ _mm_maskz_cvts_2ph_bf8(__mmask16 __U, __m128h __A, __m128h __B) {
286
272
  return (__m128i)__builtin_ia32_selectb_128(
287
- (__mmask16)__U, (__v16qi)_mm_cvts2ph_bf8(__A, __B),
273
+ (__mmask16)__U, (__v16qi)_mm_cvts_2ph_bf8(__A, __B),
288
274
  (__v16qi)(__m128i)_mm_setzero_si128());
289
275
  }
290
276
 
291
277
  static __inline__ __m256i __DEFAULT_FN_ATTRS256
292
- _mm256_cvts2ph_bf8(__m256h __A, __m256h __B) {
278
+ _mm256_cvts_2ph_bf8(__m256h __A, __m256h __B) {
293
279
  return (__m256i)__builtin_ia32_vcvt2ph2bf8s_256((__v16hf)(__A),
294
280
  (__v16hf)(__B));
295
281
  }
296
282
 
297
283
  static __inline__ __m256i __DEFAULT_FN_ATTRS256
298
- _mm256_mask_cvts2ph_bf8(__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
284
+ _mm256_mask_cvts_2ph_bf8(__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
299
285
  return (__m256i)__builtin_ia32_selectb_256(
300
- (__mmask32)__U, (__v32qi)_mm256_cvts2ph_bf8(__A, __B), (__v32qi)__W);
286
+ (__mmask32)__U, (__v32qi)_mm256_cvts_2ph_bf8(__A, __B), (__v32qi)__W);
301
287
  }
302
288
 
303
289
  static __inline__ __m256i __DEFAULT_FN_ATTRS256
304
- _mm256_maskz_cvts2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
290
+ _mm256_maskz_cvts_2ph_bf8(__mmask32 __U, __m256h __A, __m256h __B) {
305
291
  return (__m256i)__builtin_ia32_selectb_256(
306
- (__mmask32)__U, (__v32qi)_mm256_cvts2ph_bf8(__A, __B),
292
+ (__mmask32)__U, (__v32qi)_mm256_cvts_2ph_bf8(__A, __B),
307
293
  (__v32qi)(__m256i)_mm256_setzero_si256());
308
294
  }
309
295
 
@@ -344,40 +330,40 @@ _mm256_maskz_cvt2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
344
330
  (__v32qi)(__m256i)_mm256_setzero_si256());
345
331
  }
346
332
 
347
- static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvts2ph_hf8(__m128h __A,
348
- __m128h __B) {
333
+ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvts_2ph_hf8(__m128h __A,
334
+ __m128h __B) {
349
335
  return (__m128i)__builtin_ia32_vcvt2ph2hf8s_128((__v8hf)(__A), (__v8hf)(__B));
350
336
  }
351
337
 
352
338
  static __inline__ __m128i __DEFAULT_FN_ATTRS128
353
- _mm_mask_cvts2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
339
+ _mm_mask_cvts_2ph_hf8(__m128i __W, __mmask16 __U, __m128h __A, __m128h __B) {
354
340
  return (__m128i)__builtin_ia32_selectb_128(
355
- (__mmask16)__U, (__v16qi)_mm_cvts2ph_hf8(__A, __B), (__v16qi)__W);
341
+ (__mmask16)__U, (__v16qi)_mm_cvts_2ph_hf8(__A, __B), (__v16qi)__W);
356
342
  }
357
343
 
358
344
  static __inline__ __m128i __DEFAULT_FN_ATTRS128
359
- _mm_maskz_cvts2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
345
+ _mm_maskz_cvts_2ph_hf8(__mmask16 __U, __m128h __A, __m128h __B) {
360
346
  return (__m128i)__builtin_ia32_selectb_128(
361
- (__mmask16)__U, (__v16qi)_mm_cvts2ph_hf8(__A, __B),
347
+ (__mmask16)__U, (__v16qi)_mm_cvts_2ph_hf8(__A, __B),
362
348
  (__v16qi)(__m128i)_mm_setzero_si128());
363
349
  }
364
350
 
365
351
  static __inline__ __m256i __DEFAULT_FN_ATTRS256
366
- _mm256_cvts2ph_hf8(__m256h __A, __m256h __B) {
352
+ _mm256_cvts_2ph_hf8(__m256h __A, __m256h __B) {
367
353
  return (__m256i)__builtin_ia32_vcvt2ph2hf8s_256((__v16hf)(__A),
368
354
  (__v16hf)(__B));
369
355
  }
370
356
 
371
357
  static __inline__ __m256i __DEFAULT_FN_ATTRS256
372
- _mm256_mask_cvts2ph_hf8(__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
358
+ _mm256_mask_cvts_2ph_hf8(__m256i __W, __mmask32 __U, __m256h __A, __m256h __B) {
373
359
  return (__m256i)__builtin_ia32_selectb_256(
374
- (__mmask32)__U, (__v32qi)_mm256_cvts2ph_hf8(__A, __B), (__v32qi)__W);
360
+ (__mmask32)__U, (__v32qi)_mm256_cvts_2ph_hf8(__A, __B), (__v32qi)__W);
375
361
  }
376
362
 
377
363
  static __inline__ __m256i __DEFAULT_FN_ATTRS256
378
- _mm256_maskz_cvts2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
364
+ _mm256_maskz_cvts_2ph_hf8(__mmask32 __U, __m256h __A, __m256h __B) {
379
365
  return (__m256i)__builtin_ia32_selectb_256(
380
- (__mmask32)__U, (__v32qi)_mm256_cvts2ph_hf8(__A, __B),
366
+ (__mmask32)__U, (__v32qi)_mm256_cvts_2ph_hf8(__A, __B),
381
367
  (__v32qi)(__m256i)_mm256_setzero_si256());
382
368
  }
383
369
 
@@ -449,36 +435,37 @@ _mm256_maskz_cvtph_bf8(__mmask16 __U, __m256h __A) {
449
435
  (__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
450
436
  }
451
437
 
452
- static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_bf8(__m128h __A) {
438
+ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvts_ph_bf8(__m128h __A) {
453
439
  return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask(
454
440
  (__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
455
441
  }
456
442
 
457
443
  static __inline__ __m128i __DEFAULT_FN_ATTRS128
458
- _mm_mask_cvtsph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
444
+ _mm_mask_cvts_ph_bf8(__m128i __W, __mmask8 __U, __m128h __A) {
459
445
  return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask(
460
446
  (__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
461
447
  }
462
448
 
463
449
  static __inline__ __m128i __DEFAULT_FN_ATTRS128
464
- _mm_maskz_cvtsph_bf8(__mmask8 __U, __m128h __A) {
450
+ _mm_maskz_cvts_ph_bf8(__mmask8 __U, __m128h __A) {
465
451
  return (__m128i)__builtin_ia32_vcvtph2bf8s_128_mask(
466
452
  (__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
467
453
  }
468
454
 
469
- static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtsph_bf8(__m256h __A) {
455
+ static __inline__ __m128i __DEFAULT_FN_ATTRS256
456
+ _mm256_cvts_ph_bf8(__m256h __A) {
470
457
  return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask(
471
458
  (__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);
472
459
  }
473
460
 
474
461
  static __inline__ __m128i __DEFAULT_FN_ATTRS256
475
- _mm256_mask_cvtsph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
462
+ _mm256_mask_cvts_ph_bf8(__m128i __W, __mmask16 __U, __m256h __A) {
476
463
  return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask(
477
464
  (__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
478
465
  }
479
466
 
480
467
  static __inline__ __m128i __DEFAULT_FN_ATTRS256
481
- _mm256_maskz_cvtsph_bf8(__mmask16 __U, __m256h __A) {
468
+ _mm256_maskz_cvts_ph_bf8(__mmask16 __U, __m256h __A) {
482
469
  return (__m128i)__builtin_ia32_vcvtph2bf8s_256_mask(
483
470
  (__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
484
471
  }
@@ -517,36 +504,37 @@ _mm256_maskz_cvtph_hf8(__mmask16 __U, __m256h __A) {
517
504
  (__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
518
505
  }
519
506
 
520
- static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvtsph_hf8(__m128h __A) {
507
+ static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_cvts_ph_hf8(__m128h __A) {
521
508
  return (__m128i)__builtin_ia32_vcvtph2hf8s_128_mask(
522
509
  (__v8hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask8)-1);
523
510
  }
524
511
 
525
512
  static __inline__ __m128i __DEFAULT_FN_ATTRS128
526
- _mm_mask_cvtsph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
513
+ _mm_mask_cvts_ph_hf8(__m128i __W, __mmask8 __U, __m128h __A) {
527
514
  return (__m128i)__builtin_ia32_vcvtph2hf8s_128_mask(
528
515
  (__v8hf)__A, (__v16qi)(__m128i)__W, (__mmask8)__U);
529
516
  }
530
517
 
531
518
  static __inline__ __m128i __DEFAULT_FN_ATTRS128
532
- _mm_maskz_cvtsph_hf8(__mmask8 __U, __m128h __A) {
519
+ _mm_maskz_cvts_ph_hf8(__mmask8 __U, __m128h __A) {
533
520
  return (__m128i)__builtin_ia32_vcvtph2hf8s_128_mask(
534
521
  (__v8hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask8)__U);
535
522
  }
536
523
 
537
- static __inline__ __m128i __DEFAULT_FN_ATTRS256 _mm256_cvtsph_hf8(__m256h __A) {
524
+ static __inline__ __m128i __DEFAULT_FN_ATTRS256
525
+ _mm256_cvts_ph_hf8(__m256h __A) {
538
526
  return (__m128i)__builtin_ia32_vcvtph2hf8s_256_mask(
539
527
  (__v16hf)__A, (__v16qi)(__m128i)_mm_undefined_si128(), (__mmask16)-1);
540
528
  }
541
529
 
542
530
  static __inline__ __m128i __DEFAULT_FN_ATTRS256
543
- _mm256_mask_cvtsph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
531
+ _mm256_mask_cvts_ph_hf8(__m128i __W, __mmask16 __U, __m256h __A) {
544
532
  return (__m128i)__builtin_ia32_vcvtph2hf8s_256_mask(
545
533
  (__v16hf)__A, (__v16qi)(__m128i)__W, (__mmask16)__U);
546
534
  }
547
535
 
548
536
  static __inline__ __m128i __DEFAULT_FN_ATTRS256
549
- _mm256_maskz_cvtsph_hf8(__mmask16 __U, __m256h __A) {
537
+ _mm256_maskz_cvts_ph_hf8(__mmask16 __U, __m256h __A) {
550
538
  return (__m128i)__builtin_ia32_vcvtph2hf8s_256_mask(
551
539
  (__v16hf)__A, (__v16qi)(__m128i)_mm_setzero_si128(), (__mmask16)__U);
552
540
  }
package/lib/clang/20/include/avx10_2minmaxintrin.h CHANGED
@@ -80,21 +80,6 @@
80
80
  (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \
81
81
  (__v4df)_mm256_setzero_pd(), (__mmask8)(U), _MM_FROUND_NO_EXC))
82
82
 
83
- #define _mm256_minmax_round_pd(A, B, C, R) \
84
- ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \
85
- (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \
86
- (__v4df)_mm256_undefined_pd(), (__mmask8)-1, (int)(R)))
87
-
88
- #define _mm256_mask_minmax_round_pd(W, U, A, B, C, R) \
89
- ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \
90
- (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \
91
- (__v4df)(__m256d)(W), (__mmask8)(U), (int)(R)))
92
-
93
- #define _mm256_maskz_minmax_round_pd(U, A, B, C, R) \
94
- ((__m256d)__builtin_ia32_vminmaxpd256_round_mask( \
95
- (__v4df)(__m256d)(A), (__v4df)(__m256d)(B), (int)(C), \
96
- (__v4df)_mm256_setzero_pd(), (__mmask8)(U), (int)(R)))
97
-
98
83
  #define _mm_minmax_ph(A, B, C) \
99
84
  ((__m128h)__builtin_ia32_vminmaxph128_mask( \
100
85
  (__v8hf)(__m128h)(A), (__v8hf)(__m128h)(B), (int)(C), \
@@ -125,21 +110,6 @@
125
110
  (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (int)(C), \
126
111
  (__v16hf)_mm256_setzero_ph(), (__mmask16)(U), _MM_FROUND_NO_EXC))
127
112
 
128
- #define _mm256_minmax_round_ph(A, B, C, R) \
129
- ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \
130
- (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (int)(C), \
131
- (__v16hf)_mm256_undefined_ph(), (__mmask16)-1, (int)(R)))
132
-
133
- #define _mm256_mask_minmax_round_ph(W, U, A, B, C, R) \
134
- ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \
135
- (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (C), \
136
- (__v16hf)(__m256h)(W), (__mmask16)(U), (int)(R)))
137
-
138
- #define _mm256_maskz_minmax_round_ph(U, A, B, C, R) \
139
- ((__m256h)__builtin_ia32_vminmaxph256_round_mask( \
140
- (__v16hf)(__m256h)(A), (__v16hf)(__m256h)(B), (int)(C), \
141
- (__v16hf)_mm256_setzero_ph(), (__mmask16)(U), (int)(R)))
142
-
143
113
  #define _mm_minmax_ps(A, B, C) \
144
114
  ((__m128)__builtin_ia32_vminmaxps128_mask( \
145
115
  (__v4sf)(__m128)(A), (__v4sf)(__m128)(B), (int)(C), \
@@ -170,21 +140,6 @@
170
140
  (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), \
171
141
  (__v8sf)_mm256_setzero_ps(), (__mmask8)(U), _MM_FROUND_NO_EXC))
172
142
 
173
- #define _mm256_minmax_round_ps(A, B, C, R) \
174
- ((__m256)__builtin_ia32_vminmaxps256_round_mask( \
175
- (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), \
176
- (__v8sf)_mm256_undefined_ps(), (__mmask8)-1, (int)(R)))
177
-
178
- #define _mm256_mask_minmax_round_ps(W, U, A, B, C, R) \
179
- ((__m256)__builtin_ia32_vminmaxps256_round_mask( \
180
- (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), (__v8sf)(__m256)(W), \
181
- (__mmask8)(U), (int)(R)))
182
-
183
- #define _mm256_maskz_minmax_round_ps(U, A, B, C, R) \
184
- ((__m256)__builtin_ia32_vminmaxps256_round_mask( \
185
- (__v8sf)(__m256)(A), (__v8sf)(__m256)(B), (int)(C), \
186
- (__v8sf)_mm256_setzero_ps(), (__mmask8)(U), (int)(R)))
187
-
188
143
  #define _mm_minmax_sd(A, B, C) \
189
144
  ((__m128d)__builtin_ia32_vminmaxsd_round_mask( \
190
145
  (__v2df)(__m128d)(A), (__v2df)(__m128d)(B), (int)(C), \