@codingame/monaco-editor-wrapper 1.5.0 → 1.8.0

package/dist/systemverilog.tmLanguage.js

@@ -1,30 +1,114 @@
+var name = "SystemVerilog";
+var scopeName = "source.systemverilog";
 var fileTypes = [
-	"sv",
-	"SV",
 	"v",
-	"V",
-	"svh",
-	"SVH",
 	"vh",
-	"VH"
+	"sv",
+	"svh"
 ];
-var hidden = true;
-var name = "SystemVerilog";
 var patterns = [
 	{
-		begin: "\\s*\\b(function|task)\\b(\\s+automatic)?",
+		include: "#comments"
+	},
+	{
+		include: "#strings"
+	},
+	{
+		include: "#parameter"
+	},
+	{
+		include: "#port-declaration"
+	},
+	{
+		include: "#module-declaration"
+	},
+	{
+		include: "#class-declaration"
+	},
+	{
+		include: "#function-task"
+	},
+	{
+		include: "#sequence"
+	},
+	{
+		include: "#keywords"
+	},
+	{
+		include: "#all-types"
+	},
+	{
+		include: "#module-parameters"
+	},
+	{
+		include: "#module-no-parameters"
+	},
+	{
+		include: "#system-tf"
+	},
+	{
+		include: "#typedef-complex"
+	},
+	{
+		include: "#typedef-simple"
+	},
+	{
+		include: "#assertion"
+	},
+	{
+		include: "#bind-directive"
+	},
+	{
+		include: "#cast-operator"
+	},
+	{
+		include: "#storage-scope"
+	},
+	{
+		include: "#attributes"
+	},
+	{
+		include: "#imports"
+	},
+	{
+		include: "#operators"
+	},
+	{
+		include: "#constants"
+	},
+	{
+		include: "#functions"
+	},
+	{
+		include: "#identifiers"
+	},
+	{
+		include: "#selects"
+	}
+];
+var repository = {
+	"function-task": {
+		begin: "[ \\t\\n]*(?:\\b(virtual)[ \\t\\n]+)?(?:\\b(function|task)\\b)(?:[ \\t\\n]+\\b(static|automatic)\\b)?",
 		beginCaptures: {
 			"1": {
-				name: "keyword.control.systemverilog"
+				name: "storage.modifier.systemverilog"
 			},
 			"2": {
-				name: "keyword.control.systemverilog"
+				name: "storage.type.function.systemverilog"
+			},
+			"3": {
+				name: "storage.modifier.systemverilog"
 			}
 		},
 		end: ";",
+		endCaptures: {
+			"0": {
+				name: "punctuation.definition.function.end.systemverilog"
+			}
+		},
 		patterns: [
 			{
-				match: "\\b([a-zA-Z_][a-zA-Z0-9_]*\\s+)?([a-zA-Z_][a-zA-Z0-9_:]*)\\s*(?=\\(|;)",
+				match: "\\b([a-zA-Z_][a-zA-Z0-9_$]*[ \\t\\n]+)?([a-zA-Z_][a-zA-Z0-9_:]*)[ \\t\\n]*(?=\\(|;)",
 				captures: {
 					"1": {
 						name: "storage.type.systemverilog"
@@ -35,31 +119,22 @@ var patterns = [
 				}
 			},
 			{
-				include: "#port-dir"
+				include: "#port-declaration"
+			},
+			{
+				include: "#keywords"
 			},
 			{
 				include: "#base-grammar"
+			},
+			{
+				include: "#identifiers"
 			}
 		],
 		name: "meta.function.systemverilog"
 	},
-	{
-		match: "\\s*\\b(task)\\s+(automatic)?\\s*(\\w+)\\s*;",
-		captures: {
-			"1": {
-				name: "keyword.control.systemverilog"
-			},
-			"2": {
-				name: "keyword.control.systemverilog"
-			},
-			"3": {
-				name: "entity.name.function.systemverilog"
-			}
-		},
-		name: "meta.task.simple.systemverilog"
-	},
-	{
-		begin: "\\s*\\b(typedef\\s+(struct|enum|union)\\b)\\s*(packed)?\\s*([a-zA-Z_][a-zA-Z0-9_]*)?",
+	"typedef-complex": {
+		begin: "[ \\t\\n]*\\b(typedef)[ \\t\\n]+(enum|struct|union|class|interface[ \\t\\n]+class)(?:[ \\t\\n]+(packed))?(?:[ \\t\\n]+([a-zA-Z_][a-zA-Z0-9_$]*)(?=[ \\t\\n]*(\\[[a-zA-Z0-9_:$\\-\\+` \\t\\n\\[\\]]*\\])?))?(?=[ \\t\\n]*{)",
 		beginCaptures: {
 			"1": {
 				name: "keyword.control.systemverilog"
@@ -74,53 +149,58 @@ var patterns = [
 				name: "storage.type.systemverilog"
 			}
 		},
-		end: "(})\\s*([a-zA-Z_][a-zA-Z0-9_]*)\\s*;",
+		end: "(?<=})(?:[ \\t\\n]*([a-zA-Z_][a-zA-Z0-9_$]*))(?:[ \\t\\n]*(\\[[a-zA-Z0-9_:$\\-\\+` \\t\\n\\[\\]]*\\])?)[ \\t\\n]*;",
 		endCaptures: {
 			"1": {
-				name: "keyword.operator.other.systemverilog"
+				name: "storage.type.systemverilog"
 			},
 			"2": {
-				name: "entity.name.function.systemverilog"
+				patterns: [
+					{
+						include: "#selects"
+					}
+				]
 			}
 		},
 		patterns: [
 			{
-				include: "#struct-anonymous"
+				include: "#keywords"
 			},
 			{
 				include: "#base-grammar"
+			},
+			{
+				include: "#identifiers"
 			}
 		],
-		name: "meta.typedef.struct.systemverilog"
+		name: "meta.typedef.complex.systemverilog"
 	},
-	{
-		match: "\\s*\\b(typedef\\s+class)\\s+([a-zA-Z_][a-zA-Z0-9_]*)\\s*;",
-		captures: {
+	"typedef-simple": {
+		begin: "[ \\t\\n]*\\b(typedef)[ \\t\\n]+(enum|struct|union|class|interface[ \\t\\n]+class)\\b",
+		beginCaptures: {
 			"1": {
 				name: "keyword.control.systemverilog"
 			},
 			"2": {
-				name: "entity.name.declaration.systemverilog"
-			}
-		},
-		name: "meta.typedef.class.systemverilog"
-	},
-	{
-		begin: "\\s*\\b(typedef)\\b",
-		beginCaptures: {
-			"1": {
 				name: "keyword.control.systemverilog"
 			}
 		},
-		end: "([a-zA-Z_][a-zA-Z0-9_]*)\\s*(?=(\\[[a-zA-Z0-9_:\\$\\-\\+]*\\])?;)",
+		end: "(?:[ \\t\\n]*([a-zA-Z_][a-zA-Z0-9_$]*))(?:[ \\t\\n]*(\\[[a-zA-Z0-9_:$\\-\\+` \\t\\n\\[\\]]*\\])?)[ \\t\\n]*;",
 		endCaptures: {
 			"1": {
-				name: "entity.name.function.systemverilog"
+				name: "storage.type.systemverilog"
+			},
+			"2": {
+				patterns: [
+					{
+						include: "#selects"
+					}
+				]
 			}
 		},
 		patterns: [
 			{
-				match: "\\b([a-zA-Z_]\\w*)\\s*(#)\\(",
+				match: "[ \\t\\n]+\\b([a-zA-Z_][a-zA-Z0-9_$]*)[ \\t\\n]*(#)\\(",
 				captures: {
 					"1": {
 						name: "storage.type.userdefined.systemverilog"
@@ -136,48 +216,56 @@ var patterns = [
 			},
 			{
 				include: "#module-binding"
+			},
+			{
+				include: "#identifiers"
 			}
 		],
 		name: "meta.typedef.simple.systemverilog"
 	},
-	{
-		begin: "\\s*(module)\\s+\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
+	"module-declaration": {
+		begin: "[ \\t\\n]*\\b((?:macro)?module|interface|program|package)[ \\t\\n]+(?:(static|automatic)[ \\t\\n]+)?([a-zA-Z_][a-zA-Z0-9_$]*)\\b",
 		beginCaptures: {
 			"1": {
 				name: "keyword.control.systemverilog"
 			},
 			"2": {
+				name: "storage.modifier.systemverilog"
+			},
+			"3": {
 				name: "entity.name.type.module.systemverilog"
 			}
 		},
 		end: ";",
 		endCaptures: {
-			"1": {
-				name: "entity.name.function.systemverilog"
+			"0": {
+				name: "punctuation.definition.module.end.systemverilog"
 			}
 		},
 		patterns: [
 			{
-				include: "#port-dir"
+				include: "#parameter"
 			},
 			{
-				match: "\\s*(parameter)",
-				name: "keyword.other.systemverilog"
+				include: "#port-declaration"
 			},
 			{
-				include: "#base-grammar"
+				include: "#interface-port"
+			},
+			{
+				include: "#imports"
 			},
 			{
-				include: "#ifmodport"
+				include: "#base-grammar"
 			},
 			{
-				match: "\\$\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
-				name: "support.function.systemverilog"
+				include: "#identifiers"
 			}
 		],
 		name: "meta.module.systemverilog"
 	},
-	{
+	sequence: {
+		match: "[ \\t\\n]*\\b(sequence)[ \\t\\n]+([a-zA-Z_][a-zA-Z0-9_$]*)\\b",
 		captures: {
 			"1": {
 				name: "keyword.control.systemverilog"
@@ -186,51 +274,25 @@ var patterns = [
 				name: "entity.name.function.systemverilog"
 			}
 		},
-		match: "\\b(sequence)\\s+([a-zA-Z_][a-zA-Z0-9_]*)",
 		name: "meta.sequence.systemverilog"
 	},
-	{
-		match: "\\b(bind)\\s+([a-zA-Z_][a-zA-Z0-9_\\.]*)\\b",
+	"bind-directive": {
+		match: "[ \\t\\n]*\\b(bind)[ \\t\\n]+([a-zA-Z_][a-zA-Z0-9_$\\.]*)\\b",
 		captures: {
 			"1": {
 				name: "keyword.control.systemverilog"
-			}
-		}
-	},
-	{
-		captures: {
-			"0": {
-				name: "meta.section.begin.systemverilog"
-			},
-			"1": {
-				name: "keyword.other.block.systemverilog"
 			},
-			"3": {
-				name: "keyword.operator.systemverilog"
-			},
-			"4": {
-				name: "entity.name.section.systemverilog"
+			"2": {
+				name: "entity.name.type.module.systemverilog"
 			}
 		},
-		match: "\\s*(begin|fork)\\s*((:)\\s*([a-zA-Z_][a-zA-Z0-9_]*))\\b",
 		name: "meta.definition.systemverilog"
 	},
-	{
-		match: "\\b(property)\\s+(\\w+)",
+	assertion: {
+		match: "\\b([a-zA-Z_][a-zA-Z0-9_$]*)[ \\t\\n]*(:)[ \\t\\n]*(assert|assume|cover|restrict)\\b",
 		captures: {
 			"1": {
-				name: "keyword.sva.systemverilog"
-			},
-			"2": {
-				name: "entity.name.sva.systemverilog"
-			}
-		}
-	},
-	{
-		match: "\\b(\\w+)\\s*(:)\\s*(assert)\\b",
-		captures: {
-			"1": {
-				name: "entity.name.sva.systemverilog"
+				name: "entity.name.goto-label.php"
 			},
 			"2": {
 				name: "keyword.operator.systemverilog"
@@ -240,173 +302,144 @@ var patterns = [
 			}
 		}
 	},
-	{
-		begin: "\\s*(//)\\s*(psl)\\s+((\\w+)\\s*(:))?\\s*(default|assert|assume)",
-		beginCaptures: {
-			"0": {
-				name: "meta.psl.systemverilog"
-			},
-			"1": {
-				name: "comment.line.double-slash.systemverilog"
-			},
-			"2": {
-				name: "keyword.psl.systemverilog"
-			},
-			"4": {
-				name: "entity.psl.name.systemverilog"
-			},
-			"5": {
-				name: "keyword.operator.systemverilog"
-			},
-			"6": {
-				name: "keyword.psl.systemverilog"
-			}
-		},
-		end: ";",
+	"compiler-directives": {
 		patterns: [
 			{
-				match: "\\b(never|always|default|clock|within|rose|fell|stable|until|before|next|eventually|abort|posedge)\\b",
-				name: "keyword.psl.systemverilog"
-			},
-			{
-				include: "#operators"
-			},
-			{
-				include: "#functions"
-			},
-			{
-				include: "#constants"
-			}
-		],
-		name: "meta.psl.systemverilog"
-	},
-	{
-		begin: "\\s*(/\\*)\\s*(psl)",
-		beginCaptures: {
-			"0": {
-				name: "meta.psl.systemverilog"
-			},
-			"1": {
-				name: "comment.block.systemverilog"
+				match: "(`)(else|endif|endcelldefine|celldefine|nounconnected_drive|resetall|undefineall|end_keywords|__FILE__|__LINE__)\\b",
+				captures: {
+					"1": {
+						name: "punctuation.definition.directive.systemverilog"
+					},
+					"2": {
+						name: "string.regexp.systemverilog"
+					}
+				}
 			},
-			"2": {
-				name: "keyword.psl.systemverilog"
-			}
-		},
-		end: "(\\*/)",
-		endCaptures: {
-			"1": {
-				name: "comment.block.systemverilog"
-			}
-		},
-		patterns: [
 			{
-				match: "^\\s*((\\w+)\\s*(:))?\\s*(default|assert|assume)",
+				match: "(`)(ifdef|ifndef|elsif|define|undef|pragma)[ \\t\\n]+([a-zA-Z_][a-zA-Z0-9_$]*)\\b",
 				captures: {
-					"0": {
-						name: "meta.psl.systemverilog"
+					"1": {
+						name: "punctuation.definition.directive.systemverilog"
 					},
 					"2": {
-						name: "entity.psl.name.systemverilog"
+						name: "string.regexp.systemverilog"
 					},
 					"3": {
-						name: "keyword.operator.systemverilog"
+						name: "entity.name.function.preprocessor.systemverilog"
+					}
+				}
+			},
+			{
+				match: "(`)(include|timescale|default_nettype|unconnected_drive|line|begin_keywords)\\b",
+				captures: {
+					"1": {
+						name: "punctuation.definition.directive.systemverilog"
 					},
-					"4": {
-						name: "keyword.psl.systemverilog"
+					"2": {
+						name: "string.regexp.systemverilog"
 					}
 				}
 			},
 			{
-				match: "\\b(property)\\s+(\\w+)",
+				match: "(`)([a-zA-Z_][a-zA-Z0-9_$]*)\\b",
 				captures: {
 					"1": {
-						name: "keyword.psl.systemverilog"
+						name: "punctuation.definition.directive.systemverilog"
 					},
 					"2": {
-						name: "entity.psl.name.systemverilog"
+						name: "entity.name.function.preprocessor.systemverilog"
+					}
+				}
+			}
+		],
+		name: "meta.preprocessor.systemverilog"
+	},
+	keywords: {
+		patterns: [
+			{
+				match: "\\b(edge|negedge|posedge|cell|config|deassign|defparam|design|disable|endgenerate|endspecify|endtable|event|generate|genvar|ifnone|incdir|instance|liblist|library|noshowcancelled|pulsestyle_onevent|pulsestyle_ondetect|scalared|showcancelled|specify|specparam|table|use|vectored)\\b",
+				captures: {
+					"1": {
+						name: "keyword.other.systemverilog"
 					}
 				}
 			},
 			{
-				match: "\\b(never|always|default|clock|within|rose|fell|stable|until|before|next|eventually|abort|posedge|negedge)\\b",
-				name: "keyword.psl.systemverilog"
+				include: "#sv-control"
 			},
 			{
-				include: "#operators"
+				include: "#sv-control-begin"
 			},
 			{
-				include: "#functions"
+				include: "#sv-control-end"
 			},
 			{
-				include: "#constants"
-			}
-		],
-		name: "meta.psl.systemverilog"
-	},
-	{
-		match: "\\s*\\b(automatic|cell|config|deassign|defparam|design|disable|edge|endconfig|endgenerate|endspecify|endtable|event|generate|genvar|ifnone|incdir|instance|liblist|library|macromodule|negedge|noshowcancelled|posedge|pulsestyle_onevent|pulsestyle_ondetect|scalared|showcancelled|specify|specparam|table|use|vectored)\\b",
-		captures: {
-			"1": {
-				name: "keyword.other.systemverilog"
+				include: "#sv-definition"
+			},
+			{
+				include: "#sv-cover-cross"
+			},
+			{
+				include: "#sv-std"
+			},
+			{
+				include: "#sv-option"
+			},
+			{
+				include: "#sv-local"
+			},
+			{
+				include: "#sv-rand"
+			},
+			{
+				include: "#sv-support"
 			}
-		}
+		]
 	},
-	{
-		match: "\\s*\\b(initial|always|wait|force|release|assign|always_comb|always_ff|always_latch|forever|repeat|while|for|if|iff|else|case|casex|casez|default|endcase|return|break|continue|do|foreach|with|inside|dist|clocking|cover|coverpoint|property|bins|binsof|illegal_bins|ignore_bins|randcase|modport|matches|solve|static|assert|assume|before|expect|cross|ref|first_match|srandom|struct|packed|final|chandle|alias|tagged|extern|throughout|timeprecision|timeunit|priority|type|union|uwire|wait_order|triggered|randsequence|import|export|context|pure|intersect|wildcard|within|new|typedef|enum|this|super|begin|fork|forkjoin|unique|unique0|priority)\\b",
+	"sv-control": {
+		match: "[ \\t\\n]*\\b(initial|wait|force|release|assign|always|always_comb|always_ff|always_latch|forever|repeat|while|for|if|iff|else|case|casex|casez|default|endcase|return|break|continue|do|foreach|with|clocking|coverpoint|property|bins|binsof|illegal_bins|ignore_bins|randcase|modport|matches|solve|before|expect|cross|ref|first_match|srandom|struct|packed|final|chandle|alias|tagged|extern|throughout|timeprecision|timeunit|priority|type|union|uwire|wait_order|triggered|randsequence|context|pure|intersect|wildcard|typedef|new|forkjoin|unique|unique0|priority)\\b",
 		captures: {
 			"1": {
 				name: "keyword.control.systemverilog"
 			}
 		}
 	},
-	{
-		match: "\\s*\\b(end|endtask|endmodule|endfunction|endprimitive|endclass|endpackage|endsequence|endprogram|endclocking|endproperty|endgroup|endinterface|join|join_any|join_none)\\b(\\s*(:)\\s*(\\w+))?",
+	"sv-control-begin": {
+		match: "[ \\t\\n]*\\b(begin|fork)\\b(?:[ \\t\\n]*(:)[ \\t\\n]*([a-zA-Z_][a-zA-Z0-9_$]*))?",
 		captures: {
 			"1": {
 				name: "keyword.control.systemverilog"
 			},
-			"3": {
-				name: "keyword.operator.systemverilog"
+			"2": {
+				name: "punctuation.definition.label.systemverilog"
 			},
-			"4": {
-				name: "entity.label.systemverilog"
+			"3": {
+				name: "entity.name.section.systemverilog"
 			}
 		},
-		name: "meta.object.end.systemverilog"
+		name: "meta.item.begin.systemverilog"
 	},
-	{
-		match: "\\b(std)\\b::",
-		name: "support.class.systemverilog"
-	},
-	{
+	"sv-control-end": {
+		match: "[ \\t\\n]*\\b(end|endmodule|endinterface|endprogram|endchecker|endclass|endpackage|endconfig|endfunction|endtask|endproperty|endsequence|endgroup|endprimitive|endclocking|join|join_any|join_none)\\b(?:[ \\t\\n]*(:)[ \\t\\n]*([a-zA-Z_][a-zA-Z0-9_$]*))?",
 		captures: {
 			"1": {
-				name: "constant.other.define.systemverilog"
+				name: "keyword.control.systemverilog"
 			},
 			"2": {
-				name: "entity.name.type.define.systemverilog"
-			}
-		},
-		match: "^\\s*(`define)\\s+([a-zA-Z_][a-zA-Z0-9_]*)",
-		name: "meta.define.systemverilog"
-	},
-	{
-		captures: {
-			"1": {
-				name: "constant.other.undef.systemverilog"
+				name: "punctuation.definition.label.systemverilog"
 			},
-			"2": {
-				name: "entity.name.type.undef.systemverilog"
+			"3": {
+				name: "entity.name.section.systemverilog"
 			}
 		},
-		match: "^\\s*(`undef)\\s+([a-zA-Z_][a-zA-Z0-9_]*)",
-		name: "meta.undef.systemverilog"
+		name: "meta.item.end.systemverilog"
 	},
-	{
-		include: "#comments"
+	"sv-std": {
+		match: "\\b(std)\\b::",
+		name: "support.class.systemverilog"
 	},
-	{
+	"sv-definition": {
+		match: "[ \\t\\n]*\\b(primitive|package|constraint|interface|covergroup|program)[ \\t\\n]+\\b([a-zA-Z_][a-zA-Z0-9_$]*)\\b",
 		captures: {
 			"1": {
 				name: "keyword.control.systemverilog"
@@ -415,10 +448,10 @@ var patterns = [
 				name: "entity.name.type.class.systemverilog"
 			}
 		},
-		match: "\\s*(primitive|package|constraint|interface|covergroup|program)\\s+\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
 		name: "meta.definition.systemverilog"
 	},
-	{
+	"sv-cover-cross": {
+		match: "(([a-zA-Z_][a-zA-Z0-9_$]*)[ \\t\\n]*(:))?[ \\t\\n]*(coverpoint|cross)[ \\t\\n]+([a-zA-Z_][a-zA-Z0-9_$]*)",
 		captures: {
 			"2": {
 				name: "entity.name.type.class.systemverilog"
@@ -430,279 +463,288 @@ var patterns = [
 				name: "keyword.control.systemverilog"
 			}
 		},
-		match: "(([a-zA-Z_][a-zA-Z0-9_]*)\\s*(:))?\\s*(coverpoint|cross)\\s+([a-zA-Z_][a-zA-Z0-9_]*)",
 		name: "meta.definition.systemverilog"
 	},
-	{
-		captures: {
+	"class-declaration": {
+		begin: "[ \\t\\n]*\\b(virtual[ \\t\\n]+)?(class)(?:[ \\t\\n]+(static|automatic))?[ \\t\\n]+([a-zA-Z_][a-zA-Z0-9_$:]*)(?:[ \\t\\n]+(extends|implements)[ \\t\\n]+([a-zA-Z_][a-zA-Z0-9_$:]*))?",
+		beginCaptures: {
 			"1": {
-				name: "keyword.control.systemverilog"
+				name: "storage.modifier.systemverilog"
 			},
 			"2": {
-				name: "keyword.control.systemverilog"
+				name: "storage.type.class.systemverilog"
 			},
 			"3": {
+				name: "storage.modifier.systemverilog"
+			},
+			"4": {
 				name: "entity.name.type.class.systemverilog"
-			}
-		},
-		match: "\\b(virtual\\s+)?(class)\\s+\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
-		name: "meta.definition.class.systemverilog"
-	},
-	{
-		captures: {
-			"1": {
+			},
+			"5": {
 				name: "keyword.control.systemverilog"
 			},
-			"2": {
-				name: "entity.other.inherited-class.systemverilog"
+			"6": {
+				name: "entity.name.type.class.systemverilog"
 			}
 		},
-		match: "\\b(extends)\\s+([a-zA-Z_][a-zA-Z0-9_]*)\\b",
-		name: "meta.definition.systemverilog"
-	},
-	{
-		include: "#all-types"
-	},
-	{
-		include: "#operators"
-	},
-	{
-		include: "#port-dir"
+		end: ";",
+		endCaptures: {
+			"0": {
+				name: "punctuation.definition.class.end.systemverilog"
+			}
+		},
+		patterns: [
+			{
+				match: "[ \\t\\n]+\\b(extends|implements)[ \\t\\n]+([a-zA-Z_][a-zA-Z0-9_$:]*)(?:[ \\t\\n]*,[ \\t\\n]*([a-zA-Z_][a-zA-Z0-9_$:]*))*",
+				captures: {
+					"1": {
+						name: "keyword.control.systemverilog"
+					},
+					"2": {
+						name: "entity.name.type.class.systemverilog"
+					},
+					"3": {
+						name: "entity.name.type.class.systemverilog"
+					}
+				}
+			},
+			{
+				match: "[ \\t\\n]+\\b([a-zA-Z_][a-zA-Z0-9_$]*)[ \\t\\n]*(#)\\(",
+				captures: {
+					"1": {
+						name: "storage.type.userdefined.systemverilog"
+					},
+					"2": {
+						name: "keyword.operator.param.systemverilog"
+					}
+				},
+				name: "meta.typedef.class.systemverilog"
+			},
+			{
+				include: "#parameter"
+			},
+			{
+				include: "#port-declaration"
+			},
+			{
+				include: "#interface-port"
+			},
+			{
+				include: "#base-grammar"
+			},
+			{
+				include: "#module-binding"
+			},
+			{
+				include: "#identifiers"
+			}
+		],
+		name: "meta.class.systemverilog"
 	},
-	{
+	"sv-support": {
 		match: "\\b(and|nand|nor|or|xor|xnor|buf|not|bufif[01]|notif[01]|r?[npc]mos|tran|r?tranif[01]|pullup|pulldown)\\b",
 		name: "support.type.systemverilog"
 	},
-	{
-		include: "#strings"
-	},
-	{
-		match: "\\$\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
+	"system-tf": {
+		match: "\\$[a-zA-Z0-9_$][a-zA-Z0-9_$]*\\b",
 		name: "support.function.systemverilog"
 	},
-	{
-		match: "\\b([a-zA-Z_][a-zA-Z0-9_]*)(')(?=\\()",
-		name: "meta.cast.systemverilog",
+	"cast-operator": {
+		match: "[ \\t\\n]*([a-zA-Z_][a-zA-Z0-9_$]*)(')(?=\\()",
 		captures: {
 			"1": {
-				name: "storage.type.systemverilog"
+				name: "storage.type.interface.systemverilog"
 			},
 			"2": {
 				name: "keyword.operator.cast.systemverilog"
 			}
-		}
-	},
-	{
-		match: "^\\s*(localparam|parameter)\\s+([A-Z_][A-Z0-9_]*)\\b\\s*(?=(=))",
-		name: "meta.param.systemverilog",
-		captures: {
-			"1": {
-				name: "keyword.other.systemverilog"
-			},
-			"2": {
-				name: "constant.other.systemverilog"
-			}
-		}
+		},
+		name: "meta.cast.systemverilog"
 	},
-	{
-		match: "^\\s*(localparam|parameter)\\s+([a-zA-Z_][a-zA-Z0-9_]*)\\b\\s*(?=(=))",
-		name: "meta.param.systemverilog",
-		captures: {
-			"1": {
-				name: "keyword.other.systemverilog"
-			}
-		}
-	},
-	{
-		match: "^\\s*(local\\s+|protected\\s+|localparam\\s+|parameter\\s+)?(const\\s+|virtual\\s+)?(rand\\s+|randc\\s+)?(([a-zA-Z_][a-zA-Z0-9_]*)(::))?([a-zA-Z_][a-zA-Z0-9_]*)\\b\\s*(?=(#\\s*\\([\\w,]+\\)\\s*)?([a-zA-Z][a-zA-Z0-9_\\s\\[\\]']*)(;|,|=|'\\{))",
-		name: "meta.userdefined.systemverilog",
+	parameter: {
+		match: "[ \\t\\n]*(localparam|parameter)[ \\t\\n]+([a-zA-Z_][a-zA-Z0-9_$:]*[ \\t\\n]+)?(?:((?:un)?signed)[ \\t\\n]+)?(?:(\\[[a-zA-Z0-9_:$\\-\\+` \\t\\n\\[\\]]*\\])[ \\t\\n]*)?([a-zA-Z_][a-zA-Z0-9_$]*)(?:[ \\t\\n]*(\\[[a-zA-Z0-9_:$\\-\\+` \\t\\n\\[\\]]*\\]))?[ \\t\\n]*(?==)",
 		captures: {
 			"1": {
 				name: "keyword.other.systemverilog"
 			},
 			"2": {
-				name: "keyword.other.systemverilog"
+				patterns: [
+					{
+						include: "#storage-scope"
+					}
+				],
+				name: "storage.type.built-in.systemverilog"
 			},
 			"3": {
-				name: "storage.type.rand.systemverilog"
+				name: "storage.modifier.systemverilog"
+			},
+			"4": {
+				patterns: [
+					{
+						include: "#selects"
+					}
+				]
 			},
 			"5": {
-				name: "support.type.scope.systemverilog"
+				name: "constant.other.systemverilog"
 			},
 			"6": {
-				name: "keyword.operator.scope.systemverilog"
-			},
-			"7": {
-				name: "storage.type.userdefined.systemverilog"
+				patterns: [
+					{
+						include: "#selects"
+					}
+				]
 			}
-		}
+		},
+		name: "meta.param.systemverilog"
 	},
-	{
-		match: "\\s*\\b(option)\\.",
+	"sv-option": {
+		match: "[ \\t\\n]*\\b(option)\\.",
 		captures: {
 			"1": {
 				name: "keyword.cover.systemverilog"
 			}
 		}
 	},
-	{
-		match: "\\s*\\b(local|const|protected|virtual|localparam|parameter)\\b",
+	"sv-local": {
+		match: "[ \\t\\n]*\\b(const|static|protected|virtual|localparam|parameter|local)\\b",
 		captures: {
 			"1": {
 				name: "keyword.other.systemverilog"
 			}
 		}
 	},
-	{
-		match: "\\s*\\b(rand|randc)\\b",
+	"sv-rand": {
+		match: "[ \\t\\n]*\\b(?:rand|randc)\\b",
 		name: "storage.type.rand.systemverilog"
 	},
-	{
-		begin: "^(\\s*(bind)\\s+([a-zA-Z_][\\w\\.]*))?\\s*([a-zA-Z_][a-zA-Z0-9_]*)\\s*(?=#[^#])",
+	"module-parameters": {
+		begin: "[ \\t\\n]*\\b(?:(bind)[ \\t\\n]+([a-zA-Z_][a-zA-Z0-9_$\\.]*)[ \\t\\n]+)?([a-zA-Z_][a-zA-Z0-9_$]*)[ \\t\\n]+(?!intersect|and|or|throughout|within)(?=#[^#])",
 		beginCaptures: {
-			"2": {
+			"1": {
 				name: "keyword.control.systemverilog"
 			},
-			"4": {
-				name: "storage.module.systemverilog"
+			"2": {
+				name: "entity.name.type.module.systemverilog"
+			},
+			"3": {
+				name: "entity.name.type.module.systemverilog"
+			}
+		},
+		end: ";",
+		endCaptures: {
+			"0": {
+				name: "punctuation.module.instantiation.end.systemverilog"
 			}
 		},
-		end: "(?=;|=|:)",
 		patterns: [
 			{
 				include: "#module-binding"
 			},
 			{
-				include: "#module-param"
+				include: "#parameters"
 			},
 			{
 				include: "#comments"
-			},
-			{
-				include: "#operators"
-			},
-			{
-				include: "#constants"
-			},
-			{
-				include: "#strings"
-			},
-			{
-				match: "\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b(?=\\s*(\\(|$))",
-				name: "entity.name.type.module.systemverilog"
-			}
-		],
-		name: "meta.module.inst.param.systemverilog"
-	},
-	{
-		begin: "\\b([a-zA-Z_][a-zA-Z0-9_]*)\\s+(?!intersect|and|or|throughout|within)([a-zA-Z_][a-zA-Z0-9_]*)\\s*(\\[(\\d+)(\\:(\\d+))?\\])?\\s*(\\(|$)",
-		beginCaptures: {
-			"1": {
-				name: "storage.module.systemverilog"
-			},
-			"2": {
-				name: "entity.name.type.module.systemverilog"
-			},
-			"4": {
-				name: "constant.numeric.systemverilog"
-			},
-			"6": {
-				name: "constant.numeric.systemverilog"
-			}
-		},
-		end: ";",
-		patterns: [
+			},
 			{
-				include: "#module-binding"
+				include: "#operators"
 			},
 			{
-				include: "#comments"
+				include: "#constants"
 			},
 			{
 				include: "#strings"
 			},
 			{
-				include: "#operators"
+				include: "#port-declaration"
 			},
 			{
-				include: "#constants"
+				match: "\\b([a-zA-Z_][a-zA-Z0-9_$]*)\\b(?=[ \\t\\n]*(\\(|$))",
+				name: "variable.other.module.systemverilog"
+			},
+			{
+				include: "#identifiers"
 			}
 		],
-		name: "meta.module.inst.systemverilog"
+		name: "meta.module.parameters.systemverilog"
 	},
-	{
-		name: "meta.struct.assign.systemverilog",
-		begin: "\\b\\s+(<?=)\\s*(\\'{)",
+	"module-no-parameters": {
+		begin: "[ \\t\\n]*\\b(?:(bind)[ \\t\\n]+([a-zA-Z_][a-zA-Z0-9_$\\.]*)[ \\t\\n]+)?([a-zA-Z_][a-zA-Z0-9_$]*)[ \\t\\n]+(?!intersect|and|or|throughout|within)([a-zA-Z_][a-zA-Z0-9_$]*)(?:[ \\t\\n]*(\\[[a-zA-Z0-9_:$\\-\\+` \\t\\n\\[\\]]*\\])?)[ \\t\\n]*(?=\\(|;)",
 		beginCaptures: {
 			"1": {
-				name: "keyword.operator.other.systemverilog"
+				name: "keyword.control.systemverilog"
 			},
 			"2": {
-				name: "keyword.operator.other.systemverilog"
+				name: "entity.name.type.module.systemverilog"
 			},
 			"3": {
-				name: "keyword.operator.other.systemverilog"
+				name: "entity.name.type.module.systemverilog"
+			},
+			"4": {
+				name: "variable.other.module.systemverilog"
+			},
+			"5": {
+				patterns: [
+					{
+						include: "#selects"
+					}
+				]
 			}
 		},
 		end: ";",
+		endCaptures: {
+			"0": {
+				name: "punctuation.module.instantiation.end.systemverilog"
+			}
+		},
 		patterns: [
 			{
-				match: "\\b(\\w+)\\s*(:)(?!:)",
-				captures: {
-					"1": {
-						name: "support.function.field.systemverilog"
-					},
-					"2": {
-						name: "keyword.operator.other.systemverilog"
-					}
-				}
+				include: "#module-binding"
 			},
 			{
 				include: "#comments"
 			},
+			{
+				include: "#operators"
+			},
+			{
+				include: "#constants"
+			},
 			{
 				include: "#strings"
 			},
 			{
-				include: "#operators"
+				include: "#port-declaration"
 			},
 			{
-				include: "#constants"
+				match: "\\b([a-zA-Z_][a-zA-Z0-9_$]*)\\b(?=[ \\t\\n]*(\\(|$))",
+				name: "variable.other.module.systemverilog"
 			},
 			{
-				include: "#storage-scope-systemverilog"
+				include: "#identifiers"
 			}
-		]
-	},
-	{
-		include: "#storage-scope-systemverilog"
-	},
-	{
-		include: "#functions"
+		],
+		name: "meta.module.no_parameters.systemverilog"
 	},
-	{
-		include: "#constants"
-	}
-];
-var repository = {
 	functions: {
-		match: "\\b(\\w+)(?=\\s*\\()",
-		name: "support.function.generic.systemverilog"
+		match: "[ \\t\\n]*\\b([a-zA-Z_][a-zA-Z0-9_$]*)(?=[ \\t\\n]*\\()",
+		name: "entity.name.function.systemverilog"
 	},
 	"all-types": {
 		patterns: [
 			{
-				include: "#storage-type-systemverilog"
+				include: "#built-ins"
 			},
 			{
-				include: "#storage-modifier-systemverilog"
+				include: "#modifiers"
 			}
 		]
 	},
 	constants: {
 		patterns: [
 			{
-				match: "(\\b\\d+)?'(s?[bB]\\s*[0-1xXzZ?][0-1_xXzZ?]*|s?[oO]\\s*[0-7xXzZ?][0-7_xXzZ?]*|s?[dD]\\s*[0-9xXzZ?][0-9_xXzZ?]*|s?[hH]\\s*[0-9a-fA-FxXzZ?][0-9a-fA-F_xXzZ?]*)((e|E)(\\+|-)?[0-9]+)?(?!'|\\w)",
+				match: "(\\b[1-9][0-9_]*)?'([sS]?[bB][ \\t\\n]*[0-1xXzZ?][0-1_xXzZ?]*|[sS]?[oO][ \\t\\n]*[0-7xXzZ?][0-7_xXzZ?]*|[sS]?[dD][ \\t\\n]*[0-9xXzZ?][0-9_xXzZ?]*|[sS]?[hH][ \\t\\n]*[0-9a-fA-FxXzZ?][0-9a-fA-F_xXzZ?]*)((e|E)(\\+|-)?[0-9]+)?(?!'|\\w)",
 				name: "constant.numeric.systemverilog"
 			},
 			{
@@ -710,67 +752,79 @@ var repository = {
 				name: "constant.numeric.bit.systemverilog"
 			},
 			{
-				match: "\\b((\\d[\\d_]*)(e|E)(\\+|-)?[0-9]+)\\b",
+				match: "\\b(?:\\d[\\d_\\.]*(?<!\\.)(?:e|E)(?:\\+|-)?[0-9]+)\\b",
 				name: "constant.numeric.exp.systemverilog"
 			},
 			{
-				match: "\\b(\\d[\\d_]*)\\b",
+				match: "\\b(?:\\d[\\d_\\.]*(?!(?:[\\d\\.]|[ \\t\\n]*(?:e|E|fs|ps|ns|us|ms|s))))\\b",
 				name: "constant.numeric.decimal.systemverilog"
 			},
 			{
-				match: "\\b(\\d+(fs|ps|ns|us|ms|s)?)\\b",
+				match: "\\b(?:\\d[\\d\\.]*[ \\t\\n]*(?:fs|ps|ns|us|ms|s))\\b",
 				name: "constant.numeric.time.systemverilog"
 			},
 			{
-				match: "\\b([A-Z][A-Z0-9_]*)\\b",
-				name: "constant.other.net.systemverilog"
+				include: "#compiler-directives"
 			},
 			{
-				match: "(`ifdef|`ifndef|`default_nettype)\\s+(\\w+)",
-				captures: {
-					"1": {
-						name: "constant.other.preprocessor.systemverilog"
-					},
-					"2": {
-						name: "support.variable.systemverilog"
-					}
-				}
+				match: "\\b(?:this|super|null)\\b",
+				name: "constant.language.systemverilog"
 			},
 			{
-				match: "`(celldefine|else|elsif|endcelldefine|endif|include|line|nounconnected_drive|resetall|timescale|unconnected_drive|undef|begin_\\w+|end_\\w+|remove_\\w+|restore_\\w+)\\b",
-				name: "constant.other.preprocessor.systemverilog"
+				match: "\\b([A-Z][A-Z0-9_]*)\\b",
+				name: "constant.other.net.systemverilog"
 			},
 			{
-				match: "`\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
-				name: "constant.other.define.systemverilog"
+				match: "\\b(?<!\\.)([A-Z_0-9]+)(?!\\.)\\b",
+				name: "constant.numeric.parameter.uppercase.systemverilog"
 			},
 			{
-				match: "\\b(null)\\b",
-				name: "support.constant.systemverilog"
+				match: "\\.\\*",
+				name: "keyword.operator.quantifier.regexp"
 			}
 		]
 	},
 	operators: {
 		patterns: [
 			{
-				match: "(=|==|===|!=|!==|<=|>=|<|>)",
-				name: "keyword.operator.comparison.systemverilog"
+				match: "\\+=|-=|/=|\\*=|%=|&=|\\|=|\\^=|>>>=|>>=|<<<=|<<=|<=|=",
+				name: "keyword.operator.assignment.systemverilog"
+			},
+			{
+				match: "\\+\\+",
+				name: "keyword.operator.increment.systemverilog"
 			},
 			{
-				match: "(\\-|\\+|\\*|\\/|%)",
+				match: "--",
+				name: "keyword.operator.decrement.systemverilog"
+			},
+			{
+				match: "\\+|-|\\*\\*|\\*|/|%",
 				name: "keyword.operator.arithmetic.systemverilog"
 			},
 			{
-				match: "(!|&&|\\|\\||\\bor\\b)",
+				match: "!|&&|\\|\\|",
 				name: "keyword.operator.logical.systemverilog"
 			},
 			{
-				match: "(&|\\||\\^|~|{|'{|}|<<|>>|\\?|:)",
+				match: "<<<|<<|>>>|>>",
+				name: "keyword.operator.bitwise.shift.systemverilog"
+			},
+			{
+				match: "~&|~\\||~|\\^~|~\\^|&|\\||\\^|{|''{|}|:|\\?",
 				name: "keyword.operator.bitwise.systemverilog"
 			},
 			{
-				match: "(#|@)",
-				name: "keyword.operator.other.systemverilog"
+				match: "<=|<|>=|>|==\\?|!=\\?|===|!==|==|!=",
+				name: "keyword.operator.comparison.systemverilog"
+			},
+			{
+				match: "@|#|->|<->",
+				name: "keyword.operator.channel.systemverilog"
+			},
+			{
+				match: "\\b(?:dist|inside|or|and)\\b|:=|:/|\\|->|\\|=>|#-#|#=#",
+				name: "keyword.operator.logical.systemverilog"
 			}
 		]
 	},
@@ -778,64 +832,100 @@ var repository = {
 		patterns: [
 			{
 				begin: "/\\*",
-				captures: {
+				beginCaptures: {
 					"0": {
 						name: "punctuation.definition.comment.systemverilog"
 					}
 				},
 				end: "\\*/",
+				endCaptures: {
+					"0": {
+						name: "punctuation.definition.comment.systemverilog"
+					}
+				},
+				patterns: [
+					{
+						include: "#fixme-todo"
+					}
+				],
 				name: "comment.block.systemverilog"
 			},
 			{
-				captures: {
-					"1": {
+				begin: "//",
+				beginCaptures: {
+					"0": {
 						name: "punctuation.definition.comment.systemverilog"
 					}
 				},
-				match: "(//).*$\\n?",
+				end: "$\\n?",
+				patterns: [
+					{
+						include: "#fixme-todo"
+					}
+				],
 				name: "comment.line.double-slash.systemverilog"
 			}
 		]
 	},
-	"port-dir": {
+	"fixme-todo": {
 		patterns: [
 			{
-				match: "\\s*\\b(output|input|inout|ref)\\s+(([a-zA-Z_][a-zA-Z0-9_]*)(::))?([a-zA-Z_][a-zA-Z0-9_]*)?\\s+(?=\\[[a-zA-Z0-9_\\-\\+]*:[a-zA-Z0-9_\\-\\+]*\\]\\s+[a-zA-Z_][a-zA-Z0-9_\\s]*)",
+				match: "(?i:fixme)",
+				name: "invalid.broken.fixme.systemverilog"
+			},
+			{
+				match: "(?i:todo)",
+				name: "invalid.unimplemented.todo.systemverilog"
+			}
+		]
+	},
+	"port-declaration": {
+		patterns: [
+			{
+				match: ",?[ \\t\\n]*\\b(output|input|inout|ref)\\b[ \\t\\n]+(?:\\b([a-zA-Z_][a-zA-Z0-9_$]*)(::))?([a-zA-Z_][a-zA-Z0-9_$]*\\b)?(?:[ \\t\\n]*(\\[[a-zA-Z0-9_:$\\-\\+` \\t\\n\\[\\]]*\\])?)(?:[ \\t\\n]*\\b([a-zA-Z_][a-zA-Z0-9_$]*)\\b)(?:[ \\t\\n]*(\\[[a-zA-Z0-9_:$\\-\\+` \\t\\n\\[\\]]*\\])?)(?:[ \\t\\n]*(,|;))?",
 				captures: {
 					"1": {
 						name: "support.type.systemverilog"
 					},
-					"3": {
+					"2": {
 						name: "support.type.scope.systemverilog"
 					},
-					"4": {
+					"3": {
 						name: "keyword.operator.scope.systemverilog"
 					},
+					"4": {
+						patterns: [
+							{
+								include: "#built-ins"
+							}
+						]
+					},
 					"5": {
-						name: "storage.type.interface.systemverilog"
-					}
-				}
-			},
-			{
-				match: "\\s*\\b(output|input|inout|ref)\\s+(([a-zA-Z_][a-zA-Z0-9_]*)(::))?([a-zA-Z_][a-zA-Z0-9_]*)?\\s+(?=[a-zA-Z_][a-zA-Z0-9_\\s]*)",
-				captures: {
-					"1": {
-						name: "support.type.systemverilog"
+						patterns: [
+							{
+								include: "#selects"
+							}
+						]
 					},
-					"3": {
-						name: "support.type.scope.systemverilog"
+					"6": {
+						patterns: [
+							{
+								include: "#identifiers"
+							}
+						]
 					},
-					"4": {
-						name: "keyword.operator.scope.systemverilog"
+					"7": {
+						patterns: [
+							{
+								include: "#selects"
+							}
+						]
 					},
-					"5": {
-						name: "storage.type.interface.systemverilog"
+					"8": {
+						name: "punctuation.terminator.port.systemverilog"
 					}
-				}
-			},
-			{
-				match: "\\s*\\b(output|input|inout|ref)\\b",
-				name: "support.type.systemverilog"
+				},
+				name: "meta.port.declaration.systemverilog"
 			}
 		]
 	},
@@ -857,7 +947,7 @@ var repository = {
 				include: "#strings"
 			},
 			{
-				match: "^\\s*([a-zA-Z_][a-zA-Z0-9_]*)\\s+[a-zA-Z_][a-zA-Z0-9_,=\\s]*",
+				match: "[ \\t\\n]*\\b([a-zA-Z_][a-zA-Z0-9_$]*)[ \\t\\n]+[a-zA-Z_][a-zA-Z0-9_,= \\t\\n]*",
 				captures: {
 					"1": {
 						name: "storage.type.interface.systemverilog"
@@ -865,24 +955,28 @@ var repository = {
 				}
 			},
 			{
-				include: "#storage-scope-systemverilog"
+				include: "#storage-scope"
 			}
 		]
 	},
-	"storage-type-systemverilog": {
+	"built-ins": {
 		patterns: [
 			{
-				match: "\\s*\\b(var|wire|tri|tri[01]|supply[01]|wand|triand|wor|trior|trireg|reg|integer|int|longint|shortint|logic|bit|byte|shortreal|string|time|realtime|real|process|void)\\b",
-				name: "storage.type.systemverilog"
+				match: "[ \\t\\n]*\\b(var|wire|tri|tri[01]|supply[01]|wand|triand|wor|trior|trireg|reg|integer|int|longint|shortint|logic|bit|byte|shortreal|string|time|realtime|real|process|void)\\b",
+				name: "storage.type.built-in.systemverilog"
 			},
 			{
-				match: "\\s*\\b(uvm_transaction|uvm_component|uvm_monitor|uvm_driver|uvm_test|uvm_env|uvm_object|uvm_agent|uvm_sequence_base|uvm_sequence|uvm_sequence_item|uvm_sequence_state|uvm_sequencer|uvm_sequencer_base|uvm_component_registry|uvm_analysis_imp|uvm_analysis_port|uvm_analysis_export|uvm_config_db|uvm_active_passive_enum|uvm_phase|uvm_verbosity|uvm_tlm_analysis_fifo|uvm_tlm_fifo|uvm_report_server|uvm_objection|uvm_recorder|uvm_domain|uvm_reg_field|uvm_reg|uvm_reg_block|uvm_bitstream_t|uvm_radix_enum|uvm_printer|uvm_packer|uvm_comparer|uvm_scope_stack)\\b",
+				match: "[ \\t\\n]*\\b(uvm_transaction|uvm_component|uvm_monitor|uvm_driver|uvm_test|uvm_env|uvm_object|uvm_agent|uvm_sequence_base|uvm_sequence|uvm_sequence_item|uvm_sequence_state|uvm_sequencer|uvm_sequencer_base|uvm_component_registry|uvm_analysis_imp|uvm_analysis_port|uvm_analysis_export|uvm_config_db|uvm_active_passive_enum|uvm_phase|uvm_verbosity|uvm_tlm_analysis_fifo|uvm_tlm_fifo|uvm_report_server|uvm_objection|uvm_recorder|uvm_domain|uvm_reg_field|uvm_reg|uvm_reg_block|uvm_bitstream_t|uvm_radix_enum|uvm_printer|uvm_packer|uvm_comparer|uvm_scope_stack)\\b",
 				name: "storage.type.uvm.systemverilog"
 			}
 		]
 	},
-	"storage-scope-systemverilog": {
-		match: "\\b([a-zA-Z_][a-zA-Z0-9_]*)(::)",
+	modifiers: {
+		match: "[ \\t\\n]*\\b(?:(?:un)?signed|small|medium|large|supply[01]|strong[01]|pull[01]|weak[01]|highz[01])\\b",
+		name: "storage.modifier.systemverilog"
+	},
+	"storage-scope": {
+		match: "\\b([a-zA-Z_][a-zA-Z0-9_$]*)(::)",
 		captures: {
 			"1": {
 				name: "support.type.systemverilog"
@@ -893,31 +987,35 @@ var repository = {
 		},
 		name: "meta.scope.systemverilog"
 	},
-	"storage-modifier-systemverilog": {
-		match: "\\b(signed|unsigned|small|medium|large|supply[01]|strong[01]|pull[01]|weak[01]|highz[01])\\b",
-		name: "storage.modifier.systemverilog"
-	},
-	ifmodport: {
-		match: "\\b([a-zA-Z_][a-zA-Z0-9_]*)\\.([a-zA-Z_][a-zA-Z0-9_]*)\\s+([a-zA-Z_][a-zA-Z0-9_]*)\\b",
+	"interface-port": {
+		match: "[ \\t\\n]*\\b([a-zA-Z_][a-zA-Z0-9_$]*)(?:\\.([a-zA-Z_][a-zA-Z0-9_$]*))?[ \\t\\n]+([a-zA-Z_][a-zA-Z0-9_$]*)\\b",
 		captures: {
 			"1": {
 				name: "storage.type.interface.systemverilog"
 			},
 			"2": {
 				name: "support.modport.systemverilog"
+			},
+			"3": {
+				patterns: [
+					{
+						include: "#identifiers"
+					}
+				]
 			}
-		}
+		},
+		name: "meta.interface-port.declaration.systemverilog"
 	},
 	strings: {
 		patterns: [
 			{
-				begin: "\"",
+				begin: "`?\"",
 				beginCaptures: {
 					"0": {
 						name: "punctuation.definition.string.begin.systemverilog"
 					}
 				},
-				end: "\"",
+				end: "\"`?",
 				endCaptures: {
 					"0": {
 						name: "punctuation.definition.string.end.systemverilog"
@@ -926,29 +1024,47 @@ var repository = {
 				name: "string.quoted.double.systemverilog",
 				patterns: [
 					{
-						match: "\\\\.",
+						match: "\\\\(?:[nt\\\\\"vfa]|[0-7]{3}|x[0-9a-fA-F]{2})",
 						name: "constant.character.escape.systemverilog"
 					},
 					{
-						match: "(?x)%\n                                        (\\d+\\$)?                             # field (argument #)\n                                        [#0\\- +']*                           # flags\n                                        [,;:_]?                              # separator character (AltiVec)\n                                        ((-?\\d+)|\\*(-?\\d+\\$)?)?              # minimum field width\n                                        (\\.((-?\\d+)|\\*(-?\\d+\\$)?)?)?         # precision\n                                        (hh|h|ll|l|j|t|z|q|L|vh|vl|v|hv|hl)? # length modifier\n                                        [bdiouxXhHDOUeEfFgGaACcSspnmt%]      # conversion type\n                                    ",
-						name: "constant.other.placeholder.systemverilog"
+						match: "(?x)%\n(\\d+\\$)?                              # field (argument #)\n['\\-+0 #]*                            # flags\n[,;:_]?                               # separator character\n((-?\\d+)|\\*(-?\\d+\\$)?)?               # minimum field width\n(\\.((-?\\d+)|\\*(-?\\d+\\$)?)?)?          # precision\n(hh|h|ll|l|j|z|t|L)?                  # length modifier\n[xXhHdDoObBcClLvVmMpPsStTuUzZeEfFgG%] # conversion type",
+						name: "constant.character.format.placeholder.systemverilog"
 					},
 					{
 						match: "%",
 						name: "invalid.illegal.placeholder.systemverilog"
+					},
+					{
+						include: "#fixme-todo"
 					}
 				]
+			},
+			{
+				begin: "(?<=include)[ \\t\\n]*(<)",
+				beginCaptures: {
+					"1": {
+						name: "punctuation.definition.string.begin.systemverilog"
+					}
+				},
+				end: ">",
+				endCaptures: {
+					"0": {
+						name: "punctuation.definition.string.end.systemverilog"
+					}
+				},
+				name: "string.quoted.other.lt-gt.include.systemverilog"
 			}
 		]
 	},
 	"module-binding": {
-		begin: "\\.([a-zA-Z_][a-zA-Z0-9_]*)\\s*\\(",
+		begin: "\\.([a-zA-Z_][a-zA-Z0-9_$]*)[ \\t\\n]*\\(",
 		beginCaptures: {
 			"1": {
 				name: "support.function.port.systemverilog"
 			}
 		},
-		end: "\\)",
+		end: "\\),?",
 		patterns: [
 			{
 				include: "#constants"
@@ -966,52 +1082,40 @@ var repository = {
 				include: "#constants"
 			},
 			{
-				match: "\\b([a-zA-Z_]\\w*)(::)",
-				captures: {
-					"1": {
-						name: "support.type.scope.systemverilog"
-					},
-					"2": {
-						name: "keyword.operator.scope.systemverilog"
-					}
-				}
+				include: "#storage-scope"
 			},
 			{
-				match: "\\b([a-zA-Z_]\\w*)(')",
-				captures: {
-					"1": {
-						name: "storage.type.interface.systemverilog"
-					},
-					"2": {
-						name: "keyword.operator.cast.systemverilog"
-					}
-				}
+				include: "#cast-operator"
 			},
 			{
-				match: "\\$\\b([a-zA-Z_][a-zA-Z0-9_]*)\\b",
-				name: "support.function.systemverilog"
+				include: "#system-tf"
 			},
 			{
-				match: "\\b(virtual)\\b",
+				match: "\\bvirtual\\b",
 				name: "keyword.control.systemverilog"
+			},
+			{
+				include: "#identifiers"
 			}
 		],
-		match: "\\.([a-zA-Z_][a-zA-Z0-9_]*)\\s*",
-		captures: {
-			"1": {
-				name: "support.function.port.implicit.systemverilog"
-			}
-		}
+		name: "meta.port.binding.systemverilog"
 	},
-	"module-param": {
-		name: "meta.module-param.systemverilog",
-		begin: "(#)\\s*\\(",
+	parameters: {
+		begin: "(#)[ \\t\\n]*(\\()",
 		beginCaptures: {
 			"1": {
-				name: "keyword.operator.param.systemverilog"
+				name: "keyword.operator.channel.systemverilog"
+			},
+			"2": {
+				name: "punctuation.section.parameters.begin"
 			}
 		},
 		end: "\\)",
+		endCaptures: {
+			"0": {
+				name: "punctuation.section.parameters.end"
+			}
+		},
 		patterns: [
 			{
 				include: "#comments"
@@ -1029,51 +1133,127 @@ var repository = {
 				include: "#module-binding"
 			},
 			{
-				match: "\\b(virtual)\\b",
+				match: "\\bvirtual\\b",
 				name: "keyword.control.systemverilog"
 			}
+		],
+		name: "meta.parameters.systemverilog"
+	},
+	identifiers: {
+		patterns: [
+			{
+				match: "\\b[a-zA-Z_][a-zA-Z0-9_$]*\\b",
+				name: "variable.other.identifier.systemverilog"
+			},
+			{
+				match: "(?<=^|[ \\t\\n])\\\\[!-~]+",
+				name: "variable.other.identifier.systemverilog"
+			}
 		]
 	},
-	"struct-anonymous": {
-		begin: "\\s*\\b(struct|union)\\s*(packed)?\\s*",
+	selects: {
+		begin: "\\[",
 		beginCaptures: {
-			"1": {
-				name: "keyword.control.systemverilog"
+			"0": {
+				name: "punctuation.slice.brackets.begin"
+			}
+		},
+		end: "\\]",
+		endCaptures: {
+			"0": {
+				name: "punctuation.slice.brackets.end"
+			}
+		},
+		patterns: [
+			{
+				match: "\\$",
+				name: "constant.language.systemverilog"
 			},
-			"2": {
-				name: "keyword.control.systemverilog"
+			{
+				include: "#constants"
+			},
+			{
+				include: "#operators"
+			},
+			{
+				match: "[a-zA-Z0-9_$]+",
+				name: "meta.index.systemverilog"
+			}
+		],
+		name: "meta.brackets.select.systemverilog"
+	},
+	attributes: {
+		begin: "(?<!@[ \\t\\n]?)\\(\\*",
+		beginCaptures: {
+			"0": {
+				name: "punctuation.attribute.rounds.begin"
 			}
 		},
-		end: "(})\\s*([a-zA-Z_]\\w*)\\s*;",
+		end: "\\*\\)",
 		endCaptures: {
-			"1": {
-				name: "keyword.operator.other.systemverilog"
+			"0": {
+				name: "punctuation.attribute.rounds.end"
 			}
 		},
 		patterns: [
 			{
-				include: "#base-grammar"
+				match: "([a-zA-Z_][a-zA-Z0-9_$]*)(?:[ \\t\\n]*(=)[ \\t\\n]*)?",
+				captures: {
+					"1": {
+						name: "keyword.control.systemverilog"
+					},
+					"2": {
+						name: "keyword.operator.assignment.systemverilog"
+					}
+				}
+			},
+			{
+				include: "#constants"
+			},
+			{
+				include: "#strings"
 			}
 		],
-		name: "meta.struct.anonymous.systemverilog"
+		name: "meta.attribute.systemverilog"
+	},
+	imports: {
+		match: "[ \\t\\n]*\\b(import|export)[ \\t\\n]+([a-zA-Z_][a-zA-Z0-9_$]*|\\*)[ \\t\\n]*(::)[ \\t\\n]*([a-zA-Z_][a-zA-Z0-9_$]*|\\*)[ \\t\\n]*(,|;)",
+		captures: {
+			"1": {
+				name: "keyword.control.systemverilog"
+			},
+			"2": {
+				name: "support.type.systemverilog"
+			},
+			"3": {
+				name: "keyword.operator.scope.systemverilog"
+			},
+			"4": {
+				patterns: [
+					{
+						include: "#operators"
+					},
+					{
+						include: "#identifiers"
+					}
+				]
+			}
+		},
+		name: "meta.import.systemverilog"
 	}
 };
-var scopeName = "source.systemverilog";
-var uuid = "789be04c-8b74-352e-8f37-63d336001277";
 var information_for_contributors = [
-	"This file has been converted from https://github.com/mshr-h/vscode-verilog-hdl-support/blob/master/",
+	"This file has been converted from https://github.com/codingame/svlangserver/blob/master/",
 	"If you want to provide a fix or improvement, please create a pull request against the original repository.",
 	"Once accepted there, we are happy to receive an update request."
 ];
 var systemverilog_tmLanguage = {
-	fileTypes: fileTypes,
-	hidden: hidden,
 	name: name,
+	scopeName: scopeName,
+	fileTypes: fileTypes,
 	patterns: patterns,
 	repository: repository,
-	scopeName: scopeName,
-	uuid: uuid,
 	information_for_contributors: information_for_contributors
 };
 
-export { systemverilog_tmLanguage as default, fileTypes, hidden, information_for_contributors, name, patterns, repository, scopeName, uuid };
+export { systemverilog_tmLanguage as default, fileTypes, information_for_contributors, name, patterns, repository, scopeName };