@codingame/monaco-editor-wrapper 1.10.0 → 1.10.3

package/dist/verilog-systemverilog.js

@@ -1,208 +0,0 @@
-var bit = {
-	prefix: "bit",
-	body: "bit ${1:bit_name} = ${2:value};"
-};
-var int = {
-	prefix: "int",
-	body: "int ${1:int_name} = ${2:value};"
-};
-var shortint = {
-	prefix: "shortint",
-	body: "shortint ${1:name} = ${2:value};"
-};
-var longint = {
-	prefix: "longint",
-	body: "longint ${1:name} = ${2:value};"
-};
-var byte = {
-	prefix: "byte",
-	body: "byte ${1:byte:_name} = ${2:value};"
-};
-var logic = {
-	prefix: "logic",
-	body: "logic ${1:logic_name} = ${2:value};"
-};
-var packed = {
-	prefix: "packed",
-	body: "packed"
-};
-var task = {
-	prefix: "task",
-	body: [
-		"task ${1:automatic} ${2:taskName}(${3:arguments});",
-		"\t$0",
-		"endtask //$1"
-	],
-	description: "task name; ... endtask"
-};
-var modport = {
-	prefix: "modport",
-	body: [
-		"modport ${1:identifier} (",
-		"input ${2:input_ports},",
-		"output ${3:output_ports}",
-		");"
-	],
-	description: "modport name (input ports_in, output ports_out); "
-};
-var display = {
-	prefix: "display",
-	body: [
-		"\\$display(\"$1\"$2);$0"
-	],
-	description: "$display(\"...\", params...)"
-};
-var queue = {
-	prefix: "queue",
-	body: "${1:data_type} ${2:queue_name}[\\$];",
-	description: "insert queue."
-};
-var mailbox = {
-	prefix: "mailbox",
-	body: [
-		"mailbox mbx",
-		"${1:mbx = new();}"
-	],
-	description: "insert mailbox instance"
-};
-var assert = {
-	prefix: "assert",
-	body: [
-		"assert (${1:condition}) $2",
-		"else   ${3:error_process}"
-	],
-	description: "insert assert() ... else ..."
-};
-var verilogSystemverilog = {
-	"always_ff block": {
-	prefix: "always_ff",
-	body: [
-		"always_ff @( ${1:clock} ) begin : ${2:blockName}",
-		"\t$0",
-		"end"
-	],
-	description: "Insert an always_ff block"
-},
-	"always_comb block": {
-	prefix: "always_comb",
-	body: [
-		"always_comb begin : ${1:blockName}",
-		"\t$0",
-		"end"
-	],
-	description: "Insert an always_comb block"
-},
-	"always_latch block": {
-	prefix: "always_latch",
-	body: [
-		"always_latch begin : ${1:blockName}",
-		"\t$0",
-		"end"
-	],
-	description: "Insert an always_latch block"
-},
-	bit: bit,
-	int: int,
-	shortint: shortint,
-	longint: longint,
-	byte: byte,
-	logic: logic,
-	packed: packed,
-	"this": {
-	prefix: "this",
-	body: "this"
-},
-	"typedef struct packed": {
-	prefix: "typedef struct packed",
-	body: [
-		"typedef struct packed {",
-		"\t$0",
-		"} ${1:struct_name};"
-	],
-	description: "typedef struct packed { ... } name"
-},
-	"class": {
-	prefix: "class",
-	body: [
-		"class ${1:className};",
-		"\tfunction new();",
-		"\t\t$0",
-		"\tendfunction //new()",
-		"endclass //$1"
-	],
-	description: "class name; ... endclass"
-},
-	"class extends": {
-	prefix: "class extends",
-	body: [
-		"class ${1:className} extends ${2:superClass};",
-		"\tfunction new();",
-		"\t\t$0",
-		"\tendfunction //new()",
-		"endclass //$1 extends $2"
-	],
-	description: "class name extends super; ... endclass"
-},
-	task: task,
-	"package": {
-	prefix: "package",
-	body: [
-		"package ${1:package_name}",
-		"\t$2",
-		"endpackage"
-	],
-	description: "package name; ... endpackage"
-},
-	"import": {
-	prefix: "import",
-	body: "import ${1:name}::${2:scope};",
-	description: "import name::scope"
-},
-	"interface": {
-	prefix: "interface",
-	body: [
-		"interface ${1:interfacename};",
-		"\t$0",
-		"endinterface //$1"
-	],
-	description: "interface name; ... endinterface"
-},
-	modport: modport,
-	display: display,
-	"typedef enum": {
-	prefix: "typedef enum",
-	body: [
-		"typedef enum ${1:data_type} { $0 } ${2:name};"
-	],
-	description: "typedef enum (data_type) { ... } name"
-},
-	"enum": {
-	prefix: [
-		"en",
-		"enum"
-	],
-	body: [
-		"enum ${1:data_type} { $0 } ${2:name}"
-	],
-	description: "enum (data_type) { ... } name"
-},
-	queue: queue,
-	mailbox: mailbox,
-	"associative array": {
-	prefix: "AA",
-	body: "${1:data_type} ${2:name}[${3:index_type}];$0",
-	description: "insert Associative array(AA)."
-},
-	assert: assert,
-	"fork-join": {
-	prefix: "fork join",
-	body: [
-		"fork",
-		"\t$0",
-		"join"
-	],
-	description: "fork ... join"
-}
-};
-
-export { assert, bit, byte, verilogSystemverilog as default, display, int, logic, longint, mailbox, modport, packed, queue, shortint, task };

package/dist/verilog-verilog.js

@@ -1,432 +0,0 @@
-var always = {
-	prefix: [
-		"al",
-		"always"
-	],
-	body: [
-		"always @($1) begin",
-		"\t$2",
-		"end"
-	],
-	description: "Insert an always block"
-};
-var alwaysposclk = {
-	prefix: [
-		"alclk",
-		"alwaysposclk"
-	],
-	body: [
-		"always @(posedge clk $1) begin",
-		"\t$2",
-		"end"
-	],
-	description: "always @(posedge clk)"
-};
-var alwaysnegclk = {
-	prefix: [
-		"alnegclk",
-		"alwaysnegclk"
-	],
-	body: [
-		"always @(negedge clk $1) begin",
-		"\t$2",
-		"end"
-	],
-	description: "always @(negedge clk)"
-};
-var end = {
-	prefix: "end",
-	body: "end",
-	description: "Insert end keyword"
-};
-var initial = {
-	prefix: "initial",
-	body: [
-		"initial begin",
-		"\t$0",
-		"end"
-	],
-	description: "initial begin ... end"
-};
-var casex = {
-	prefix: "casex",
-	body: [
-		"casex (${1:param})",
-		"\t$2: $3",
-		"\tdefault: $4",
-		"endcase"
-	],
-	description: "casex () ... endcase"
-};
-var casez = {
-	prefix: "casez",
-	body: [
-		"casez (${1:param})",
-		"\t$2: $3",
-		"\tdefault: $4",
-		"endcase"
-	],
-	description: "casez () ... endcase"
-};
-var reg = {
-	prefix: "reg",
-	body: [
-		"reg $1;"
-	],
-	description: "reg reg_name;"
-};
-var regarray = {
-	prefix: [
-		"regarray",
-		"reg ["
-	],
-	body: [
-		"reg [$1:$2] $3;"
-	],
-	description: "reg [N:0] reg_name;"
-};
-var regmemory = {
-	prefix: [
-		"regmemory",
-		"memory"
-	],
-	body: [
-		"reg [$1:$2] $3 [$4:$5];"
-	],
-	description: "reg [N:0] reg_name [0:M];"
-};
-var wire = {
-	prefix: "wire",
-	body: [
-		"wire $1;"
-	],
-	description: "wire wire_name;"
-};
-var wirearray = {
-	prefix: [
-		"wirearray",
-		"wire ["
-	],
-	body: [
-		"wire [$1:$2] $3;"
-	],
-	description: "wire [N:0] wire_name;"
-};
-var array = {
-	prefix: "array",
-	body: "[${1:8}:${2:0}]$0",
-	description: "insert [x:y]"
-};
-var parameter = {
-	prefix: "parameter",
-	body: [
-		"parameter $1 = $2;"
-	],
-	description: "paramter var = val;"
-};
-var localparam = {
-	prefix: "localparam",
-	body: "localparam $1 = $2;",
-	description: "localparam var = val"
-};
-var integer = {
-	prefix: "integer",
-	body: "integer $1;",
-	description: "integer int_name"
-};
-var signed = {
-	prefix: "signed",
-	body: "signed $1 $2;",
-	description: "signed datatype name"
-};
-var include = {
-	prefix: [
-		"include",
-		"`include"
-	],
-	body: [
-		"`include \"$1\""
-	],
-	description: "`include \"..\""
-};
-var define = {
-	prefix: [
-		"def",
-		"define",
-		"`define"
-	],
-	body: [
-		"`define ${1:macro}"
-	],
-	description: "`define macro"
-};
-var ifdef = {
-	prefix: [
-		"ifdef",
-		"`ifdef"
-	],
-	body: "`ifdef ${1:macro}",
-	description: "`ifdef macro"
-};
-var ifndef = {
-	prefix: [
-		"ifndef",
-		"`ifndef"
-	],
-	body: "`ifndef ${1:macro}",
-	description: "`ifndef macro"
-};
-var elsif = {
-	prefix: [
-		"elsif",
-		"`elsif"
-	],
-	body: "`elsif ${1:macro}",
-	description: "`elsif macro"
-};
-var endif = {
-	prefix: [
-		"endif",
-		"`endif"
-	],
-	body: "`endif ${1:macro}",
-	description: "`endif macro"
-};
-var undef = {
-	prefix: [
-		"undef",
-		"`undef"
-	],
-	body: "`undef ${1:macro}",
-	description: "`undef macro"
-};
-var timescale = {
-	prefix: [
-		"ts",
-		"timescale",
-		"`timescale"
-	],
-	body: [
-		"`timescale ${1:1ps}/${2:1ps}$0"
-	]
-};
-var default_nettype = {
-	prefix: [
-		"default_nettype",
-		"`default_nettype"
-	],
-	body: "`default_nettype ${1:none}",
-	description: "Set default nettype"
-};
-var ternary = {
-	prefix: "ternary",
-	body: [
-		"$1 ? $2 : $3"
-	],
-	description: "a ? b : c"
-};
-var ifelse = {
-	prefix: "ifelse",
-	body: [
-		"if (${1:conditions}) begin",
-		"\t$2",
-		"end else begin",
-		"\t$3",
-		"end"
-	],
-	description: "if (...) begin ... end else begin ... end"
-};
-var forever = {
-	prefix: "forever",
-	body: [
-		"forever begin",
-		"\t$0",
-		"end"
-	],
-	description: "forever begin ... end"
-};
-var generate = {
-	prefix: "generate",
-	body: [
-		"generate",
-		"\t$1",
-		"endgenerate"
-	],
-	description: "generate (...) ... endgenerate"
-};
-var genvar = {
-	prefix: "genvar",
-	body: "genvar $1",
-	description: "genvar i"
-};
-var verilogVerilog = {
-	"module with parameters": {
-	prefix: [
-		"paramod",
-		"module #"
-	],
-	body: [
-		"module ${1:moduleName} #(",
-		"\t${2:parameters}",
-		") (",
-		"\t${3:ports}",
-		");",
-		"\t$0",
-		"endmodule"
-	],
-	description: "Insert a module with parameter"
-},
-	"module without parameters": {
-	prefix: "module",
-	body: [
-		"module ${1:moduleName} (",
-		"\t${2:ports}",
-		");",
-		"\t$0",
-		"endmodule"
-	],
-	description: "Insert a module without parameter"
-},
-	"instantiate module": {
-	prefix: [
-		"set module",
-		"instantiate module"
-	],
-	body: [
-		"${1:mod_name} ${2:instance_name} (${3:.*}$0);"
-	],
-	description: "set module, mod i0 (.*);"
-},
-	always: always,
-	alwaysposclk: alwaysposclk,
-	alwaysnegclk: alwaysnegclk,
-	"begin/end": {
-	prefix: "begin",
-	body: [
-		"begin",
-		"\t$1",
-		"end"
-	],
-	description: "Insert a begin ... end block"
-},
-	end: end,
-	initial: initial,
-	"case": {
-	prefix: "case",
-	body: [
-		"case (${1:param})",
-		"\t$2: $3",
-		"\tdefault: $4",
-		"endcase"
-	],
-	description: "case () ... endcase"
-},
-	casex: casex,
-	casez: casez,
-	reg: reg,
-	regarray: regarray,
-	regmemory: regmemory,
-	wire: wire,
-	wirearray: wirearray,
-	array: array,
-	parameter: parameter,
-	localparam: localparam,
-	integer: integer,
-	signed: signed,
-	include: include,
-	define: define,
-	ifdef: ifdef,
-	ifndef: ifndef,
-	elsif: elsif,
-	endif: endif,
-	undef: undef,
-	timescale: timescale,
-	default_nettype: default_nettype,
-	ternary: ternary,
-	"if": {
-	prefix: "if",
-	body: [
-		"if (${1:conditions}) begin",
-		"\t$0",
-		"end"
-	],
-	description: "if (...) begin ... end"
-},
-	ifelse: ifelse,
-	"for loop": {
-	prefix: "for",
-	body: [
-		"for ($1 = $2; $3; $4) begin",
-		"\t$0",
-		"end"
-	],
-	description: "for (...) begin ... end"
-},
-	"while loop": {
-	prefix: "while",
-	body: [
-		"while ($1) begin",
-		"\t$2",
-		"end"
-	],
-	description: "while (...) begin ... end"
-},
-	forever: forever,
-	"function": {
-	prefix: "function",
-	body: [
-		"function $1;",
-		"\t$2;",
-		"\t$3",
-		"endfunction"
-	],
-	description: "function (...) ... endfunction"
-},
-	generate: generate,
-	genvar: genvar,
-	"testbench template": {
-	prefix: [
-		"tb",
-		"testbench"
-	],
-	body: [
-		"`include \"$1.v\"",
-		"`default_nettype none",
-		"",
-		"module tb_$1;",
-		"reg clk;",
-		"reg rst_n;",
-		"",
-		"$1 $3",
-		"(",
-		"\t.rst_n (rst_n),",
-		"\t.clk (clk),",
-		");",
-		"",
-		"localparam CLK_PERIOD = 10;",
-		"always #(CLK_PERIOD/2) clk=~clk;",
-		"",
-		"initial begin",
-		"\t\\$dumpfile(\"tb_$1.vcd\");",
-		"\t\\$dumpvars(0, tb_$1);",
-		"end",
-		"",
-		"initial begin",
-		"\t#1 rst_n<=1'bx;clk<=1'bx;",
-		"\t#(CLK_PERIOD*3) rst_n<=1;",
-		"\t#(CLK_PERIOD*3) rst_n<=0;clk<=0;",
-		"\trepeat(5) @(posedge clk);",
-		"\trst_n<=1;",
-		"\t@(posedge clk);",
-		"\trepeat(2) @(posedge clk);",
-		"\t\\$finish(2);",
-		"end",
-		"",
-		"endmodule",
-		"`default_nettype wire"
-	],
-	description: "testbench template"
-}
-};
-
-export { always, alwaysnegclk, alwaysposclk, array, casex, casez, verilogVerilog as default, default_nettype, define, elsif, end, endif, forever, generate, genvar, ifdef, ifelse, ifndef, include, initial, integer, localparam, parameter, reg, regarray, regmemory, signed, ternary, timescale, undef, wire, wirearray };