@celox-sim/celox 0.1.12 → 0.1.13

package/dist/dut.d.ts.map

@@ -1 +1 @@
-{"version":3,"file":"dut.d.ts","sourceRoot":"","sources":["../src/dut.ts"],"names":[],"mappings":"AAAA;;;;;;;GAOG;AAEH,OAAO,KAAK,EACV,YAAY,EACZ,QAAQ,EACR,YAAY,EAEb,MAAM,YAAY,CAAC;AACpB,OAAO,KAAK,EAAE,aAAa,EAAE,MAAM,mBAAmB,CAAC;AAOvD;;;;;;GAMG;AACH,MAAM,WAAW,UAAU;IACzB,KAAK,EAAE,OAAO,CAAC;CAChB;AAqJD;;;;;;;;;GASG;AACH,wBAAgB,SAAS,CAAC,CAAC,EACzB,MAAM,EAAE,WAAW,GAAG,iBAAiB,EACvC,MAAM,EAAE,MAAM,CAAC,MAAM,EAAE,YAAY,CAAC,EACpC,QAAQ,EAAE,MAAM,CAAC,MAAM,EAAE,QAAQ,CAAC,EAClC,MAAM,EAAE,YAAY,EACpB,KAAK,EAAE,UAAU,EACjB,SAAS,CAAC,EAAE,aAAa,GACxB,CAAC,CA0EH;AAED;;;GAGG;AACH,wBAAgB,cAAc,CAC5B,MAAM,EAAE,WAAW,GAAG,iBAAiB,EACvC,SAAS,EAAE,aAAa,EACxB,MAAM,EAAE,YAAY,EACpB,KAAK,EAAE,UAAU,GAChB,MAAM,CAoER;AAmSD;;;GAGG;AACH,wBAAgB,aAAa,CAC3B,MAAM,EAAE,WAAW,GAAG,iBAAiB,EACvC,GAAG,EAAE,YAAY,GAChB,CAAC,KAAK,EAAE,MAAM,EAAE,IAAI,EAAE,MAAM,CAAC,CAe/B"}
+{"version":3,"file":"dut.d.ts","sourceRoot":"","sources":["../src/dut.ts"],"names":[],"mappings":"AAAA;;;;;;;GAOG;AAEH,OAAO,KAAK,EACV,YAAY,EACZ,QAAQ,EACR,YAAY,EAEb,MAAM,YAAY,CAAC;AACpB,OAAO,KAAK,EAAE,aAAa,EAAE,MAAM,mBAAmB,CAAC;AAOvD;;;;;;GAMG;AACH,MAAM,WAAW,UAAU;IACzB,KAAK,EAAE,OAAO,CAAC;CAChB;AAqJD;;;;;;;;;GASG;AACH,wBAAgB,SAAS,CAAC,CAAC,EACzB,MAAM,EAAE,WAAW,GAAG,iBAAiB,EACvC,MAAM,EAAE,MAAM,CAAC,MAAM,EAAE,YAAY,CAAC,EACpC,QAAQ,EAAE,MAAM,CAAC,MAAM,EAAE,QAAQ,CAAC,EAClC,MAAM,EAAE,YAAY,EACpB,KAAK,EAAE,UAAU,EACjB,SAAS,CAAC,EAAE,aAAa,GACxB,CAAC,CA0EH;AAED;;;GAGG;AACH,wBAAgB,cAAc,CAC5B,MAAM,EAAE,WAAW,GAAG,iBAAiB,EACvC,SAAS,EAAE,aAAa,EACxB,MAAM,EAAE,YAAY,EACpB,KAAK,EAAE,UAAU,GAChB,MAAM,CAoER;AA2SD;;;GAGG;AACH,wBAAgB,aAAa,CAC3B,MAAM,EAAE,WAAW,GAAG,iBAAiB,EACvC,GAAG,EAAE,YAAY,GAChB,CAAC,KAAK,EAAE,MAAM,EAAE,IAAI,EAAE,MAAM,CAAC,CAe/B"}

package/dist/dut.js

@@ -328,6 +328,15 @@ function createNestedDut(view, layout, members, prefix, handle, state) {
                 writable: false,
             });
         }
+        else if (memberPort.arrayDims && memberPort.arrayDims.length > 0) {
+            const arrayObj = createArrayDut(view, sig, memberPort, handle, state);
+            Object.defineProperty(obj, memberName, {
+                value: arrayObj,
+                enumerable: true,
+                configurable: false,
+                writable: false,
+            });
+        }
         else {
             defineSignalProperty(obj, memberName, view, sig, memberPort, handle, state);
         }

package/dist/dut.js.map

@@ -1 +1 @@
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package/package.json

@@ -1,6 +1,6 @@
 {
   "name": "@celox-sim/celox",
-  "version": "0.1.12",
+  "version": "0.1.13",
   "description": "TypeScript runtime for Celox HDL simulation",
   "type": "module",
   "main": "./dist/index.js",
@@ -29,7 +29,7 @@
   },
   "license": "MIT",
   "dependencies": {
-    "@celox-sim/celox-napi": "0.1.12"
+    "@celox-sim/celox-napi": "0.1.13"
   },
   "peerDependencies": {
     "vitest": ">=1.0.0"

package/src/dut.test.ts

@@ -670,6 +670,90 @@ describe("createDut — array ports", () => {
 // Interface (nested) ports
 // ---------------------------------------------------------------------------
 
+describe("createDut — interface ports with array members", () => {
+  test("interface member with arrayDims uses array accessor", () => {
+    // Interface array pattern: bus: modport Bus::consumer [2]
+    // Veryl expands to bus.data with arrayDims:[2], bus.valid with arrayDims:[2]
+    const buffer = makeBuffer(64);
+    const layout: Record<string, SignalLayout> = {
+      "bus.data":  { offset: 0, width: 8, byteSize: 2, is4state: false, direction: "input" },
+      "bus.valid": { offset: 2, width: 1, byteSize: 1, is4state: false, direction: "input" },
+    };
+    const ports: Record<string, PortInfo> = {
+      bus: {
+        direction: "inout",
+        type: "logic",
+        width: 0,
+        interface: {
+          data:  { direction: "input", type: "logic", width: 8, arrayDims: [2] },
+          valid: { direction: "input", type: "logic", width: 1, arrayDims: [2] },
+        },
+      },
+    };
+    const handle = mockHandle();
+    const state: DirtyState = { dirty: false };
+
+    const dut = createDut<{
+      bus: {
+        data:  { at(i: number): bigint; set(i: number, v: bigint): void; length: number };
+        valid: { at(i: number): bigint; set(i: number, v: bigint): void; length: number };
+      };
+    }>(buffer, layout, ports, handle, state);
+
+    // data: 2 elements of 8 bits each
+    dut.bus.data.set(0, 0xAAn);
+    dut.bus.data.set(1, 0xBBn);
+    expect(dut.bus.data.at(0)).toBe(0xAAn);
+    expect(dut.bus.data.at(1)).toBe(0xBBn);
+    expect(dut.bus.data.length).toBe(2);
+
+    // valid: 2 elements of 1 bit each (bit-packed)
+    dut.bus.valid.set(0, 1n);
+    dut.bus.valid.set(1, 0n);
+    expect(dut.bus.valid.at(0)).toBe(1n);
+    expect(dut.bus.valid.at(1)).toBe(0n);
+    expect(dut.bus.valid.length).toBe(2);
+  });
+
+  test("interface with mixed scalar and array members", () => {
+    const buffer = makeBuffer(64);
+    const layout: Record<string, SignalLayout> = {
+      "bus.data":  { offset: 0, width: 8, byteSize: 2, is4state: false, direction: "input" },
+      "bus.valid": { offset: 4, width: 1, byteSize: 1, is4state: false, direction: "input" },
+    };
+    const ports: Record<string, PortInfo> = {
+      bus: {
+        direction: "inout",
+        type: "logic",
+        width: 0,
+        interface: {
+          data:  { direction: "input", type: "logic", width: 8, arrayDims: [2] },
+          valid: { direction: "input", type: "logic", width: 1 },
+        },
+      },
+    };
+    const handle = mockHandle();
+    const state: DirtyState = { dirty: false };
+
+    const dut = createDut<{
+      bus: {
+        data:  { at(i: number): bigint; set(i: number, v: bigint): void; length: number };
+        valid: bigint;
+      };
+    }>(buffer, layout, ports, handle, state);
+
+    // Array member
+    dut.bus.data.set(0, 0x11n);
+    dut.bus.data.set(1, 0x22n);
+    expect(dut.bus.data.at(0)).toBe(0x11n);
+    expect(dut.bus.data.at(1)).toBe(0x22n);
+
+    // Scalar member
+    dut.bus.valid = 1n;
+    expect(dut.bus.valid).toBe(1n);
+  });
+});
+
 describe("createDut — interface ports", () => {
   test("nested interface members", () => {
     const buffer = makeBuffer(64);

package/src/dut.ts

@@ -446,6 +446,14 @@ function createNestedDut(
         configurable: false,
         writable: false,
       });
+    } else if (memberPort.arrayDims && memberPort.arrayDims.length > 0) {
+      const arrayObj = createArrayDut(view, sig, memberPort, handle, state);
+      Object.defineProperty(obj, memberName, {
+        value: arrayObj,
+        enumerable: true,
+        configurable: false,
+        writable: false,
+      });
     } else {
       defineSignalProperty(obj, memberName, view, sig, memberPort, handle, state);
     }

package/src/e2e.bench.ts

@@ -9,6 +9,9 @@
  *   4. Simulator::tick vs Simulation::step overhead
  */
 
+import { readFileSync } from "node:fs";
+import { resolve, dirname } from "node:path";
+import { fileURLToPath } from "node:url";
 import { bench, describe, afterAll } from "vitest";
 import { Simulator } from "./simulator.js";
 import { Simulation } from "./simulation.js";
@@ -18,6 +21,12 @@ import {
   createSimulatorBridge,
 } from "./napi-helpers.js";
 
+const __benchDir = dirname(fileURLToPath(import.meta.url));
+const VERYL_STD = resolve(__benchDir, "../../../deps/veryl/crates/std/veryl/src");
+function readVeryl(...parts: string[]): string {
+  return readFileSync(resolve(VERYL_STD, ...parts), "utf8");
+}
+
 const CODE = `
     module Top #(
         param N: u32 = 1000,
@@ -401,3 +410,308 @@ describe("optimize-flag", () => {
     { iterations: 3, time: 0 },
   );
 });
+
+// ────────────────────────────────────────────────────────────
+// Stdlib benchmarks — mirrors crates/celox/benches/simulation.rs
+// ────────────────────────────────────────────────────────────
+
+// --- Linear SEC (P=6): Hamming encoder/decoder, combinational ---
+
+const LINEAR_SEC_SRC =
+  readVeryl("coding/linear_sec_encoder.veryl") +
+  readVeryl("coding/linear_sec_decoder.veryl") +
+  `
+module Top #(
+    param P: u32 = 6,
+    const K: u32 = (1 << P) - 1,
+    const N: u32 = K - P,
+)(
+    i_word     : input  logic<N>,
+    o_codeword : output logic<K>,
+    o_word     : output logic<N>,
+    o_corrected: output logic,
+) {
+    inst u_enc: linear_sec_encoder #(P: P) (i_word, o_codeword);
+    inst u_dec: linear_sec_decoder #(P: P) (
+        i_codeword: o_codeword,
+        o_word,
+        o_corrected,
+    );
+}
+`;
+
+interface LinearSecPorts {
+  i_word: bigint;
+  readonly o_codeword: bigint;
+  readonly o_word: bigint;
+  readonly o_corrected: bigint;
+}
+
+describe("stdlib-linear-sec", () => {
+  bench(
+    "simulation_build_linear_sec_p6",
+    () => {
+      const sim = Simulator.fromSource<LinearSecPorts>(LINEAR_SEC_SRC, "Top");
+      sim.dispose();
+    },
+    { iterations: 3, time: 0 },
+  );
+
+  const sim = Simulator.fromSource<LinearSecPorts>(LINEAR_SEC_SRC, "Top");
+
+  afterAll(() => {
+    sim.dispose();
+  });
+
+  let linearSecInput = 0n;
+  bench("simulation_eval_linear_sec_p6_x1", () => {
+    sim.dut.i_word = linearSecInput++;
+    // biome-ignore lint: read to measure eval
+    sim.dut.o_word;
+  });
+
+  bench(
+    "simulation_eval_linear_sec_p6_x1000000",
+    () => {
+      let input = 0n;
+      for (let i = 0; i < 1_000_000; i++) {
+        sim.dut.i_word = input++;
+        // biome-ignore lint: read to measure eval
+        sim.dut.o_word;
+      }
+    },
+    { iterations: 3, time: 0 },
+  );
+
+  bench(
+    "testbench_eval_linear_sec_p6_x1000000",
+    () => {
+      let input = 0n;
+      for (let i = 0; i < 1_000_000; i++) {
+        sim.dut.i_word = input++;
+        // biome-ignore lint: read corrected flag
+        sim.dut.o_corrected;
+      }
+    },
+    { iterations: 3, time: 0 },
+  );
+});
+
+// --- Countones (W=64): recursive combinational popcount tree ---
+
+const COUNTONES_SRC =
+  readVeryl("countones/countones.veryl") +
+  `
+module Top (
+    i_data: input  logic<64>,
+    o_ones: output logic<7>,
+) {
+    inst u: countones #(W: 64) (i_data, o_ones);
+}
+`;
+
+interface CountonesPorts {
+  i_data: bigint;
+  readonly o_ones: bigint;
+}
+
+describe("stdlib-countones", () => {
+  bench(
+    "simulation_build_countones_w64",
+    () => {
+      const sim = Simulator.fromSource<CountonesPorts>(COUNTONES_SRC, "Top");
+      sim.dispose();
+    },
+    { iterations: 3, time: 0 },
+  );
+
+  const sim = Simulator.fromSource<CountonesPorts>(COUNTONES_SRC, "Top");
+
+  afterAll(() => {
+    sim.dispose();
+  });
+
+  let countonesInput = 0n;
+  bench("simulation_eval_countones_w64_x1", () => {
+    sim.dut.i_data = countonesInput++;
+    // biome-ignore lint: read to measure eval
+    sim.dut.o_ones;
+  });
+
+  bench(
+    "simulation_eval_countones_w64_x1000000",
+    () => {
+      let input = 0n;
+      for (let i = 0; i < 1_000_000; i++) {
+        sim.dut.i_data = input++;
+        // biome-ignore lint: read to measure eval
+        sim.dut.o_ones;
+      }
+    },
+    { iterations: 3, time: 0 },
+  );
+});
+
+// --- std::counter (WIDTH=32): sequential up-counter ---
+
+const STD_COUNTER_SRC =
+  readVeryl("counter/counter.veryl") +
+  `
+module Top (
+    clk    : input  clock,
+    rst    : input  reset,
+    i_up   : input  logic,
+    o_count: output logic<32>,
+) {
+    inst u: counter #(WIDTH: 32) (
+        i_clk       : clk,
+        i_rst       : rst,
+        i_clear     : 1'b0,
+        i_set       : 1'b0,
+        i_set_value : 32'b0,
+        i_up,
+        i_down      : 1'b0,
+        o_count,
+        o_count_next: _,
+        o_wrap_around: _,
+    );
+}
+`;
+
+interface StdCounterPorts {
+  rst: bigint;
+  i_up: bigint;
+  readonly o_count: bigint;
+}
+
+describe("stdlib-counter", () => {
+  bench(
+    "simulation_build_std_counter_w32",
+    () => {
+      const sim = Simulator.fromSource<StdCounterPorts>(STD_COUNTER_SRC, "Top");
+      sim.dispose();
+    },
+    { iterations: 3, time: 0 },
+  );
+
+  const sim = Simulator.fromSource<StdCounterPorts>(STD_COUNTER_SRC, "Top");
+  sim.dut.rst = 1n;
+  sim.dut.i_up = 0n;
+  sim.tick();
+  sim.dut.rst = 0n;
+  sim.dut.i_up = 1n;
+  sim.tick();
+
+  afterAll(() => {
+    sim.dispose();
+  });
+
+  bench("simulation_tick_std_counter_w32_x1", () => {
+    sim.tick();
+  });
+
+  bench(
+    "simulation_tick_std_counter_w32_x1000000",
+    () => {
+      for (let i = 0; i < 1_000_000; i++) {
+        sim.tick();
+      }
+    },
+    { iterations: 3, time: 0 },
+  );
+
+  bench(
+    "testbench_tick_std_counter_w32_x1000000",
+    () => {
+      for (let i = 0; i < 1_000_000; i++) {
+        sim.tick();
+        // biome-ignore lint: read to measure testbench cycle
+        sim.dut.o_count;
+      }
+    },
+    { iterations: 3, time: 0 },
+  );
+});
+
+// --- std::gray_counter (WIDTH=32): Gray-encoded sequential counter ---
+
+const GRAY_COUNTER_SRC =
+  readVeryl("counter/counter.veryl") +
+  readVeryl("gray/gray_encoder.veryl") +
+  readVeryl("gray/gray_counter.veryl") +
+  `
+module Top (
+    clk    : input  clock,
+    rst    : input  reset,
+    i_up   : input  logic,
+    o_count: output logic<32>,
+) {
+    inst u: gray_counter #(WIDTH: 32) (
+        i_clk       : clk,
+        i_rst       : rst,
+        i_clear     : 1'b0,
+        i_set       : 1'b0,
+        i_set_value : 32'b0,
+        i_up,
+        i_down      : 1'b0,
+        o_count,
+        o_count_next: _,
+        o_wrap_around: _,
+    );
+}
+`;
+
+interface GrayCounterPorts {
+  rst: bigint;
+  i_up: bigint;
+  readonly o_count: bigint;
+}
+
+describe("stdlib-gray-counter", () => {
+  bench(
+    "simulation_build_gray_counter_w32",
+    () => {
+      const sim = Simulator.fromSource<GrayCounterPorts>(GRAY_COUNTER_SRC, "Top");
+      sim.dispose();
+    },
+    { iterations: 3, time: 0 },
+  );
+
+  const sim = Simulator.fromSource<GrayCounterPorts>(GRAY_COUNTER_SRC, "Top");
+  sim.dut.rst = 1n;
+  sim.dut.i_up = 0n;
+  sim.tick();
+  sim.dut.rst = 0n;
+  sim.dut.i_up = 1n;
+  sim.tick();
+
+  afterAll(() => {
+    sim.dispose();
+  });
+
+  bench("simulation_tick_gray_counter_w32_x1", () => {
+    sim.tick();
+  });
+
+  bench(
+    "simulation_tick_gray_counter_w32_x1000000",
+    () => {
+      for (let i = 0; i < 1_000_000; i++) {
+        sim.tick();
+      }
+    },
+    { iterations: 3, time: 0 },
+  );
+
+  bench(
+    "testbench_tick_gray_counter_w32_x1000000",
+    () => {
+      for (let i = 0; i < 1_000_000; i++) {
+        sim.tick();
+        // biome-ignore lint: read to measure testbench cycle
+        sim.dut.o_count;
+      }
+    },
+    { iterations: 3, time: 0 },
+  );
+});

package/src/e2e.test.ts

@@ -1566,7 +1566,7 @@ describe("E2E: parameter override — DUT correctness", () => {
     sim.dispose();
   });
 
-  test("param value reflected in logic via fromSource", () => {
+  test.skip("param value reflected in logic via fromSource", () => { // blocked by upstream Veryl IR bug
     interface Ports {
       a: bigint;
       readonly b: bigint;
@@ -1889,6 +1889,55 @@ module Top (
   });
 });
 
+// ---------------------------------------------------------------------------
+// Interface array port (modport [N])
+// ---------------------------------------------------------------------------
+
+const INTERFACE_ARRAY_SOURCE = `
+interface Bus {
+    var data:  logic<8>;
+    var valid: logic;
+    modport consumer {
+        data:  input,
+        valid: input,
+    }
+}
+
+module Top (
+    bus: modport Bus::consumer [2],
+    out: output logic<8>,
+) {
+    assign out = bus.data[0] + bus.data[1];
+}
+`;
+
+describe("E2E: interface array port (modport [N])", () => {
+  test("interface array members accessible via .at()/.set()", () => {
+    interface TopPorts {
+      bus: {
+        data: { at(i: number): bigint; set(i: number, v: bigint): void; length: number };
+        valid: { at(i: number): bigint; set(i: number, v: bigint): void; length: number };
+      };
+      readonly out: bigint;
+    }
+
+    const sim = Simulator.fromSource<TopPorts>(INTERFACE_ARRAY_SOURCE, "Top");
+
+    sim.dut.bus.data.set(0, 0x10n);
+    sim.dut.bus.data.set(1, 0x20n);
+    expect(sim.dut.out).toBe(0x30n);
+
+    sim.dut.bus.data.set(0, 0xAAn);
+    sim.dut.bus.data.set(1, 0x11n);
+    expect(sim.dut.out).toBe(0xBBn);
+
+    expect(sim.dut.bus.data.length).toBe(2);
+    expect(sim.dut.bus.valid.length).toBe(2);
+
+    sim.dispose();
+  });
+});
+
 // ---------------------------------------------------------------------------
 // Bug fix: 1-bit unpacked array port (logic [N])
 // ---------------------------------------------------------------------------