npm - @celox-sim/celox - Versions diffs - 0.1.11 → 0.1.12 - Mend

@celox-sim/celox 0.1.11 → 0.1.12

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.

Files changed (17) hide show

package/dist/dut.d.ts.map +1 -1
package/dist/dut.js +97 -1
package/dist/dut.js.map +1 -1
package/dist/napi-helpers.d.ts +5 -0
package/dist/napi-helpers.d.ts.map +1 -1
package/dist/napi-helpers.js +34 -2
package/dist/napi-helpers.js.map +1 -1
package/dist/simulation.d.ts +1 -0
package/dist/simulation.d.ts.map +1 -1
package/dist/simulation.js +6 -3
package/dist/simulation.js.map +1 -1
package/package.json +2 -2
package/src/dut.test.ts +187 -0
package/src/dut.ts +123 -1
package/src/e2e.test.ts +329 -2
package/src/napi-helpers.ts +37 -2
package/src/simulation.ts +6 -2

package/dist/dut.d.ts.map CHANGED Viewed

	@@ -1 +1 @@
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1	+ {"version":3,"file":"dut.d.ts","sourceRoot":"","sources":["../src/dut.ts"],"names":[],"mappings":"AAAA;;;;;;;GAOG;AAEH,OAAO,KAAK,EACV,YAAY,EACZ,QAAQ,EACR,YAAY,EAEb,MAAM,YAAY,CAAC;AACpB,OAAO,KAAK,EAAE,aAAa,EAAE,MAAM,mBAAmB,CAAC;AAOvD;;;;;;GAMG;AACH,MAAM,WAAW,UAAU;IACzB,KAAK,EAAE,OAAO,CAAC;CAChB;AAqJD;;;;;;;;;GASG;AACH,wBAAgB,SAAS,CAAC,CAAC,EACzB,MAAM,EAAE,WAAW,GAAG,iBAAiB,EACvC,MAAM,EAAE,MAAM,CAAC,MAAM,EAAE,YAAY,CAAC,EACpC,QAAQ,EAAE,MAAM,CAAC,MAAM,EAAE,QAAQ,CAAC,EAClC,MAAM,EAAE,YAAY,EACpB,KAAK,EAAE,UAAU,EACjB,SAAS,CAAC,EAAE,aAAa,GACxB,CAAC,CA0EH;AAED;;;GAGG;AACH,wBAAgB,cAAc,CAC5B,MAAM,EAAE,WAAW,GAAG,iBAAiB,EACvC,SAAS,EAAE,aAAa,EACxB,MAAM,EAAE,YAAY,EACpB,KAAK,EAAE,UAAU,GAChB,MAAM,CAoER;AAmSD;;;GAGG;AACH,wBAAgB,aAAa,CAC3B,MAAM,EAAE,WAAW,GAAG,iBAAiB,EACvC,GAAG,EAAE,YAAY,GAChB,CAAC,KAAK,EAAE,MAAM,EAAE,IAAI,EAAE,MAAM,CAAC,CAe/B"}

package/dist/dut.js CHANGED Viewed

@@ -210,6 +210,17 @@ export function createChildDut(buffer, hierarchy, handle, state) {
     for (const [name, port] of Object.entries(hierarchy.ports)) {
         if (port.type === "clock")
             continue;
+        // Handle nested interface port
+        if (port.interface) {
+            const nestedObj = createNestedDut(view, hierarchy.forDut, port.interface, name, handle, state);
+            Object.defineProperty(obj, name, {
+                value: nestedObj,
+                enumerable: true,
+                configurable: false,
+                writable: false,
+            });
+            continue;
+        }
         const sig = hierarchy.forDut[name];
         if (!sig)
             continue;
@@ -326,15 +337,100 @@ function createNestedDut(view, layout, members, prefix, handle, state) {
 // ---------------------------------------------------------------------------
 // Array port accessor
 // ---------------------------------------------------------------------------
+/**
+ * Read a single element from a bit-packed byte region.
+ *
+ * The JIT stores array elements contiguously at the bit level:
+ * element i occupies bits [i*W .. (i+1)*W - 1] starting at baseOffset.
+ * Used when elementWidth < 8 (sub-byte elements).
+ */
+function readBitPackedElement(view, baseOffset, elementWidth, i) {
+    const bitStart = i * elementWidth;
+    const byteStart = baseOffset + (bitStart >> 3);
+    const bitShift = bitStart & 7;
+    const mask = (1 << elementWidth) - 1;
+    if (bitShift + elementWidth <= 8) {
+        return (view.getUint8(byteStart) >> bitShift) & mask;
+    }
+    // Spans two bytes
+    const lo = view.getUint8(byteStart);
+    const hi = view.getUint8(byteStart + 1);
+    return ((lo | (hi << 8)) >> bitShift) & mask;
+}
+/**
+ * Write a single element into a bit-packed byte region (read-modify-write).
+ *
+ * Used when elementWidth < 8 (sub-byte elements).
+ */
+function writeBitPackedElement(view, baseOffset, elementWidth, i, value) {
+    const bitStart = i * elementWidth;
+    const byteStart = baseOffset + (bitStart >> 3);
+    const bitShift = bitStart & 7;
+    const mask = (1 << elementWidth) - 1;
+    const maskedValue = value & mask;
+    const lo = view.getUint8(byteStart);
+    view.setUint8(byteStart, (lo & ~((mask << bitShift) & 0xff)) | ((maskedValue << bitShift) & 0xff));
+    if (bitShift + elementWidth > 8) {
+        const bitsInLo = 8 - bitShift;
+        const hi = view.getUint8(byteStart + 1);
+        const hiMask = mask >> bitsInLo;
+        view.setUint8(byteStart + 1, (hi & ~hiMask) | (maskedValue >> bitsInLo));
+    }
+}
 function createArrayDut(view, baseSig, port, handle, state) {
     const dims = port.arrayDims;
     const elementWidth = port.width;
-    const elementByteSize = Math.ceil(elementWidth / 8);
     const totalElements = dims.reduce((a, b) => a * b, 1);
     const isOutput = port.direction === "output";
     const isInput = port.direction === "input";
     const baseOffset = baseSig.offset;
     const is4state = baseSig.is4state;
+    if (elementWidth < 8) {
+        // Sub-byte elements: the JIT stores them bit-packed.
+        // Element i occupies bits [i*W .. (i+1)*W - 1] starting at baseOffset.
+        // For 4-state signals the mask region starts immediately after the value bytes.
+        const totalValueBytes = Math.ceil(totalElements * elementWidth / 8);
+        const maskBase = baseOffset + totalValueBytes;
+        return {
+            length: totalElements,
+            at(i) {
+                if (state.dirty && !isInput) {
+                    handle.evalComb();
+                    state.dirty = false;
+                }
+                return BigInt(readBitPackedElement(view, baseOffset, elementWidth, i));
+            },
+            set(i, value) {
+                if (isOutput) {
+                    throw new Error("Cannot write to output array port");
+                }
+                if (value === Symbol.for("veryl:X")) {
+                    if (!is4state) {
+                        throw new Error("Array port is not 4-state; cannot assign X");
+                    }
+                    writeBitPackedElement(view, baseOffset, elementWidth, i, 0);
+                    writeBitPackedElement(view, maskBase, elementWidth, i, (1 << elementWidth) - 1);
+                }
+                else if (isFourStateValue(value)) {
+                    if (!is4state) {
+                        throw new Error("Array port is not 4-state; cannot assign FourState");
+                    }
+                    writeBitPackedElement(view, baseOffset, elementWidth, i, Number(value.value));
+                    writeBitPackedElement(view, maskBase, elementWidth, i, Number(value.mask));
+                }
+                else {
+                    const bigVal = typeof value === "bigint" ? value : BigInt(value);
+                    writeBitPackedElement(view, baseOffset, elementWidth, i, Number(bigVal));
+                    if (is4state) {
+                        writeBitPackedElement(view, maskBase, elementWidth, i, 0);
+                    }
+                }
+                state.dirty = true;
+            },
+        };
+    }
+    // elementWidth >= 8: byte-aligned stride.
+    const elementByteSize = Math.ceil(elementWidth / 8);
     return {
         length: totalElements,
         at(i) {

package/dist/dut.js.map CHANGED Viewed

	@@ -1 +1 @@
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package/dist/napi-helpers.d.ts CHANGED Viewed

@@ -30,6 +30,7 @@ export interface RawNapiSimulationHandle {
     readonly hierarchyJson: string;
     readonly stableSize: number;
     readonly totalSize: number;
+    readonly defaultMaxSteps: number | null;
     addClock(eventId: number, period: number, initialDelay: number): void;
     schedule(eventId: number, time: number, value: number): void;
     runUntil(endTime: number): void;
@@ -129,6 +130,10 @@ export declare function parseNapiLayout(json: string): {
 /**
  * Build PortInfo records from the NAPI layout signals.
  * This auto-detects port metadata so users don't need to hand-write ModuleDefinition.
+ *
+ * Hierarchical signal names (e.g. "bus.data", "bus.valid" from an interface port)
+ * are grouped into a nested PortInfo with an `interface` map so that createDut can
+ * expose them as `dut.bus.data` and `dut.bus.valid`.
  */
 export declare function buildPortsFromLayout(signals: Record<string, SignalLayout & {
     typeKind: string;

package/dist/napi-helpers.d.ts.map CHANGED Viewed

	@@ -1 +1 @@
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package/dist/napi-helpers.js CHANGED Viewed

@@ -165,9 +165,14 @@ export function parseNapiLayout(json) {
 /**
  * Build PortInfo records from the NAPI layout signals.
  * This auto-detects port metadata so users don't need to hand-write ModuleDefinition.
+ *
+ * Hierarchical signal names (e.g. "bus.data", "bus.valid" from an interface port)
+ * are grouped into a nested PortInfo with an `interface` map so that createDut can
+ * expose them as `dut.bus.data` and `dut.bus.valid`.
  */
 export function buildPortsFromLayout(signals, _events) {
-    const ports = {};
+    // Step 1: Build flat PortInfo for every signal name
+    const flat = {};
     for (const [name, sig] of Object.entries(signals)) {
         const typeKind = sig.typeKind;
         let portType;
@@ -192,7 +197,34 @@ export function buildPortsFromLayout(signals, _events) {
         if (sig.arrayDims && sig.arrayDims.length > 0) {
             port.arrayDims = sig.arrayDims;
         }
-        ports[name] = port;
+        flat[name] = port;
+    }
+    // Step 2: Group hierarchical signals (e.g. "bus.data") into nested PortInfo.
+    // Veryl interface ports are exactly one level deep, so "bus.data" → parent "bus",
+    // member "data". The parent entry receives an `interface` map of its members;
+    // the flat layout keys are kept as-is so createNestedDut can look them up.
+    const ports = {};
+    const ifMaps = new Map();
+    for (const [name, port] of Object.entries(flat)) {
+        const dotIdx = name.indexOf(".");
+        if (dotIdx < 0) {
+            ports[name] = port;
+            continue;
+        }
+        // Hierarchical signal: first segment is the interface port name
+        const parentName = name.slice(0, dotIdx);
+        const memberName = name.slice(dotIdx + 1);
+        if (!ifMaps.has(parentName)) {
+            const ifMap = {};
+            ifMaps.set(parentName, ifMap);
+            ports[parentName] = {
+                direction: "inout",
+                type: "logic",
+                width: 0,
+                interface: ifMap,
+            };
+        }
+        ifMaps.get(parentName)[memberName] = port;
     }
     return ports;
 }

package/dist/napi-helpers.js.map CHANGED Viewed

	@@ -1 +1 @@
1	- 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package/dist/simulation.d.ts CHANGED Viewed

@@ -24,6 +24,7 @@ export declare class Simulation<P = Record<string, unknown>> {
     private readonly _buffer;
     private readonly _layout;
     private readonly _clocks;
+    private readonly _defaultMaxSteps;
     private _disposed;
     private constructor();
     /**

package/dist/simulation.d.ts.map CHANGED Viewed

	@@ -1 +1 @@
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package/dist/simulation.js CHANGED Viewed

@@ -26,14 +26,16 @@ export class Simulation {
     _buffer;
     _layout;
     _clocks = new Map();
+    _defaultMaxSteps;
     _disposed = false;
-    constructor(handle, dut, events, state, buffer, layout) {
+    constructor(handle, dut, events, state, buffer, layout, defaultMaxSteps) {
         this._handle = handle;
         this._dut = dut;
         this._events = events;
         this._state = state;
         this._buffer = buffer;
         this._layout = layout;
+        this._defaultMaxSteps = defaultMaxSteps;
     }
     /**
      * Create a Simulation for the given module.
@@ -109,10 +111,11 @@ export class Simulation {
         const hierarchy = parseHierarchyLayout(raw.hierarchyJson, events);
         const ports = buildPortsFromLayout(layout.signals, events);
         const buf = raw.sharedMemory().buffer;
+        const defaultMaxSteps = raw.defaultMaxSteps ?? undefined;
         const state = { dirty: false };
         const handle = wrapDirectSimulationHandle(raw);
         const dut = createDut(buf, layout.forDut, ports, handle, state, hierarchy);
-        return new Simulation(handle, dut, events, state, buf, layout.signals);
+        return new Simulation(handle, dut, events, state, buf, layout.signals, defaultMaxSteps);
     }
     /** The DUT accessor object — read/write ports as plain properties. */
     get dut() {
@@ -203,7 +206,7 @@ export class Simulation {
      */
     waitUntil(condition, opts) {
         this.ensureAlive();
-        const max = opts?.maxSteps ?? 100_000;
+        const max = opts?.maxSteps ?? this._defaultMaxSteps ?? 100_000;
         let steps = 0;
         while (!condition()) {
             const t = this._handle.step();

package/dist/simulation.js.map CHANGED Viewed

	@@ -1 +1 @@
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package/package.json CHANGED Viewed

@@ -1,6 +1,6 @@
 {
   "name": "@celox-sim/celox",
-  "version": "0.1.11",
+  "version": "0.1.12",
   "description": "TypeScript runtime for Celox HDL simulation",
   "type": "module",
   "main": "./dist/index.js",
@@ -29,7 +29,7 @@
   },
   "license": "MIT",
   "dependencies": {
-    "@celox-sim/celox-napi": "0.1.11"
+    "@celox-sim/celox-napi": "0.1.12"
   },
   "peerDependencies": {
     "vitest": ">=1.0.0"

package/src/dut.test.ts CHANGED Viewed

@@ -477,6 +477,193 @@ describe("createDut — array ports", () => {
     expect(dut.data.at(3)).toBe(0xDDn);
     expect(dut.data.length).toBe(4);
   });
+  test("1-bit elements (logic [N]): bit-packed read/write", () => {
+    // logic[4]: 4 elements of 1 bit each = 1 byte total in native memory
+    const buffer = makeBuffer(64);
+    const layout: Record<string, SignalLayout> = {
+      push: { offset: 0, width: 1, byteSize: 1, is4state: false, direction: "input" },
+    };
+    const ports: Record<string, PortInfo> = {
+      push: { direction: "input", type: "logic", width: 1, arrayDims: [4] },
+    };
+    const handle = mockHandle();
+    const state: DirtyState = { dirty: false };
+    const dut = createDut<{ push: { at(i: number): bigint; set(i: number, v: bigint): void; length: number } }>(
+      buffer, layout, ports, handle, state,
+    );
+    dut.push.set(0, 1n);
+    dut.push.set(1, 1n);
+    dut.push.set(2, 0n);
+    dut.push.set(3, 1n);
+    expect(dut.push.at(0)).toBe(1n);
+    expect(dut.push.at(1)).toBe(1n);
+    expect(dut.push.at(2)).toBe(0n);
+    expect(dut.push.at(3)).toBe(1n);
+    expect(dut.push.length).toBe(4);
+    // Verify native layout: all 4 elements packed in byte 0
+    const view = new DataView(buffer);
+    expect(view.getUint8(0)).toBe(0b1011); // bits 0,1,3 set = 0x0B
+    expect(view.getUint8(1)).toBe(0);      // no overflow into byte 1
+  });
+  test("1-bit elements: writes don't corrupt adjacent elements", () => {
+    const buffer = makeBuffer(64);
+    const layout: Record<string, SignalLayout> = {
+      bits: { offset: 0, width: 1, byteSize: 1, is4state: false, direction: "input" },
+    };
+    const ports: Record<string, PortInfo> = {
+      bits: { direction: "input", type: "logic", width: 1, arrayDims: [8] },
+    };
+    const handle = mockHandle();
+    const state: DirtyState = { dirty: false };
+    const dut = createDut<{ bits: { at(i: number): bigint; set(i: number, v: bigint): void } }>(
+      buffer, layout, ports, handle, state,
+    );
+    // Set element 0; verify element 1 unaffected
+    dut.bits.set(0, 1n);
+    expect(dut.bits.at(0)).toBe(1n);
+    dut.bits.set(1, 1n);
+    expect(dut.bits.at(0)).toBe(1n);  // element 0 must not be corrupted
+    expect(dut.bits.at(1)).toBe(1n);
+    // Clear element 0; element 1 must remain set
+    dut.bits.set(0, 0n);
+    expect(dut.bits.at(0)).toBe(0n);
+    expect(dut.bits.at(1)).toBe(1n);
+  });
+  test("1-bit elements: 8 elements span exactly one byte", () => {
+    const buffer = makeBuffer(64);
+    const layout: Record<string, SignalLayout> = {
+      bits: { offset: 2, width: 1, byteSize: 1, is4state: false, direction: "input" },
+    };
+    const ports: Record<string, PortInfo> = {
+      bits: { direction: "input", type: "logic", width: 1, arrayDims: [8] },
+    };
+    const handle = mockHandle();
+    const state: DirtyState = { dirty: false };
+    const dut = createDut<{ bits: { at(i: number): bigint; set(i: number, v: bigint): void } }>(
+      buffer, layout, ports, handle, state,
+    );
+    // Set all 8 bits
+    for (let i = 0; i < 8; i++) dut.bits.set(i, 1n);
+    const view = new DataView(buffer);
+    expect(view.getUint8(2)).toBe(0xff);
+    // Clear alternating bits
+    for (let i = 0; i < 8; i += 2) dut.bits.set(i, 0n);
+    expect(view.getUint8(2)).toBe(0b10101010);
+  });
+  test("elementWidth=3: elements spanning byte boundaries read/write correctly", () => {
+    // logic<3>[6]: 6 × 3 = 18 bits = 3 bytes
+    // Element 2: bitStart=6, spans bytes 0→1  ← cross-byte write/read path
+    // Element 5: bitStart=15, spans bytes 1→2 ← cross-byte write/read path
+    const buffer = makeBuffer(64);
+    const layout: Record<string, SignalLayout> = {
+      data: { offset: 0, width: 3, byteSize: 1, is4state: false, direction: "input" },
+    };
+    const ports: Record<string, PortInfo> = {
+      data: { direction: "input", type: "logic", width: 3, arrayDims: [6] },
+    };
+    const handle = mockHandle();
+    const state: DirtyState = { dirty: false };
+    const dut = createDut<{ data: { at(i: number): bigint; set(i: number, v: bigint): void; length: number } }>(
+      buffer, layout, ports, handle, state,
+    );
+    // Set all 6 elements to distinct values 1..6
+    for (let i = 0; i < 6; i++) dut.data.set(i, BigInt(i + 1));
+    for (let i = 0; i < 6; i++) expect(dut.data.at(i)).toBe(BigInt(i + 1));
+    // Overwrite the two cross-byte elements and verify neighbours are unaffected
+    dut.data.set(2, 0b101n);  // bitStart=6, crosses byte 0→1
+    expect(dut.data.at(2)).toBe(5n);
+    expect(dut.data.at(1)).toBe(2n);  // neighbour below
+    expect(dut.data.at(3)).toBe(4n);  // neighbour above
+    dut.data.set(5, 0b110n);  // bitStart=15, crosses byte 1→2
+    expect(dut.data.at(5)).toBe(6n);
+    expect(dut.data.at(4)).toBe(5n);  // neighbour below
+  });
+  test("1-bit 4-state: X writes value=0 and mask=1 at correct byte offset", () => {
+    // logic[8] with 4-state: value in byte 0 (bits 0-7 = elements 0-7),
+    // mask in byte 1 (bits 0-7 = masks for elements 0-7).
+    // totalValueBytes = ceil(8*1/8) = 1, so maskBase = offset + 1.
+    const buffer = makeBuffer(64);
+    const layout: Record<string, SignalLayout> = {
+      bits: { offset: 0, width: 1, byteSize: 1, is4state: true, direction: "input" },
+    };
+    const ports: Record<string, PortInfo> = {
+      bits: { direction: "input", type: "logic", width: 1, arrayDims: [8], is4state: true },
+    };
+    const handle = mockHandle();
+    const state: DirtyState = { dirty: false };
+    const dut = createDut<{ bits: { at(i: number): bigint; set(i: number, v: unknown): void } }>(
+      buffer, layout, ports, handle, state,
+    );
+    const view = new DataView(buffer);
+    // Assign X to element 3: value bit 3 → 0, mask bit 3 → 1
+    dut.bits.set(3, X);
+    expect(view.getUint8(0) & 0b00001000).toBe(0);           // value: bit 3 = 0
+    expect(view.getUint8(1) & 0b00001000).toBe(0b00001000);  // mask:  bit 3 = 1
+    // Write a defined 1 to element 3: value bit 3 → 1, mask bit 3 → 0
+    dut.bits.set(3, 1n);
+    expect(view.getUint8(0) & 0b00001000).toBe(0b00001000);  // value: bit 3 = 1
+    expect(view.getUint8(1) & 0b00001000).toBe(0);           // mask:  bit 3 cleared
+    // Setting elements 0 and 7 to X should only affect those mask bits
+    dut.bits.set(0, X);
+    dut.bits.set(7, X);
+    expect(view.getUint8(1)).toBe(0b10000001);  // mask: bits 0 and 7 set
+  });
+  test("3-bit 4-state: mask region starts at ceil(totalBits/8) bytes after value", () => {
+    // logic<3>[5]: 5 × 3 = 15 bits → totalValueBytes = ceil(15/8) = 2
+    // value occupies bytes 0-1, mask occupies bytes 2-3; maskBase = offset + 2
+    const buffer = makeBuffer(64);
+    const layout: Record<string, SignalLayout> = {
+      data: { offset: 0, width: 3, byteSize: 1, is4state: true, direction: "input" },
+    };
+    const ports: Record<string, PortInfo> = {
+      data: { direction: "input", type: "logic", width: 3, arrayDims: [5], is4state: true },
+    };
+    const handle = mockHandle();
+    const state: DirtyState = { dirty: false };
+    const dut = createDut<{ data: { set(i: number, v: unknown): void } }>(
+      buffer, layout, ports, handle, state,
+    );
+    const view = new DataView(buffer);
+    // Assign X to element 0 (bitStart=0, no cross-byte): value bits 0-2 = 0, mask bits 0-2 = 0b111
+    dut.data.set(0, X);
+    expect(view.getUint8(0) & 0b111).toBe(0);    // value byte 0: bits 0-2 cleared
+    expect(view.getUint8(2) & 0b111).toBe(0b111); // mask byte 2: bits 0-2 set
+    expect(view.getUint8(1)).toBe(0);              // value byte 1: untouched
+    expect(view.getUint8(3)).toBe(0);              // mask byte 3: untouched
+    // Write a defined value to element 0, verify mask cleared
+    dut.data.set(0, 0b110n);
+    expect(view.getUint8(0) & 0b111).toBe(0b110);  // value bits 0-2 = 6
+    expect(view.getUint8(2) & 0b111).toBe(0);       // mask bits 0-2 cleared
+  });
 });
 // ---------------------------------------------------------------------------

package/src/dut.ts CHANGED Viewed

@@ -288,6 +288,25 @@ export function createChildDut(
   for (const [name, port] of Object.entries(hierarchy.ports)) {
     if (port.type === "clock") continue;
+    // Handle nested interface port
+    if (port.interface) {
+      const nestedObj = createNestedDut(
+        view,
+        hierarchy.forDut,
+        port.interface,
+        name,
+        handle,
+        state,
+      );
+      Object.defineProperty(obj, name, {
+        value: nestedObj,
+        enumerable: true,
+        configurable: false,
+        writable: false,
+      });
+      continue;
+    }
     const sig = hierarchy.forDut[name];
     if (!sig) continue;
@@ -439,6 +458,61 @@ function createNestedDut(
 // Array port accessor
 // ---------------------------------------------------------------------------
+/**
+ * Read a single element from a bit-packed byte region.
+ *
+ * The JIT stores array elements contiguously at the bit level:
+ * element i occupies bits [i*W .. (i+1)*W - 1] starting at baseOffset.
+ * Used when elementWidth < 8 (sub-byte elements).
+ */
+function readBitPackedElement(
+  view: DataView,
+  baseOffset: number,
+  elementWidth: number,
+  i: number,
+): number {
+  const bitStart = i * elementWidth;
+  const byteStart = baseOffset + (bitStart >> 3);
+  const bitShift = bitStart & 7;
+  const mask = (1 << elementWidth) - 1;
+  if (bitShift + elementWidth <= 8) {
+    return (view.getUint8(byteStart) >> bitShift) & mask;
+  }
+  // Spans two bytes
+  const lo = view.getUint8(byteStart);
+  const hi = view.getUint8(byteStart + 1);
+  return ((lo | (hi << 8)) >> bitShift) & mask;
+}
+/**
+ * Write a single element into a bit-packed byte region (read-modify-write).
+ *
+ * Used when elementWidth < 8 (sub-byte elements).
+ */
+function writeBitPackedElement(
+  view: DataView,
+  baseOffset: number,
+  elementWidth: number,
+  i: number,
+  value: number,
+): void {
+  const bitStart = i * elementWidth;
+  const byteStart = baseOffset + (bitStart >> 3);
+  const bitShift = bitStart & 7;
+  const mask = (1 << elementWidth) - 1;
+  const maskedValue = value & mask;
+  const lo = view.getUint8(byteStart);
+  view.setUint8(byteStart, (lo & ~((mask << bitShift) & 0xff)) | ((maskedValue << bitShift) & 0xff));
+  if (bitShift + elementWidth > 8) {
+    const bitsInLo = 8 - bitShift;
+    const hi = view.getUint8(byteStart + 1);
+    const hiMask = mask >> bitsInLo;
+    view.setUint8(byteStart + 1, (hi & ~hiMask) | (maskedValue >> bitsInLo));
+  }
+}
 function createArrayDut(
   view: DataView,
   baseSig: SignalLayout,
@@ -448,13 +522,61 @@ function createArrayDut(
 ): object {
   const dims = port.arrayDims!;
   const elementWidth = port.width;
-  const elementByteSize = Math.ceil(elementWidth / 8);
   const totalElements = dims.reduce((a, b) => a * b, 1);
   const isOutput = port.direction === "output";
   const isInput = port.direction === "input";
   const baseOffset = baseSig.offset;
   const is4state = baseSig.is4state;
+  if (elementWidth < 8) {
+    // Sub-byte elements: the JIT stores them bit-packed.
+    // Element i occupies bits [i*W .. (i+1)*W - 1] starting at baseOffset.
+    // For 4-state signals the mask region starts immediately after the value bytes.
+    const totalValueBytes = Math.ceil(totalElements * elementWidth / 8);
+    const maskBase = baseOffset + totalValueBytes;
+    return {
+      length: totalElements,
+      at(i: number): bigint {
+        if (state.dirty && !isInput) {
+          handle.evalComb();
+          state.dirty = false;
+        }
+        return BigInt(readBitPackedElement(view, baseOffset, elementWidth, i));
+      },
+      set(i: number, value: bigint | number | symbol | FourStateValue): void {
+        if (isOutput) {
+          throw new Error("Cannot write to output array port");
+        }
+        if (value === Symbol.for("veryl:X")) {
+          if (!is4state) {
+            throw new Error("Array port is not 4-state; cannot assign X");
+          }
+          writeBitPackedElement(view, baseOffset, elementWidth, i, 0);
+          writeBitPackedElement(view, maskBase, elementWidth, i, (1 << elementWidth) - 1);
+        } else if (isFourStateValue(value)) {
+          if (!is4state) {
+            throw new Error("Array port is not 4-state; cannot assign FourState");
+          }
+          writeBitPackedElement(view, baseOffset, elementWidth, i, Number(value.value));
+          writeBitPackedElement(view, maskBase, elementWidth, i, Number(value.mask));
+        } else {
+          const bigVal = typeof value === "bigint" ? value : BigInt(value as number);
+          writeBitPackedElement(view, baseOffset, elementWidth, i, Number(bigVal));
+          if (is4state) {
+            writeBitPackedElement(view, maskBase, elementWidth, i, 0);
+          }
+        }
+        state.dirty = true;
+      },
+    };
+  }
+  // elementWidth >= 8: byte-aligned stride.
+  const elementByteSize = Math.ceil(elementWidth / 8);
   return {
     length: totalElements,

package/src/e2e.test.ts CHANGED Viewed

@@ -497,9 +497,9 @@ module InitTest (
     const layout = parseNapiLayout(raw.layoutJson);
     const buf = raw.sharedMemory().buffer;
-    // logic port should have mask=0xFF (all X)
+    // logic port should have mask=0xFF (all X), X encoding: v=1, m=1
     const [valA, maskA] = readFourState(buf, layout.forDut.a);
-    expect(valA).toBe(0n);
+    expect(valA).toBe(0xFFn);
     expect(maskA).toBe(0xFFn);
     // bit port should have mask=0 (defined)
@@ -812,6 +812,11 @@ describe("E2E: 4-state high-level DUT API", () => {
     // In 4-state mode, count starts as X. Reset should clear it.
     // (default async_low: rst=0 is active)
     sim.dut.rst = 0n;
+    // Clear X on en before deactivating reset. In 4-state mode, en starts
+    // as X (v=1, m=1). The FF branch condition currently uses only the value
+    // bit, so X with v=1 is treated as "true" — a known limitation in FF
+    // conditional handling (combinational mux handles X correctly).
+    sim.dut.en = 0n;
     sim.tick();
     sim.dut.rst = 1n;
     sim.tick();
@@ -1695,4 +1700,326 @@ describe("E2E: celox.toml test sources", () => {
     expect(names).toContain("Adder");
     expect(names).toContain("Reg");
   });
+  test("[simulation] max_steps from celox.toml is used as waitUntil default", () => {
+    // celox.toml sets [simulation] max_steps = 20; waitUntil should honour it
+    // when no per-call maxSteps is provided.
+    const sim = Simulation.fromProject(CELOX_TOML_PROJECT, "Reg");
+    sim.addClock("clk", { period: 10 });
+    expect(() => sim.waitUntil(() => false)).toThrow(SimulationTimeoutError);
+    const err = (() => {
+      try { sim.waitUntil(() => false); } catch (e) { return e; }
+    })() as SimulationTimeoutError;
+    expect(err.steps).toBe(20);
+    sim.dispose();
+  });
+  test("[simulation] max_steps per-call override takes precedence over celox.toml", () => {
+    const sim = Simulation.fromProject(CELOX_TOML_PROJECT, "Reg");
+    sim.addClock("clk", { period: 10 });
+    // Per-call maxSteps=5 is lower than the toml default of 20
+    expect(() => sim.waitUntil(() => false, { maxSteps: 5 })).toThrow(SimulationTimeoutError);
+    const err = (() => {
+      try { sim.waitUntil(() => false, { maxSteps: 5 }); } catch (e) { return e; }
+    })() as SimulationTimeoutError;
+    expect(err.steps).toBe(5);
+    sim.dispose();
+  });
+});
+// ---------------------------------------------------------------------------
+// Interface port DUT accessor tests
+// ---------------------------------------------------------------------------
+// A module whose top-level port is a modport interface.
+// After Veryl expansion "sig.data" and "sig.valid" become individual ports.
+// buildPortsFromLayout must group them into a nested PortInfo so that the
+// DUT exposes them as dut.sig.data / dut.sig.valid.
+const INTERFACE_PORT_SOURCE = `
+interface Signal {
+    var data:  logic<8>;
+    var valid: logic;
+    modport src {
+        data:  output,
+        valid: output,
+    }
+    modport dst {
+        data:  input,
+        valid: input,
+    }
+}
+module Top (
+    sig: modport Signal::dst,
+    out: output logic<8>,
+) {
+    assign out = sig.data;
+}
+`;
+// A module that uses two instances connected via an interface so we can verify
+// that the hierarchy DUT also exposes nested accessors correctly.
+const INTERFACE_HIERARCHY_SOURCE = `
+interface Bus {
+    var data:  logic<8>;
+    var valid: logic;
+    modport producer {
+        data:  output,
+        valid: output,
+    }
+    modport consumer {
+        data:  input,
+        valid: input,
+    }
+}
+module Producer (
+    bus: modport Bus::producer,
+    val: input logic<8>,
+) {
+    assign bus.data  = val;
+    assign bus.valid = 1'b1;
+}
+module Consumer (
+    bus:  modport Bus::consumer,
+    out:  output logic<8>,
+    got:  output logic,
+) {
+    assign out = bus.data;
+    assign got = bus.valid;
+}
+module Top (
+    val: input  logic<8>,
+    out: output logic<8>,
+    got: output logic,
+) {
+    inst b:   Bus;
+    inst p:   Producer (bus: b, val: val);
+    inst c:   Consumer (bus: b, out: out, got: got);
+}
+`;
+describe("E2E: interface port DUT accessor", () => {
+  test("top-level interface port members accessible as nested dut properties", () => {
+    interface TopPorts {
+      sig: { data: bigint; valid: bigint };
+      readonly out: bigint;
+    }
+    const sim = Simulator.fromSource<TopPorts>(INTERFACE_PORT_SOURCE, "Top");
+    sim.dut.sig.data = 0x42n;
+    expect(sim.dut.out).toBe(0x42n);
+    sim.dut.sig.data = 0xFFn;
+    expect(sim.dut.out).toBe(0xFFn);
+    sim.dut.sig.data = 0x00n;
+    expect(sim.dut.out).toBe(0x00n);
+    sim.dispose();
+  });
+  test("writing to interface output member throws", () => {
+    // bus.data / bus.valid are outputs of Top — writing should throw.
+    const PRODUCER_ONLY = `
+interface Bus {
+    var data:  logic<8>;
+    var valid: logic;
+    modport src {
+        data:  output,
+        valid: output,
+    }
+}
+module Top (
+    bus: modport Bus::src,
+    val: input logic<8>,
+) {
+    assign bus.data  = val;
+    assign bus.valid = 1'b1;
+}
+`;
+    const sim = Simulator.fromSource(PRODUCER_ONLY, "Top");
+    expect(() => {
+      (sim.dut as any).bus.data = 0n;
+    }).toThrow("Cannot write to output port 'data'");
+    sim.dispose();
+  });
+  test("interface port propagates through sub-module instances", () => {
+    interface TopPorts {
+      val: bigint;
+      readonly out: bigint;
+      readonly got: bigint;
+    }
+    const sim = Simulator.fromSource<TopPorts>(INTERFACE_HIERARCHY_SOURCE, "Top");
+    sim.dut.val = 0xABn;
+    expect(sim.dut.out).toBe(0xABn);
+    expect(sim.dut.got).toBe(1n);
+    sim.dut.val = 0x00n;
+    expect(sim.dut.out).toBe(0x00n);
+    sim.dispose();
+  });
+  test("multiple interface port members are independently accessible", () => {
+    interface TopPorts {
+      sig: { data: bigint; valid: bigint };
+      readonly out: bigint;
+    }
+    const sim = Simulator.fromSource<TopPorts>(INTERFACE_PORT_SOURCE, "Top");
+    sim.dut.sig.data = 0x77n;
+    sim.dut.sig.valid = 1n;
+    expect(sim.dut.out).toBe(0x77n);
+    sim.dut.sig.data = 0x33n;
+    sim.dut.sig.valid = 0n;
+    expect(sim.dut.out).toBe(0x33n);
+    sim.dispose();
+  });
+});
+// ---------------------------------------------------------------------------
+// Bug fix: 1-bit unpacked array port (logic [N])
+// ---------------------------------------------------------------------------
+const ARRAY_1BIT_SOURCE = `
+module ArrayPassThrough (
+    clk: input  clock,
+    rst: input  reset,
+    en:  input  logic [4],
+    y0:  output logic,
+    y1:  output logic,
+    y2:  output logic,
+    y3:  output logic,
+) {
+    always_comb {
+        y0 = en[0];
+        y1 = en[1];
+        y2 = en[2];
+        y3 = en[3];
+    }
+}
+`;
+describe("E2E: 1-bit unpacked array port (logic [N])", () => {
+  test("each element is independently visible in hardware (issue #6)", () => {
+    interface Ports {
+      rst: bigint;
+      en: { at(i: number): bigint; set(i: number, v: bigint): void; length: number };
+      readonly y0: bigint;
+      readonly y1: bigint;
+      readonly y2: bigint;
+      readonly y3: bigint;
+    }
+    const sim = Simulator.fromSource<Ports>(ARRAY_1BIT_SOURCE, "ArrayPassThrough");
+    // Default: all inputs 0
+    sim.tick();
+    expect(sim.dut.y0).toBe(0n);
+    expect(sim.dut.y1).toBe(0n);
+    expect(sim.dut.y2).toBe(0n);
+    expect(sim.dut.y3).toBe(0n);
+    // Set element 0 only
+    sim.dut.en.set(0, 1n);
+    sim.tick();
+    expect(sim.dut.y0).toBe(1n);
+    expect(sim.dut.y1).toBe(0n);
+    expect(sim.dut.y2).toBe(0n);
+    expect(sim.dut.y3).toBe(0n);
+    // Set element 1 (was silently ignored before the fix)
+    sim.dut.en.set(0, 0n);
+    sim.dut.en.set(1, 1n);
+    sim.tick();
+    expect(sim.dut.y0).toBe(0n);
+    expect(sim.dut.y1).toBe(1n);
+    expect(sim.dut.y2).toBe(0n);
+    expect(sim.dut.y3).toBe(0n);
+    // Set elements 2 and 3
+    sim.dut.en.set(1, 0n);
+    sim.dut.en.set(2, 1n);
+    sim.dut.en.set(3, 1n);
+    sim.tick();
+    expect(sim.dut.y0).toBe(0n);
+    expect(sim.dut.y1).toBe(0n);
+    expect(sim.dut.y2).toBe(1n);
+    expect(sim.dut.y3).toBe(1n);
+    sim.dispose();
+  });
+  test("length property is correct", () => {
+    interface Ports {
+      rst: bigint;
+      en: { at(i: number): bigint; set(i: number, v: bigint): void; length: number };
+      readonly y0: bigint;
+      readonly y1: bigint;
+      readonly y2: bigint;
+      readonly y3: bigint;
+    }
+    const sim = Simulator.fromSource<Ports>(ARRAY_1BIT_SOURCE, "ArrayPassThrough");
+    expect(sim.dut.en.length).toBe(4);
+    sim.dispose();
+  });
+  test("4-state mode: X written to element i propagates only to output yi (verifies maskBase layout)", () => {
+    // This test validates that the maskBase = baseOffset + totalValueBytes assumption
+    // matches the actual JIT memory layout when fourState: true is used.
+    interface Ports {
+      rst: bigint;
+      en: { at(i: number): bigint; set(i: number, v: unknown): void; length: number };
+      readonly y0: bigint;
+      readonly y1: bigint;
+      readonly y2: bigint;
+      readonly y3: bigint;
+    }
+    const sim = Simulator.fromSource<Ports>(ARRAY_1BIT_SOURCE, "ArrayPassThrough", { fourState: true });
+    // Start with all defined zeros
+    for (let i = 0; i < 4; i++) sim.dut.en.set(i, 0n);
+    sim.tick();
+    // Set element 1 to X; only y1 should become X
+    sim.dut.en.set(1, X);
+    sim.tick();
+    expect(sim.fourState("y1").mask).not.toBe(0n);  // y1 = X
+    expect(sim.fourState("y0").mask).toBe(0n);       // y0 defined
+    expect(sim.fourState("y2").mask).toBe(0n);       // y2 defined
+    expect(sim.fourState("y3").mask).toBe(0n);       // y3 defined
+    // Set element 2 to X; y2 becomes X, y1 remains X
+    sim.dut.en.set(2, X);
+    sim.tick();
+    expect(sim.fourState("y1").mask).not.toBe(0n);
+    expect(sim.fourState("y2").mask).not.toBe(0n);
+    expect(sim.fourState("y0").mask).toBe(0n);
+    expect(sim.fourState("y3").mask).toBe(0n);
+    // Clear element 1 to defined 0; y1 becomes defined again
+    sim.dut.en.set(1, 0n);
+    sim.tick();
+    expect(sim.fourState("y1").mask).toBe(0n);
+    expect(sim.fourState("y2").mask).not.toBe(0n);
+    sim.dispose();
+  });
 });

package/src/napi-helpers.ts CHANGED Viewed

@@ -46,6 +46,7 @@ export interface RawNapiSimulationHandle {
   readonly hierarchyJson: string;
   readonly stableSize: number;
   readonly totalSize: number;
+  readonly defaultMaxSteps: number | null;
   addClock(eventId: number, period: number, initialDelay: number): void;
   schedule(eventId: number, time: number, value: number): void;
   runUntil(endTime: number): void;
@@ -300,12 +301,17 @@ export function parseNapiLayout(json: string): {
 /**
  * Build PortInfo records from the NAPI layout signals.
  * This auto-detects port metadata so users don't need to hand-write ModuleDefinition.
+ *
+ * Hierarchical signal names (e.g. "bus.data", "bus.valid" from an interface port)
+ * are grouped into a nested PortInfo with an `interface` map so that createDut can
+ * expose them as `dut.bus.data` and `dut.bus.valid`.
  */
 export function buildPortsFromLayout(
   signals: Record<string, SignalLayout & { typeKind: string; arrayDims?: number[] }>,
   _events: Record<string, number>,
 ): Record<string, PortInfo> {
-  const ports: Record<string, PortInfo> = {};
+  // Step 1: Build flat PortInfo for every signal name
+  const flat: Record<string, PortInfo> = {};
   for (const [name, sig] of Object.entries(signals)) {
     const typeKind = sig.typeKind;
@@ -329,7 +335,36 @@ export function buildPortsFromLayout(
     if (sig.arrayDims && sig.arrayDims.length > 0) {
       (port as { arrayDims: readonly number[] }).arrayDims = sig.arrayDims;
     }
-    ports[name] = port;
+    flat[name] = port;
+  }
+  // Step 2: Group hierarchical signals (e.g. "bus.data") into nested PortInfo.
+  // Veryl interface ports are exactly one level deep, so "bus.data" → parent "bus",
+  // member "data". The parent entry receives an `interface` map of its members;
+  // the flat layout keys are kept as-is so createNestedDut can look them up.
+  const ports: Record<string, PortInfo> = {};
+  const ifMaps = new Map<string, Record<string, PortInfo>>();
+  for (const [name, port] of Object.entries(flat)) {
+    const dotIdx = name.indexOf(".");
+    if (dotIdx < 0) {
+      ports[name] = port;
+      continue;
+    }
+    // Hierarchical signal: first segment is the interface port name
+    const parentName = name.slice(0, dotIdx);
+    const memberName = name.slice(dotIdx + 1);
+    if (!ifMaps.has(parentName)) {
+      const ifMap: Record<string, PortInfo> = {};
+      ifMaps.set(parentName, ifMap);
+      ports[parentName] = {
+        direction: "inout",
+        type: "logic",
+        width: 0,
+        interface: ifMap,
+      };
+    }
+    ifMaps.get(parentName)![memberName] = port;
   }
   return ports;

package/src/simulation.ts CHANGED Viewed

@@ -57,6 +57,7 @@ export class Simulation<P = Record<string, unknown>> {
   private readonly _buffer: ArrayBuffer | SharedArrayBuffer;
   private readonly _layout: Record<string, SignalLayout & { typeKind?: string; associatedClock?: string }>;
   private readonly _clocks = new Map<string, { period: number; eventId: number }>();
+  private readonly _defaultMaxSteps: number | undefined;
   private _disposed = false;
   private constructor(
@@ -66,6 +67,7 @@ export class Simulation<P = Record<string, unknown>> {
     state: DirtyState,
     buffer: ArrayBuffer | SharedArrayBuffer,
     layout: Record<string, SignalLayout & { typeKind?: string; associatedClock?: string }>,
+    defaultMaxSteps?: number,
   ) {
     this._handle = handle;
     this._dut = dut;
@@ -73,6 +75,7 @@ export class Simulation<P = Record<string, unknown>> {
     this._state = state;
     this._buffer = buffer;
     this._layout = layout;
+    this._defaultMaxSteps = defaultMaxSteps;
   }
   /**
@@ -185,12 +188,13 @@ export class Simulation<P = Record<string, unknown>> {
     const ports = buildPortsFromLayout(layout.signals, events);
     const buf = raw.sharedMemory().buffer;
+    const defaultMaxSteps = raw.defaultMaxSteps ?? undefined;
     const state: DirtyState = { dirty: false };
     const handle = wrapDirectSimulationHandle(raw);
     const dut = createDut<P>(buf, layout.forDut, ports, handle, state, hierarchy);
-    return new Simulation<P>(handle, dut, events, state, buf, layout.signals);
+    return new Simulation<P>(handle, dut, events, state, buf, layout.signals, defaultMaxSteps);
   }
   /** The DUT accessor object — read/write ports as plain properties. */
@@ -298,7 +302,7 @@ export class Simulation<P = Record<string, unknown>> {
     opts?: { maxSteps?: number },
   ): number {
     this.ensureAlive();
-    const max = opts?.maxSteps ?? 100_000;
+    const max = opts?.maxSteps ?? this._defaultMaxSteps ?? 100_000;
     let steps = 0;
     while (!condition()) {
       const t = this._handle.step();