@andrivet/z80-assembler 1.4.1 → 2.0.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- package/CHANGELOG.md +80 -0
- package/index.js +12 -12
- package/index.mjs +4477 -2353
- package/lib/compiler/Ast.d.ts +12 -1
- package/lib/compiler/Compiler.d.ts +12 -2
- package/lib/grammar/LowLevel.d.ts +2 -0
- package/lib/grammar/Parse.d.ts +2 -8
- package/lib/grammar/z80.d.ts +1258 -203
- package/package.json +1 -1
package/CHANGELOG.md
CHANGED
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@@ -1,5 +1,85 @@
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# Changelog
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## 2.0.0 - December 29, 2025
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* Fix propagation or source file name in case of compilation error.
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* Allowed device names are now:
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- zx81: automatic generation of system variables, BASIC REM lines, etc. for the ZX81
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- zx81-raw: without automatic generation of code but with translation for the ZX81 (characters)
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- z80: Generic Z80 code without any generation or translation specific to the ZX81. Characters are treated as ASCII (i.e. they are not translated).
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* Strings are translated only for zx81 or zx81raw devices, not z80.
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* Add undocumented instructions
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- Add support for IXh, IXl, IYh, IYl 8 bits registers
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- Add support of these registers for ADC, ADD, AND, CP, DEC, INC, OR, SBC, SUB and XOR
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- Add support of these registers for LD
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- Add support of (IX+d), (IY+d) to RL, RLC, RR, RRC, SLA, SRA, SRL
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- Add new instruction SSL
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- Add IN F, (C)
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- Add OUT (C), 0
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* Add fake instructions
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- 16-bit rotate and shift
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* rl qq
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* rr qq
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* sla qq
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* sll qq, sli qq
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* sra qq
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* srl qq
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- 16-bit load
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* ld qq, qq
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* ld qq, ix
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* ld qq, iy
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* ld qq, (hl)
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* ld qq, (ix + nn)
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* ld qq, (iy + nn)
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* ld ix, qq
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* ld iy, qq
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* ld iy, ix
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* ld ix, iy
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* ld (hl), qq
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* ld (ix + nn), qq
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* ld (iy + nn), qq
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- 16-bit load, increment
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* ldi qq, (hl)
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* ldi qq, (ix + nn)
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* ldi qq, (iy + nn)
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* ldi (hl), qq
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* ldi (ix + nn), qq
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* ldi (iy + nn), qq
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- 8-bit load, increment
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* ldi a, (bc)
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* ldi a, (de)
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* ldi r, (hl)
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* ldi r, (ix + nn)
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* ldi r, (iy + nn)
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* ldi (bc), a
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* ldi (de), a
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* ldi (hl), r
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* ldi (ix + nn), r
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* ldi (iy + nn), r
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* ldi (hl), n
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* ldi (ix + nn), n
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* ldi (iy + nn), n
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- 8-bit load, decrement
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* ldd a, (bc)
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* ldd a, (de)
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* ldd r, (hl)
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* ldd r, (ix + nn)
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* ldd r, (iy + nn)
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* ldd (bc), a
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* ldd (de), a
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* ldd (hl), r
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* ldd (ix + nn), r
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* ldd (iy + nn), r
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* ldd (hl), n
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* ldd (ix + nn), n
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* ldd (iy + nn), n
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- 16-bit arithmetic
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* adc de, ss
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* add de, ss
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* sbc de, ss
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* sub de, ss
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* sub hl, ss
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## 1.4.1 - December 22, 2025
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* Fix wrong publication
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