@aardworx/wombat.rendering 0.9.19 → 0.9.20

package/dist/runtime/derivedModes/gpuKernel.d.ts

@@ -1,4 +1,4 @@
-export declare const GPU_FLIP_CULL_BY_DET_WGSL = "\n// Per-RO record. Index i corresponds to drawId i in the scene's\n// flat RO table.\nstruct GpuRuleParams {\n  numROs:     u32,\n  declared:   u32,   // 0 = none, 1 = front, 2 = back  (must match CULL_MODE[] order in bitfield.ts)\n  _pad0:      u32,\n  _pad1:      u32,\n};\n\n@group(0) @binding(0) var<storage, read>       arena:        array<u32>;\n// One per-RO entry: byte offset within the arena of the ROs ModelTrafo\n// allocation header. Data is at offset + 16 (ALLOC_HEADER_PAD_TO).\n// 0xFFFFFFFFu means \"this RO does NOT have a flip-cull-by-det rule\".\n@group(0) @binding(1) var<storage, read>       roInputRefs:  array<u32>;\n@group(0) @binding(2) var<storage, read_write> roOutputs:    array<u32>;\n@group(0) @binding(3) var<uniform>             uIn:          GpuRuleParams;\n\n// Read a row-major mat4 from the arena at byte offset `refBytes + 16`\n// (header is 16 bytes wide due to ALLOC_HEADER_PAD_TO). Returns the\n// 3\u00D73 upper-left in row-major order: [m00,m01,m02, m10,m11,m12, m20,m21,m22].\nfn loadUpper3x3(refBytes: u32) -> array<f32, 9> {\n  let baseU32 = (refBytes + 16u) >> 2u;\n  // The arena is a Float32 storage of mat4 in row-major, 16 floats.\n  // Read 9 of them.\n  return array<f32, 9>(\n    bitcast<f32>(arena[baseU32 + 0u]),  bitcast<f32>(arena[baseU32 + 1u]),  bitcast<f32>(arena[baseU32 + 2u]),\n    bitcast<f32>(arena[baseU32 + 4u]),  bitcast<f32>(arena[baseU32 + 5u]),  bitcast<f32>(arena[baseU32 + 6u]),\n    bitcast<f32>(arena[baseU32 + 8u]),  bitcast<f32>(arena[baseU32 + 9u]),  bitcast<f32>(arena[baseU32 + 10u]),\n  );\n}\n\nfn det3x3(m: array<f32, 9>) -> f32 {\n  return m[0] * (m[4] * m[8] - m[5] * m[7])\n       - m[1] * (m[3] * m[8] - m[5] * m[6])\n       + m[2] * (m[3] * m[7] - m[4] * m[6]);\n}\n\n// Mirror of bitfield.ts CULL_MODE[] order: 0=none, 1=front, 2=back.\nfn flipCull(c: u32) -> u32 {\n  if (c == 1u) { return 2u; } // front -> back\n  if (c == 2u) { return 1u; } // back  -> front\n  return c;                   // none\n}\n\n@compute @workgroup_size(64)\nfn evaluate(@builtin(global_invocation_id) gid: vec3<u32>) {\n  let i = gid.x;\n  if (i >= uIn.numROs) { return; }\n  let ref = roInputRefs[i];\n  if (ref == 0xFFFFFFFFu) {\n    // No rule on this RO; leave existing output untouched. Allows a\n    // single kernel dispatch to skip non-participating ROs.\n    return;\n  }\n  let m = loadUpper3x3(ref);\n  let d = det3x3(m);\n  let declared = uIn.declared;\n  let outVal = select(declared, flipCull(declared), d < 0.0);\n  roOutputs[i] = outVal;\n}\n";
+export declare const GPU_FLIP_CULL_BY_DET_WGSL = "\n// Per-RO record. Index i corresponds to drawId i in the scene's\n// flat RO table.\nstruct GpuRuleParams {\n  numROs:     u32,\n  declared:   u32,   // 0 = none, 1 = front, 2 = back  (must match CULL_MODE[] order in bitfield.ts)\n  _pad0:      u32,\n  _pad1:      u32,\n};\n\n@group(0) @binding(0) var<storage, read>       arena:        array<u32>;\n// One per-RO entry: byte offset within the arena of the ROs ModelTrafo\n// allocation header. Data is at offset + 16 (ALLOC_HEADER_PAD_TO).\n// 0xFFFFFFFFu means \"this RO does NOT have a flip-cull-by-det rule\".\n@group(0) @binding(1) var<storage, read>       roInputRefs:  array<u32>;\n@group(0) @binding(2) var<storage, read_write> roOutputs:    array<u32>;\n@group(0) @binding(3) var<uniform>             uIn:          GpuRuleParams;\n\n// Read a row-major mat4 from the arena at byte offset `refBytes + 16`\n// (header is 16 bytes wide due to ALLOC_HEADER_PAD_TO). Returns the\n// 3\u00D73 upper-left in row-major order: [m00,m01,m02, m10,m11,m12, m20,m21,m22].\nfn loadUpper3x3(refBytes: u32) -> array<f32, 9> {\n  let baseU32 = (refBytes + 16u) >> 2u;\n  // The arena is a Float32 storage of mat4 in row-major, 16 floats.\n  // Read 9 of them.\n  return array<f32, 9>(\n    bitcast<f32>(arena[baseU32 + 0u]),  bitcast<f32>(arena[baseU32 + 1u]),  bitcast<f32>(arena[baseU32 + 2u]),\n    bitcast<f32>(arena[baseU32 + 4u]),  bitcast<f32>(arena[baseU32 + 5u]),  bitcast<f32>(arena[baseU32 + 6u]),\n    bitcast<f32>(arena[baseU32 + 8u]),  bitcast<f32>(arena[baseU32 + 9u]),  bitcast<f32>(arena[baseU32 + 10u]),\n  );\n}\n\nfn det3x3(m: array<f32, 9>) -> f32 {\n  return m[0] * (m[4] * m[8] - m[5] * m[7])\n       - m[1] * (m[3] * m[8] - m[5] * m[6])\n       + m[2] * (m[3] * m[7] - m[4] * m[6]);\n}\n\n// Mirror of bitfield.ts CULL_MODE[] order: 0=none, 1=front, 2=back.\nfn flipCull(c: u32) -> u32 {\n  if (c == 1u) { return 2u; } // front -> back\n  if (c == 2u) { return 1u; } // back  -> front\n  return c;                   // none\n}\n\n@compute @workgroup_size(64)\nfn evaluate(@builtin(global_invocation_id) gid: vec3<u32>) {\n  let i = gid.x;\n  if (i >= uIn.numROs) { return; }\n  let refByte = roInputRefs[i];\n  if (refByte == 0xFFFFFFFFu) {\n    // No rule on this RO; leave existing output untouched. Allows a\n    // single kernel dispatch to skip non-participating ROs.\n    return;\n  }\n  let m = loadUpper3x3(refByte);\n  let d = det3x3(m);\n  let declared = uIn.declared;\n  let outVal = select(declared, flipCull(declared), d < 0.0);\n  roOutputs[i] = outVal;\n}\n";
 /** Map between bitfield.ts's CULL_MODE order and the kernel's u32 enum. */
 export declare const CULL_TO_U32: {
     readonly none: 0;

package/dist/runtime/derivedModes/gpuKernel.d.ts.map

@@ -1 +1 @@
-{"version":3,"file":"gpuKernel.d.ts","sourceRoot":"","sources":["../../../src/runtime/derivedModes/gpuKernel.ts"],"names":[],"mappings":"AAgCA,eAAO,MAAM,yBAAyB,s+EA6DrC,CAAC;AAEF,2EAA2E;AAC3E,eAAO,MAAM,WAAW;;;;CAAgD,CAAC;AACzE,eAAO,MAAM,WAAW,oCAAqC,CAAC"}
+{"version":3,"file":"gpuKernel.d.ts","sourceRoot":"","sources":["../../../src/runtime/derivedModes/gpuKernel.ts"],"names":[],"mappings":"AAgCA,eAAO,MAAM,yBAAyB,k/EA6DrC,CAAC;AAEF,2EAA2E;AAC3E,eAAO,MAAM,WAAW;;;;CAAgD,CAAC;AACzE,eAAO,MAAM,WAAW,oCAAqC,CAAC"}

package/dist/runtime/derivedModes/gpuKernel.js

@@ -78,13 +78,13 @@ fn flipCull(c: u32) -> u32 {
 fn evaluate(@builtin(global_invocation_id) gid: vec3<u32>) {
   let i = gid.x;
   if (i >= uIn.numROs) { return; }
-  let ref = roInputRefs[i];
-  if (ref == 0xFFFFFFFFu) {
+  let refByte = roInputRefs[i];
+  if (refByte == 0xFFFFFFFFu) {
     // No rule on this RO; leave existing output untouched. Allows a
     // single kernel dispatch to skip non-participating ROs.
     return;
   }
-  let m = loadUpper3x3(ref);
+  let m = loadUpper3x3(refByte);
   let d = det3x3(m);
   let declared = uIn.declared;
   let outVal = select(declared, flipCull(declared), d < 0.0);

package/package.json

@@ -1,6 +1,6 @@
 {
   "name": "@aardworx/wombat.rendering",
-  "version": "0.9.19",
+  "version": "0.9.20",
   "description": "WebGPU rendering layer for the Wombat TypeScript stack — RenderObject/RenderTask/runtime + window glue, port of Aardvark.Rendering's lower layers on top of WebGPU and wombat.shader.",
   "license": "MIT",
   "author": "krauthaufen",

package/src/runtime/derivedModes/gpuKernel.ts

@@ -79,13 +79,13 @@ fn flipCull(c: u32) -> u32 {
 fn evaluate(@builtin(global_invocation_id) gid: vec3<u32>) {
   let i = gid.x;
   if (i >= uIn.numROs) { return; }
-  let ref = roInputRefs[i];
-  if (ref == 0xFFFFFFFFu) {
+  let refByte = roInputRefs[i];
+  if (refByte == 0xFFFFFFFFu) {
     // No rule on this RO; leave existing output untouched. Allows a
     // single kernel dispatch to skip non-participating ROs.
     return;
   }
-  let m = loadUpper3x3(ref);
+  let m = loadUpper3x3(refByte);
   let d = det3x3(m);
   let declared = uIn.declared;
   let outVal = select(declared, flipCull(declared), d < 0.0);