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- checksums.yaml +4 -4
- data/Cargo.lock +116 -120
- data/ext/Cargo.toml +6 -6
- data/ext/cargo-vendor/anyhow-1.0.83/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/anyhow-1.0.83/Cargo.toml +130 -0
- data/ext/cargo-vendor/anyhow-1.0.83/README.md +181 -0
- data/ext/cargo-vendor/anyhow-1.0.83/build.rs +179 -0
- data/ext/cargo-vendor/anyhow-1.0.83/src/backtrace.rs +406 -0
- data/ext/cargo-vendor/anyhow-1.0.83/src/chain.rs +102 -0
- data/ext/cargo-vendor/anyhow-1.0.83/src/fmt.rs +158 -0
- data/ext/cargo-vendor/anyhow-1.0.83/src/kind.rs +121 -0
- data/ext/cargo-vendor/anyhow-1.0.83/src/lib.rs +702 -0
- data/ext/cargo-vendor/anyhow-1.0.83/src/macros.rs +241 -0
- data/ext/cargo-vendor/anyhow-1.0.83/src/wrapper.rs +84 -0
- data/ext/cargo-vendor/anyhow-1.0.83/tests/test_ensure.rs +724 -0
- data/ext/cargo-vendor/anyhow-1.0.83/tests/test_macros.rs +81 -0
- data/ext/cargo-vendor/anyhow-1.0.83/tests/test_repr.rs +30 -0
- data/ext/cargo-vendor/anyhow-1.0.83/tests/ui/no-impl.stderr +32 -0
- data/ext/cargo-vendor/cranelift-bforest-0.107.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-bforest-0.107.2/Cargo.toml +40 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/Cargo.toml +178 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/build.rs +396 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/alias_analysis.rs +403 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/binemit/mod.rs +171 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/bitset.rs +187 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/context.rs +386 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/egraph/elaborate.rs +835 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/egraph.rs +838 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/inst_predicates.rs +236 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/ir/constant.rs +462 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/ir/dfg.rs +1777 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/ir/entities.rs +562 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/ir/function.rs +490 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/ir/instructions.rs +1019 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/ir/memflags.rs +452 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/ir/mod.rs +108 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/ir/trapcode.rs +149 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/ir/types.rs +629 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/aarch64/abi.rs +1707 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/aarch64/inst/emit.rs +3932 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/aarch64/inst/mod.rs +3083 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/aarch64/inst.isle +4218 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/aarch64/lower/isle.rs +884 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/aarch64/lower.isle +2933 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/aarch64/mod.rs +242 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/aarch64/pcc.rs +565 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/call_conv.rs +127 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/riscv64/abi.rs +1109 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/riscv64/inst/args.rs +1968 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/riscv64/inst/emit.rs +3466 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/riscv64/inst/encode.rs +654 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/riscv64/inst.isle +2944 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/riscv64/lower/isle.rs +625 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/riscv64/lower.isle +2872 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/s390x/abi.rs +1047 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/s390x/inst/args.rs +347 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/s390x/inst/emit.rs +3646 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/s390x/inst.isle +5033 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/s390x/lower.isle +3995 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/x64/abi.rs +1369 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/x64/encoding/evex.rs +748 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/x64/encoding/rex.rs +596 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/x64/encoding/vex.rs +491 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/x64/inst/args.rs +2289 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/x64/inst/emit.rs +4383 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/x64/inst/emit_state.rs +74 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/x64/inst/mod.rs +2798 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/x64/inst.isle +5304 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/x64/lower/isle.rs +1066 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/x64/lower.isle +4809 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/x64/lower.rs +339 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/x64/mod.rs +234 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/isa/x64/pcc.rs +1003 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/legalizer/mod.rs +348 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/machinst/abi.rs +2594 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/machinst/buffer.rs +2512 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/machinst/inst_common.rs +75 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/machinst/isle.rs +914 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/machinst/lower.rs +1452 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/machinst/mod.rs +555 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/machinst/pcc.rs +169 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/machinst/vcode.rs +1807 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/nan_canonicalization.rs +110 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/opts/cprop.isle +281 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/opts/spectre.isle +14 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/opts.rs +295 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/prelude.isle +646 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/result.rs +111 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/settings.rs +591 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/verifier/mod.rs +1957 -0
- data/ext/cargo-vendor/cranelift-codegen-0.107.2/src/write.rs +631 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.107.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.107.2/Cargo.toml +35 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.107.2/src/shared/entities.rs +101 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.107.2/src/shared/formats.rs +205 -0
- data/ext/cargo-vendor/cranelift-codegen-meta-0.107.2/src/shared/instructions.rs +3791 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.107.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-codegen-shared-0.107.2/Cargo.toml +22 -0
- data/ext/cargo-vendor/cranelift-control-0.107.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-control-0.107.2/Cargo.toml +30 -0
- data/ext/cargo-vendor/cranelift-entity-0.107.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-entity-0.107.2/Cargo.toml +50 -0
- data/ext/cargo-vendor/cranelift-frontend-0.107.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-frontend-0.107.2/Cargo.toml +69 -0
- data/ext/cargo-vendor/cranelift-isle-0.107.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-isle-0.107.2/Cargo.toml +46 -0
- data/ext/cargo-vendor/cranelift-native-0.107.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-native-0.107.2/Cargo.toml +45 -0
- data/ext/cargo-vendor/cranelift-wasm-0.107.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/cranelift-wasm-0.107.2/Cargo.toml +107 -0
- data/ext/cargo-vendor/cranelift-wasm-0.107.2/src/code_translator.rs +3683 -0
- data/ext/cargo-vendor/cranelift-wasm-0.107.2/src/environ/dummy.rs +912 -0
- data/ext/cargo-vendor/cranelift-wasm-0.107.2/src/environ/mod.rs +8 -0
- data/ext/cargo-vendor/cranelift-wasm-0.107.2/src/environ/spec.rs +945 -0
- data/ext/cargo-vendor/cranelift-wasm-0.107.2/src/func_translator.rs +296 -0
- data/ext/cargo-vendor/cranelift-wasm-0.107.2/src/lib.rs +58 -0
- data/ext/cargo-vendor/cranelift-wasm-0.107.2/src/state.rs +522 -0
- data/ext/cargo-vendor/cranelift-wasm-0.107.2/src/table.rs +104 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.21/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/deterministic-wasi-ctx-0.1.21/Cargo.toml +48 -0
- data/ext/cargo-vendor/mach2-0.4.2/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/mach2-0.4.2/Cargo.toml +49 -0
- data/ext/cargo-vendor/mach2-0.4.2/LICENSE-APACHE +176 -0
- data/ext/cargo-vendor/mach2-0.4.2/LICENSE-BSD +23 -0
- data/ext/cargo-vendor/mach2-0.4.2/LICENSE-MIT +25 -0
- data/ext/cargo-vendor/mach2-0.4.2/README.md +116 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/exc.rs +73 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/kern_return.rs +59 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/lib.rs +59 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/mach_port.rs +50 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/message.rs +345 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/ndr.rs +19 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/port.rs +67 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/semaphore.rs +22 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/structs.rs +66 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/sync_policy.rs +9 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/task.rs +46 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/task_info.rs +49 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/thread_act.rs +36 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/thread_policy.rs +121 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/thread_status.rs +53 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/traps.rs +37 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/vm.rs +248 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/vm_attributes.rs +18 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/vm_page_size.rs +40 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/vm_prot.rs +13 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/vm_purgable.rs +42 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/vm_region.rs +238 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/vm_statistics.rs +58 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/vm_sync.rs +11 -0
- data/ext/cargo-vendor/mach2-0.4.2/src/vm_types.rs +19 -0
- data/ext/cargo-vendor/object-0.33.0/.cargo-checksum.json +1 -0
- data/ext/cargo-vendor/object-0.33.0/CHANGELOG.md +797 -0
- data/ext/cargo-vendor/object-0.33.0/Cargo.toml +179 -0
- data/ext/cargo-vendor/object-0.33.0/LICENSE-APACHE +201 -0
- data/ext/cargo-vendor/object-0.33.0/LICENSE-MIT +25 -0
- data/ext/cargo-vendor/object-0.33.0/README.md +56 -0
- data/ext/cargo-vendor/object-0.33.0/src/archive.rs +91 -0
- data/ext/cargo-vendor/object-0.33.0/src/build/bytes.rs +141 -0
- data/ext/cargo-vendor/object-0.33.0/src/build/elf.rs +3033 -0
- data/ext/cargo-vendor/object-0.33.0/src/build/error.rs +41 -0
- data/ext/cargo-vendor/object-0.33.0/src/build/mod.rs +18 -0
- data/ext/cargo-vendor/object-0.33.0/src/build/table.rs +128 -0
- data/ext/cargo-vendor/object-0.33.0/src/common.rs +568 -0
- data/ext/cargo-vendor/object-0.33.0/src/elf.rs +6291 -0
- data/ext/cargo-vendor/object-0.33.0/src/endian.rs +831 -0
- data/ext/cargo-vendor/object-0.33.0/src/lib.rs +107 -0
- data/ext/cargo-vendor/object-0.33.0/src/macho.rs +3309 -0
- data/ext/cargo-vendor/object-0.33.0/src/pe.rs +3056 -0
- data/ext/cargo-vendor/object-0.33.0/src/pod.rs +239 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/any.rs +1328 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/archive.rs +759 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/coff/comdat.rs +211 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/coff/file.rs +383 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/coff/import.rs +223 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/coff/mod.rs +66 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/coff/relocation.rs +108 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/coff/section.rs +585 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/coff/symbol.rs +635 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/elf/attributes.rs +306 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/elf/comdat.rs +162 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/elf/compression.rs +56 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/elf/dynamic.rs +117 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/elf/file.rs +918 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/elf/hash.rs +224 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/elf/mod.rs +78 -0
- data/ext/cargo-vendor/object-0.33.0/src/read/elf/note.rs +271 -0
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- data/ext/cargo-vendor/object-0.33.0/src/write/coff/object.rs +678 -0
- data/ext/cargo-vendor/object-0.33.0/src/write/coff/writer.rs +518 -0
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-
//!
|
3
|
-
//! This machine uses the "vanilla" ABI implementation from abi.rs,
|
4
|
-
//! however a few details are different from the description there:
|
5
|
-
//!
|
6
|
-
//! - On s390x, the caller must provide a "register save area" of 160
|
7
|
-
//! bytes to any function it calls. The called function is free to use
|
8
|
-
//! this space for any purpose; usually to save callee-saved GPRs.
|
9
|
-
//! (Note that while this area is allocated by the caller, it is counted
|
10
|
-
//! as part of the callee's stack frame; in particular, the callee's CFA
|
11
|
-
//! is the top of the register save area, not the incoming SP value.)
|
12
|
-
//!
|
13
|
-
//! - Overflow arguments are passed on the stack starting immediately
|
14
|
-
//! above the register save area. On s390x, this space is allocated
|
15
|
-
//! only once directly in the prologue, using a size large enough to
|
16
|
-
//! hold overflow arguments for every call in the function.
|
17
|
-
//!
|
18
|
-
//! - On s390x we do not use a frame pointer register; instead, every
|
19
|
-
//! element of the stack frame is addressed via (constant) offsets
|
20
|
-
//! from the stack pointer. Note that due to the above (and because
|
21
|
-
//! there are no variable-sized stack allocations in cranelift), the
|
22
|
-
//! value of the stack pointer register never changes after the
|
23
|
-
//! initial allocation in the function prologue.
|
24
|
-
//!
|
25
|
-
//! - If we are asked to "preserve frame pointers" to enable stack
|
26
|
-
//! unwinding, we use the stack backchain feature instead, which
|
27
|
-
//! is documented by the s390x ELF ABI, but marked as optional.
|
28
|
-
//! This ensures that at all times during execution of a function,
|
29
|
-
//! the lowest word on the stack (part of the register save area)
|
30
|
-
//! holds a copy of the stack pointer at function entry.
|
31
|
-
//!
|
32
|
-
//! Overall, the stack frame layout on s390x is as follows:
|
33
|
-
//!
|
34
|
-
//! ```plain
|
35
|
-
//! (high address)
|
36
|
-
//!
|
37
|
-
//! +---------------------------+
|
38
|
-
//! | ... |
|
39
|
-
//! CFA -----> | stack args |
|
40
|
-
//! +---------------------------+
|
41
|
-
//! | ... |
|
42
|
-
//! | 160 bytes reg save area |
|
43
|
-
//! | (used to save GPRs) |
|
44
|
-
//! SP at function entry -----> | (incl. caller's backchain)|
|
45
|
-
//! +---------------------------+
|
46
|
-
//! | ... |
|
47
|
-
//! | clobbered callee-saves |
|
48
|
-
//! | (used to save FPRs) |
|
49
|
-
//! unwind-frame base ----> | (alloc'd by prologue) |
|
50
|
-
//! +---------------------------+
|
51
|
-
//! | ... |
|
52
|
-
//! | spill slots |
|
53
|
-
//! | (accessed via nominal SP) |
|
54
|
-
//! | ... |
|
55
|
-
//! | stack slots |
|
56
|
-
//! | (accessed via nominal SP) |
|
57
|
-
//! nominal SP ---------------> | (alloc'd by prologue) |
|
58
|
-
//! +---------------------------+
|
59
|
-
//! | ... |
|
60
|
-
//! | args for call |
|
61
|
-
//! | outgoing reg save area |
|
62
|
-
//! | (alloc'd by prologue) |
|
63
|
-
//! SP during function ------> | (incl. callee's backchain)|
|
64
|
-
//! +---------------------------+
|
65
|
-
//!
|
66
|
-
//! (low address)
|
67
|
-
//! ```
|
68
|
-
|
69
|
-
use crate::ir;
|
70
|
-
use crate::ir::condcodes::IntCC;
|
71
|
-
use crate::ir::types;
|
72
|
-
use crate::ir::MemFlags;
|
73
|
-
use crate::ir::Signature;
|
74
|
-
use crate::ir::Type;
|
75
|
-
use crate::isa;
|
76
|
-
use crate::isa::s390x::{inst::*, settings as s390x_settings};
|
77
|
-
use crate::isa::unwind::UnwindInst;
|
78
|
-
use crate::machinst::*;
|
79
|
-
use crate::settings;
|
80
|
-
use crate::{CodegenError, CodegenResult};
|
81
|
-
use alloc::vec::Vec;
|
82
|
-
use regalloc2::{MachineEnv, PReg, PRegSet};
|
83
|
-
use smallvec::{smallvec, SmallVec};
|
84
|
-
use std::sync::OnceLock;
|
85
|
-
|
86
|
-
// We use a generic implementation that factors out ABI commonalities.
|
87
|
-
|
88
|
-
/// Support for the S390x ABI from the callee side (within a function body).
|
89
|
-
pub type S390xCallee = Callee<S390xMachineDeps>;
|
90
|
-
|
91
|
-
/// ABI Register usage
|
92
|
-
|
93
|
-
fn in_int_reg(ty: Type) -> bool {
|
94
|
-
match ty {
|
95
|
-
types::I8 | types::I16 | types::I32 | types::I64 | types::R64 => true,
|
96
|
-
_ => false,
|
97
|
-
}
|
98
|
-
}
|
99
|
-
|
100
|
-
fn in_flt_reg(ty: Type) -> bool {
|
101
|
-
match ty {
|
102
|
-
types::F32 | types::F64 => true,
|
103
|
-
_ => false,
|
104
|
-
}
|
105
|
-
}
|
106
|
-
|
107
|
-
fn in_vec_reg(ty: Type) -> bool {
|
108
|
-
ty.is_vector() && ty.bits() == 128
|
109
|
-
}
|
110
|
-
|
111
|
-
fn get_intreg_for_arg(idx: usize) -> Option<Reg> {
|
112
|
-
match idx {
|
113
|
-
0 => Some(regs::gpr(2)),
|
114
|
-
1 => Some(regs::gpr(3)),
|
115
|
-
2 => Some(regs::gpr(4)),
|
116
|
-
3 => Some(regs::gpr(5)),
|
117
|
-
4 => Some(regs::gpr(6)),
|
118
|
-
_ => None,
|
119
|
-
}
|
120
|
-
}
|
121
|
-
|
122
|
-
fn get_fltreg_for_arg(idx: usize) -> Option<Reg> {
|
123
|
-
match idx {
|
124
|
-
0 => Some(regs::vr(0)),
|
125
|
-
1 => Some(regs::vr(2)),
|
126
|
-
2 => Some(regs::vr(4)),
|
127
|
-
3 => Some(regs::vr(6)),
|
128
|
-
_ => None,
|
129
|
-
}
|
130
|
-
}
|
131
|
-
|
132
|
-
fn get_vecreg_for_arg(idx: usize) -> Option<Reg> {
|
133
|
-
match idx {
|
134
|
-
0 => Some(regs::vr(24)),
|
135
|
-
1 => Some(regs::vr(25)),
|
136
|
-
2 => Some(regs::vr(26)),
|
137
|
-
3 => Some(regs::vr(27)),
|
138
|
-
4 => Some(regs::vr(28)),
|
139
|
-
5 => Some(regs::vr(29)),
|
140
|
-
6 => Some(regs::vr(30)),
|
141
|
-
7 => Some(regs::vr(31)),
|
142
|
-
_ => None,
|
143
|
-
}
|
144
|
-
}
|
145
|
-
|
146
|
-
fn get_intreg_for_ret(idx: usize) -> Option<Reg> {
|
147
|
-
match idx {
|
148
|
-
0 => Some(regs::gpr(2)),
|
149
|
-
// ABI extension to support multi-value returns:
|
150
|
-
1 => Some(regs::gpr(3)),
|
151
|
-
2 => Some(regs::gpr(4)),
|
152
|
-
3 => Some(regs::gpr(5)),
|
153
|
-
_ => None,
|
154
|
-
}
|
155
|
-
}
|
156
|
-
|
157
|
-
fn get_fltreg_for_ret(idx: usize) -> Option<Reg> {
|
158
|
-
match idx {
|
159
|
-
0 => Some(regs::vr(0)),
|
160
|
-
// ABI extension to support multi-value returns:
|
161
|
-
1 => Some(regs::vr(2)),
|
162
|
-
2 => Some(regs::vr(4)),
|
163
|
-
3 => Some(regs::vr(6)),
|
164
|
-
_ => None,
|
165
|
-
}
|
166
|
-
}
|
167
|
-
|
168
|
-
fn get_vecreg_for_ret(idx: usize) -> Option<Reg> {
|
169
|
-
match idx {
|
170
|
-
0 => Some(regs::vr(24)),
|
171
|
-
// ABI extension to support multi-value returns:
|
172
|
-
1 => Some(regs::vr(25)),
|
173
|
-
2 => Some(regs::vr(26)),
|
174
|
-
3 => Some(regs::vr(27)),
|
175
|
-
4 => Some(regs::vr(28)),
|
176
|
-
5 => Some(regs::vr(29)),
|
177
|
-
6 => Some(regs::vr(30)),
|
178
|
-
7 => Some(regs::vr(31)),
|
179
|
-
_ => None,
|
180
|
-
}
|
181
|
-
}
|
182
|
-
|
183
|
-
/// This is the limit for the size of argument and return-value areas on the
|
184
|
-
/// stack. We place a reasonable limit here to avoid integer overflow issues
|
185
|
-
/// with 32-bit arithmetic: for now, 128 MB.
|
186
|
-
static STACK_ARG_RET_SIZE_LIMIT: u32 = 128 * 1024 * 1024;
|
187
|
-
|
188
|
-
/// The size of the register save area
|
189
|
-
pub static REG_SAVE_AREA_SIZE: u32 = 160;
|
190
|
-
|
191
|
-
impl Into<MemArg> for StackAMode {
|
192
|
-
fn into(self) -> MemArg {
|
193
|
-
match self {
|
194
|
-
StackAMode::FPOffset(off, _ty) => MemArg::InitialSPOffset { off },
|
195
|
-
StackAMode::NominalSPOffset(off, _ty) => MemArg::NominalSPOffset { off },
|
196
|
-
StackAMode::SPOffset(off, _ty) => {
|
197
|
-
MemArg::reg_plus_off(stack_reg(), off, MemFlags::trusted())
|
198
|
-
}
|
199
|
-
}
|
200
|
-
}
|
201
|
-
}
|
202
|
-
|
203
|
-
/// S390x-specific ABI behavior. This struct just serves as an implementation
|
204
|
-
/// point for the trait; it is never actually instantiated.
|
205
|
-
pub struct S390xMachineDeps;
|
206
|
-
|
207
|
-
impl IsaFlags for s390x_settings::Flags {}
|
208
|
-
|
209
|
-
impl ABIMachineSpec for S390xMachineDeps {
|
210
|
-
type I = Inst;
|
211
|
-
|
212
|
-
type F = s390x_settings::Flags;
|
213
|
-
|
214
|
-
fn word_bits() -> u32 {
|
215
|
-
64
|
216
|
-
}
|
217
|
-
|
218
|
-
/// Return required stack alignment in bytes.
|
219
|
-
fn stack_align(_call_conv: isa::CallConv) -> u32 {
|
220
|
-
8
|
221
|
-
}
|
222
|
-
|
223
|
-
fn compute_arg_locs<'a, I>(
|
224
|
-
call_conv: isa::CallConv,
|
225
|
-
_flags: &settings::Flags,
|
226
|
-
params: I,
|
227
|
-
args_or_rets: ArgsOrRets,
|
228
|
-
add_ret_area_ptr: bool,
|
229
|
-
mut args: ArgsAccumulator<'_>,
|
230
|
-
) -> CodegenResult<(u32, Option<usize>)>
|
231
|
-
where
|
232
|
-
I: IntoIterator<Item = &'a ir::AbiParam>,
|
233
|
-
{
|
234
|
-
assert_ne!(
|
235
|
-
call_conv,
|
236
|
-
isa::CallConv::Tail,
|
237
|
-
"s390x does not support the 'tail' calling convention yet"
|
238
|
-
);
|
239
|
-
|
240
|
-
let mut next_gpr = 0;
|
241
|
-
let mut next_fpr = 0;
|
242
|
-
let mut next_vr = 0;
|
243
|
-
let mut next_stack: u32 = 0;
|
244
|
-
|
245
|
-
if args_or_rets == ArgsOrRets::Args {
|
246
|
-
next_stack = REG_SAVE_AREA_SIZE;
|
247
|
-
}
|
248
|
-
|
249
|
-
// In the SystemV ABI, the return area pointer is the first argument,
|
250
|
-
// so we need to leave room for it if required.
|
251
|
-
if add_ret_area_ptr {
|
252
|
-
next_gpr += 1;
|
253
|
-
}
|
254
|
-
|
255
|
-
for mut param in params.into_iter().copied() {
|
256
|
-
let intreg = in_int_reg(param.value_type);
|
257
|
-
let fltreg = in_flt_reg(param.value_type);
|
258
|
-
let vecreg = in_vec_reg(param.value_type);
|
259
|
-
debug_assert!(intreg as i32 + fltreg as i32 + vecreg as i32 <= 1);
|
260
|
-
|
261
|
-
let (next_reg, candidate, implicit_ref) = if intreg {
|
262
|
-
let candidate = match args_or_rets {
|
263
|
-
ArgsOrRets::Args => get_intreg_for_arg(next_gpr),
|
264
|
-
ArgsOrRets::Rets => get_intreg_for_ret(next_gpr),
|
265
|
-
};
|
266
|
-
(&mut next_gpr, candidate, None)
|
267
|
-
} else if fltreg {
|
268
|
-
let candidate = match args_or_rets {
|
269
|
-
ArgsOrRets::Args => get_fltreg_for_arg(next_fpr),
|
270
|
-
ArgsOrRets::Rets => get_fltreg_for_ret(next_fpr),
|
271
|
-
};
|
272
|
-
(&mut next_fpr, candidate, None)
|
273
|
-
} else if vecreg {
|
274
|
-
let candidate = match args_or_rets {
|
275
|
-
ArgsOrRets::Args => get_vecreg_for_arg(next_vr),
|
276
|
-
ArgsOrRets::Rets => get_vecreg_for_ret(next_vr),
|
277
|
-
};
|
278
|
-
(&mut next_vr, candidate, None)
|
279
|
-
} else {
|
280
|
-
// We must pass this by implicit reference.
|
281
|
-
if args_or_rets == ArgsOrRets::Rets {
|
282
|
-
// For return values, just force them to memory.
|
283
|
-
(&mut next_gpr, None, None)
|
284
|
-
} else {
|
285
|
-
// For arguments, implicitly convert to pointer type.
|
286
|
-
let implicit_ref = Some(param.value_type);
|
287
|
-
param = ir::AbiParam::new(types::I64);
|
288
|
-
let candidate = get_intreg_for_arg(next_gpr);
|
289
|
-
(&mut next_gpr, candidate, implicit_ref)
|
290
|
-
}
|
291
|
-
};
|
292
|
-
|
293
|
-
let slot = if let Some(reg) = candidate {
|
294
|
-
*next_reg += 1;
|
295
|
-
ABIArgSlot::Reg {
|
296
|
-
reg: reg.to_real_reg().unwrap(),
|
297
|
-
ty: param.value_type,
|
298
|
-
extension: param.extension,
|
299
|
-
}
|
300
|
-
} else {
|
301
|
-
// Compute size. Every argument or return value takes a slot of
|
302
|
-
// at least 8 bytes.
|
303
|
-
let size = (ty_bits(param.value_type) / 8) as u32;
|
304
|
-
let slot_size = std::cmp::max(size, 8);
|
305
|
-
|
306
|
-
// Align the stack slot.
|
307
|
-
debug_assert!(slot_size.is_power_of_two());
|
308
|
-
let slot_align = std::cmp::min(slot_size, 8);
|
309
|
-
next_stack = align_to(next_stack, slot_align);
|
310
|
-
|
311
|
-
// If the type is actually of smaller size (and the argument
|
312
|
-
// was not extended), it is passed right-aligned.
|
313
|
-
let offset = if size < slot_size && param.extension == ir::ArgumentExtension::None {
|
314
|
-
slot_size - size
|
315
|
-
} else {
|
316
|
-
0
|
317
|
-
};
|
318
|
-
let offset = (next_stack + offset) as i64;
|
319
|
-
next_stack += slot_size;
|
320
|
-
ABIArgSlot::Stack {
|
321
|
-
offset,
|
322
|
-
ty: param.value_type,
|
323
|
-
extension: param.extension,
|
324
|
-
}
|
325
|
-
};
|
326
|
-
|
327
|
-
if let ir::ArgumentPurpose::StructArgument(size) = param.purpose {
|
328
|
-
assert!(size % 8 == 0, "StructArgument size is not properly aligned");
|
329
|
-
args.push(ABIArg::StructArg {
|
330
|
-
pointer: Some(slot),
|
331
|
-
offset: 0,
|
332
|
-
size: size as u64,
|
333
|
-
purpose: param.purpose,
|
334
|
-
});
|
335
|
-
} else if let Some(ty) = implicit_ref {
|
336
|
-
assert!(
|
337
|
-
(ty_bits(ty) / 8) % 8 == 0,
|
338
|
-
"implicit argument size is not properly aligned"
|
339
|
-
);
|
340
|
-
args.push(ABIArg::ImplicitPtrArg {
|
341
|
-
pointer: slot,
|
342
|
-
offset: 0,
|
343
|
-
ty,
|
344
|
-
purpose: param.purpose,
|
345
|
-
});
|
346
|
-
} else {
|
347
|
-
args.push(ABIArg::Slots {
|
348
|
-
slots: smallvec![slot],
|
349
|
-
purpose: param.purpose,
|
350
|
-
});
|
351
|
-
}
|
352
|
-
}
|
353
|
-
|
354
|
-
next_stack = align_to(next_stack, 8);
|
355
|
-
|
356
|
-
let extra_arg = if add_ret_area_ptr {
|
357
|
-
debug_assert!(args_or_rets == ArgsOrRets::Args);
|
358
|
-
// The return pointer is passed as first argument.
|
359
|
-
if let Some(reg) = get_intreg_for_arg(0) {
|
360
|
-
args.push(ABIArg::reg(
|
361
|
-
reg.to_real_reg().unwrap(),
|
362
|
-
types::I64,
|
363
|
-
ir::ArgumentExtension::None,
|
364
|
-
ir::ArgumentPurpose::Normal,
|
365
|
-
));
|
366
|
-
} else {
|
367
|
-
args.push(ABIArg::stack(
|
368
|
-
next_stack as i64,
|
369
|
-
types::I64,
|
370
|
-
ir::ArgumentExtension::None,
|
371
|
-
ir::ArgumentPurpose::Normal,
|
372
|
-
));
|
373
|
-
next_stack += 8;
|
374
|
-
}
|
375
|
-
Some(args.args().len() - 1)
|
376
|
-
} else {
|
377
|
-
None
|
378
|
-
};
|
379
|
-
|
380
|
-
// After all arguments are in their well-defined location,
|
381
|
-
// allocate buffers for all StructArg or ImplicitPtrArg arguments.
|
382
|
-
for arg in args.args_mut() {
|
383
|
-
match arg {
|
384
|
-
ABIArg::StructArg { offset, size, .. } => {
|
385
|
-
*offset = next_stack as i64;
|
386
|
-
next_stack += *size as u32;
|
387
|
-
}
|
388
|
-
ABIArg::ImplicitPtrArg { offset, ty, .. } => {
|
389
|
-
*offset = next_stack as i64;
|
390
|
-
next_stack += (ty_bits(*ty) / 8) as u32;
|
391
|
-
}
|
392
|
-
_ => {}
|
393
|
-
}
|
394
|
-
}
|
395
|
-
|
396
|
-
// To avoid overflow issues, limit the arg/return size to something
|
397
|
-
// reasonable -- here, 128 MB.
|
398
|
-
if next_stack > STACK_ARG_RET_SIZE_LIMIT {
|
399
|
-
return Err(CodegenError::ImplLimitExceeded);
|
400
|
-
}
|
401
|
-
|
402
|
-
Ok((next_stack, extra_arg))
|
403
|
-
}
|
404
|
-
|
405
|
-
fn fp_to_arg_offset(_call_conv: isa::CallConv, _flags: &settings::Flags) -> i64 {
|
406
|
-
0
|
407
|
-
}
|
408
|
-
|
409
|
-
fn gen_load_stack(mem: StackAMode, into_reg: Writable<Reg>, ty: Type) -> Inst {
|
410
|
-
Inst::gen_load(into_reg, mem.into(), ty)
|
411
|
-
}
|
412
|
-
|
413
|
-
fn gen_store_stack(mem: StackAMode, from_reg: Reg, ty: Type) -> Inst {
|
414
|
-
Inst::gen_store(mem.into(), from_reg, ty)
|
415
|
-
}
|
416
|
-
|
417
|
-
fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Inst {
|
418
|
-
Inst::gen_move(to_reg, from_reg, ty)
|
419
|
-
}
|
420
|
-
|
421
|
-
fn gen_extend(
|
422
|
-
to_reg: Writable<Reg>,
|
423
|
-
from_reg: Reg,
|
424
|
-
signed: bool,
|
425
|
-
from_bits: u8,
|
426
|
-
to_bits: u8,
|
427
|
-
) -> Inst {
|
428
|
-
assert!(from_bits < to_bits);
|
429
|
-
Inst::Extend {
|
430
|
-
rd: to_reg,
|
431
|
-
rn: from_reg,
|
432
|
-
signed,
|
433
|
-
from_bits,
|
434
|
-
to_bits,
|
435
|
-
}
|
436
|
-
}
|
437
|
-
|
438
|
-
fn gen_args(args: Vec<ArgPair>) -> Inst {
|
439
|
-
Inst::Args { args }
|
440
|
-
}
|
441
|
-
|
442
|
-
fn gen_rets(rets: Vec<RetPair>) -> Inst {
|
443
|
-
Inst::Rets { rets }
|
444
|
-
}
|
445
|
-
|
446
|
-
fn gen_add_imm(
|
447
|
-
_call_conv: isa::CallConv,
|
448
|
-
into_reg: Writable<Reg>,
|
449
|
-
from_reg: Reg,
|
450
|
-
imm: u32,
|
451
|
-
) -> SmallInstVec<Inst> {
|
452
|
-
let mut insts = SmallVec::new();
|
453
|
-
if let Some(imm) = UImm12::maybe_from_u64(imm as u64) {
|
454
|
-
insts.push(Inst::LoadAddr {
|
455
|
-
rd: into_reg,
|
456
|
-
mem: MemArg::BXD12 {
|
457
|
-
base: from_reg,
|
458
|
-
index: zero_reg(),
|
459
|
-
disp: imm,
|
460
|
-
flags: MemFlags::trusted(),
|
461
|
-
},
|
462
|
-
});
|
463
|
-
} else if let Some(imm) = SImm20::maybe_from_i64(imm as i64) {
|
464
|
-
insts.push(Inst::LoadAddr {
|
465
|
-
rd: into_reg,
|
466
|
-
mem: MemArg::BXD20 {
|
467
|
-
base: from_reg,
|
468
|
-
index: zero_reg(),
|
469
|
-
disp: imm,
|
470
|
-
flags: MemFlags::trusted(),
|
471
|
-
},
|
472
|
-
});
|
473
|
-
} else {
|
474
|
-
if from_reg != into_reg.to_reg() {
|
475
|
-
insts.push(Inst::mov64(into_reg, from_reg));
|
476
|
-
}
|
477
|
-
insts.push(Inst::AluRUImm32 {
|
478
|
-
alu_op: ALUOp::AddLogical64,
|
479
|
-
rd: into_reg,
|
480
|
-
ri: into_reg.to_reg(),
|
481
|
-
imm,
|
482
|
-
});
|
483
|
-
}
|
484
|
-
insts
|
485
|
-
}
|
486
|
-
|
487
|
-
fn gen_stack_lower_bound_trap(limit_reg: Reg) -> SmallInstVec<Inst> {
|
488
|
-
let mut insts = SmallVec::new();
|
489
|
-
insts.push(Inst::CmpTrapRR {
|
490
|
-
op: CmpOp::CmpL64,
|
491
|
-
rn: stack_reg(),
|
492
|
-
rm: limit_reg,
|
493
|
-
cond: Cond::from_intcc(IntCC::UnsignedLessThanOrEqual),
|
494
|
-
trap_code: ir::TrapCode::StackOverflow,
|
495
|
-
});
|
496
|
-
insts
|
497
|
-
}
|
498
|
-
|
499
|
-
fn gen_get_stack_addr(mem: StackAMode, into_reg: Writable<Reg>, _ty: Type) -> Inst {
|
500
|
-
let mem = mem.into();
|
501
|
-
Inst::LoadAddr { rd: into_reg, mem }
|
502
|
-
}
|
503
|
-
|
504
|
-
fn get_stacklimit_reg(_call_conv: isa::CallConv) -> Reg {
|
505
|
-
spilltmp_reg()
|
506
|
-
}
|
507
|
-
|
508
|
-
fn gen_load_base_offset(into_reg: Writable<Reg>, base: Reg, offset: i32, ty: Type) -> Inst {
|
509
|
-
let mem = MemArg::reg_plus_off(base, offset.into(), MemFlags::trusted());
|
510
|
-
Inst::gen_load(into_reg, mem, ty)
|
511
|
-
}
|
512
|
-
|
513
|
-
fn gen_store_base_offset(base: Reg, offset: i32, from_reg: Reg, ty: Type) -> Inst {
|
514
|
-
let mem = MemArg::reg_plus_off(base, offset.into(), MemFlags::trusted());
|
515
|
-
Inst::gen_store(mem, from_reg, ty)
|
516
|
-
}
|
517
|
-
|
518
|
-
fn gen_sp_reg_adjust(imm: i32) -> SmallInstVec<Inst> {
|
519
|
-
if imm == 0 {
|
520
|
-
return SmallVec::new();
|
521
|
-
}
|
522
|
-
|
523
|
-
let mut insts = SmallVec::new();
|
524
|
-
if let Ok(imm) = i16::try_from(imm) {
|
525
|
-
insts.push(Inst::AluRSImm16 {
|
526
|
-
alu_op: ALUOp::Add64,
|
527
|
-
rd: writable_stack_reg(),
|
528
|
-
ri: stack_reg(),
|
529
|
-
imm,
|
530
|
-
});
|
531
|
-
} else {
|
532
|
-
insts.push(Inst::AluRSImm32 {
|
533
|
-
alu_op: ALUOp::Add64,
|
534
|
-
rd: writable_stack_reg(),
|
535
|
-
ri: stack_reg(),
|
536
|
-
imm,
|
537
|
-
});
|
538
|
-
}
|
539
|
-
insts
|
540
|
-
}
|
541
|
-
|
542
|
-
fn gen_nominal_sp_adj(offset: i32) -> Inst {
|
543
|
-
Inst::VirtualSPOffsetAdj {
|
544
|
-
offset: offset.into(),
|
545
|
-
}
|
546
|
-
}
|
547
|
-
|
548
|
-
fn gen_prologue_frame_setup(
|
549
|
-
_call_conv: isa::CallConv,
|
550
|
-
_flags: &settings::Flags,
|
551
|
-
_isa_flags: &s390x_settings::Flags,
|
552
|
-
_frame_layout: &FrameLayout,
|
553
|
-
) -> SmallInstVec<Inst> {
|
554
|
-
SmallVec::new()
|
555
|
-
}
|
556
|
-
|
557
|
-
fn gen_epilogue_frame_restore(
|
558
|
-
call_conv: isa::CallConv,
|
559
|
-
_flags: &settings::Flags,
|
560
|
-
_isa_flags: &s390x_settings::Flags,
|
561
|
-
frame_layout: &FrameLayout,
|
562
|
-
) -> SmallInstVec<Inst> {
|
563
|
-
let mut insts = SmallVec::new();
|
564
|
-
if call_conv == isa::CallConv::Tail && frame_layout.stack_args_size > 0 {
|
565
|
-
insts.extend(Self::gen_sp_reg_adjust(
|
566
|
-
frame_layout.stack_args_size.try_into().unwrap(),
|
567
|
-
));
|
568
|
-
}
|
569
|
-
insts.push(Inst::Ret { link: gpr(14) });
|
570
|
-
insts
|
571
|
-
}
|
572
|
-
|
573
|
-
fn gen_probestack(_insts: &mut SmallInstVec<Self::I>, _: u32) {
|
574
|
-
// TODO: implement if we ever require stack probes on an s390x host
|
575
|
-
// (unlikely unless Lucet is ported)
|
576
|
-
unimplemented!("Stack probing is unimplemented on S390x");
|
577
|
-
}
|
578
|
-
|
579
|
-
fn gen_inline_probestack(
|
580
|
-
_insts: &mut SmallInstVec<Self::I>,
|
581
|
-
_call_conv: isa::CallConv,
|
582
|
-
_frame_size: u32,
|
583
|
-
_guard_size: u32,
|
584
|
-
) {
|
585
|
-
unimplemented!("Inline stack probing is unimplemented on S390x");
|
586
|
-
}
|
587
|
-
|
588
|
-
fn gen_clobber_save(
|
589
|
-
_call_conv: isa::CallConv,
|
590
|
-
flags: &settings::Flags,
|
591
|
-
frame_layout: &FrameLayout,
|
592
|
-
) -> SmallVec<[Inst; 16]> {
|
593
|
-
let mut insts = SmallVec::new();
|
594
|
-
|
595
|
-
// Collect clobbered registers.
|
596
|
-
let (first_clobbered_gpr, clobbered_fpr) =
|
597
|
-
get_clobbered_gpr_fpr(&frame_layout.clobbered_callee_saves);
|
598
|
-
if flags.unwind_info() {
|
599
|
-
insts.push(Inst::Unwind {
|
600
|
-
inst: UnwindInst::DefineNewFrame {
|
601
|
-
offset_upward_to_caller_sp: REG_SAVE_AREA_SIZE,
|
602
|
-
offset_downward_to_clobbers: frame_layout.clobber_size,
|
603
|
-
},
|
604
|
-
});
|
605
|
-
}
|
606
|
-
|
607
|
-
// Use STMG to save clobbered GPRs into save area.
|
608
|
-
if first_clobbered_gpr < 16 {
|
609
|
-
let offset = 8 * first_clobbered_gpr as i64;
|
610
|
-
insts.push(Inst::StoreMultiple64 {
|
611
|
-
rt: gpr(first_clobbered_gpr),
|
612
|
-
rt2: gpr(15),
|
613
|
-
mem: MemArg::reg_plus_off(stack_reg(), offset, MemFlags::trusted()),
|
614
|
-
});
|
615
|
-
}
|
616
|
-
if flags.unwind_info() {
|
617
|
-
for i in first_clobbered_gpr..16 {
|
618
|
-
insts.push(Inst::Unwind {
|
619
|
-
inst: UnwindInst::SaveReg {
|
620
|
-
clobber_offset: frame_layout.clobber_size + (i * 8) as u32,
|
621
|
-
reg: gpr(i).to_real_reg().unwrap(),
|
622
|
-
},
|
623
|
-
});
|
624
|
-
}
|
625
|
-
}
|
626
|
-
|
627
|
-
// Save current stack pointer value if we need to write the backchain.
|
628
|
-
if flags.preserve_frame_pointers() {
|
629
|
-
insts.push(Inst::mov64(writable_gpr(1), stack_reg()));
|
630
|
-
}
|
631
|
-
|
632
|
-
// Decrement stack pointer.
|
633
|
-
let stack_size = frame_layout.outgoing_args_size as i32
|
634
|
-
+ frame_layout.clobber_size as i32
|
635
|
-
+ frame_layout.fixed_frame_storage_size as i32;
|
636
|
-
insts.extend(Self::gen_sp_reg_adjust(-stack_size));
|
637
|
-
if flags.unwind_info() {
|
638
|
-
insts.push(Inst::Unwind {
|
639
|
-
inst: UnwindInst::StackAlloc {
|
640
|
-
size: stack_size as u32,
|
641
|
-
},
|
642
|
-
});
|
643
|
-
}
|
644
|
-
|
645
|
-
let sp_adj = frame_layout.outgoing_args_size as i32;
|
646
|
-
if sp_adj > 0 {
|
647
|
-
insts.push(Self::gen_nominal_sp_adj(sp_adj));
|
648
|
-
}
|
649
|
-
|
650
|
-
// Write the stack backchain if requested, using the value saved above.
|
651
|
-
if flags.preserve_frame_pointers() {
|
652
|
-
insts.push(Inst::Store64 {
|
653
|
-
rd: gpr(1),
|
654
|
-
mem: MemArg::reg_plus_off(stack_reg(), 0, MemFlags::trusted()),
|
655
|
-
});
|
656
|
-
}
|
657
|
-
|
658
|
-
// Save FPRs.
|
659
|
-
for (i, reg) in clobbered_fpr.iter().enumerate() {
|
660
|
-
insts.push(Inst::VecStoreLane {
|
661
|
-
size: 64,
|
662
|
-
rd: reg.to_reg().into(),
|
663
|
-
mem: MemArg::reg_plus_off(
|
664
|
-
stack_reg(),
|
665
|
-
(i * 8) as i64
|
666
|
-
+ frame_layout.outgoing_args_size as i64
|
667
|
-
+ frame_layout.fixed_frame_storage_size as i64,
|
668
|
-
MemFlags::trusted(),
|
669
|
-
),
|
670
|
-
lane_imm: 0,
|
671
|
-
});
|
672
|
-
if flags.unwind_info() {
|
673
|
-
insts.push(Inst::Unwind {
|
674
|
-
inst: UnwindInst::SaveReg {
|
675
|
-
clobber_offset: (i * 8) as u32,
|
676
|
-
reg: reg.to_reg(),
|
677
|
-
},
|
678
|
-
});
|
679
|
-
}
|
680
|
-
}
|
681
|
-
|
682
|
-
insts
|
683
|
-
}
|
684
|
-
|
685
|
-
fn gen_clobber_restore(
|
686
|
-
_call_conv: isa::CallConv,
|
687
|
-
_flags: &settings::Flags,
|
688
|
-
frame_layout: &FrameLayout,
|
689
|
-
) -> SmallVec<[Inst; 16]> {
|
690
|
-
let mut insts = SmallVec::new();
|
691
|
-
|
692
|
-
// Collect clobbered registers.
|
693
|
-
let (first_clobbered_gpr, clobbered_fpr) =
|
694
|
-
get_clobbered_gpr_fpr(&frame_layout.clobbered_callee_saves);
|
695
|
-
|
696
|
-
// Restore FPRs.
|
697
|
-
for (i, reg) in clobbered_fpr.iter().enumerate() {
|
698
|
-
insts.push(Inst::VecLoadLaneUndef {
|
699
|
-
size: 64,
|
700
|
-
rd: Writable::from_reg(reg.to_reg().into()),
|
701
|
-
mem: MemArg::reg_plus_off(
|
702
|
-
stack_reg(),
|
703
|
-
(i * 8) as i64
|
704
|
-
+ frame_layout.outgoing_args_size as i64
|
705
|
-
+ frame_layout.fixed_frame_storage_size as i64,
|
706
|
-
MemFlags::trusted(),
|
707
|
-
),
|
708
|
-
lane_imm: 0,
|
709
|
-
});
|
710
|
-
}
|
711
|
-
|
712
|
-
// Increment stack pointer unless it will be restored implicitly.
|
713
|
-
let stack_size = frame_layout.outgoing_args_size as i32
|
714
|
-
+ frame_layout.clobber_size as i32
|
715
|
-
+ frame_layout.fixed_frame_storage_size as i32;
|
716
|
-
let implicit_sp_restore = first_clobbered_gpr < 16
|
717
|
-
&& SImm20::maybe_from_i64(8 * first_clobbered_gpr as i64 + stack_size as i64).is_some();
|
718
|
-
if !implicit_sp_restore {
|
719
|
-
insts.extend(Self::gen_sp_reg_adjust(stack_size));
|
720
|
-
}
|
721
|
-
|
722
|
-
// Use LMG to restore clobbered GPRs from save area.
|
723
|
-
if first_clobbered_gpr < 16 {
|
724
|
-
let mut offset = 8 * first_clobbered_gpr as i64;
|
725
|
-
if implicit_sp_restore {
|
726
|
-
offset += stack_size as i64;
|
727
|
-
}
|
728
|
-
insts.push(Inst::LoadMultiple64 {
|
729
|
-
rt: writable_gpr(first_clobbered_gpr),
|
730
|
-
rt2: writable_gpr(15),
|
731
|
-
mem: MemArg::reg_plus_off(stack_reg(), offset, MemFlags::trusted()),
|
732
|
-
});
|
733
|
-
}
|
734
|
-
|
735
|
-
insts
|
736
|
-
}
|
737
|
-
|
738
|
-
fn gen_call(
|
739
|
-
_dest: &CallDest,
|
740
|
-
_uses: CallArgList,
|
741
|
-
_defs: CallRetList,
|
742
|
-
_clobbers: PRegSet,
|
743
|
-
_opcode: ir::Opcode,
|
744
|
-
_tmp: Writable<Reg>,
|
745
|
-
_callee_conv: isa::CallConv,
|
746
|
-
_caller_conv: isa::CallConv,
|
747
|
-
_callee_pop_size: u32,
|
748
|
-
) -> SmallVec<[Inst; 2]> {
|
749
|
-
unreachable!();
|
750
|
-
}
|
751
|
-
|
752
|
-
fn gen_memcpy<F: FnMut(Type) -> Writable<Reg>>(
|
753
|
-
_call_conv: isa::CallConv,
|
754
|
-
_dst: Reg,
|
755
|
-
_src: Reg,
|
756
|
-
_size: usize,
|
757
|
-
_alloc: F,
|
758
|
-
) -> SmallVec<[Self::I; 8]> {
|
759
|
-
unimplemented!("StructArgs not implemented for S390X yet");
|
760
|
-
}
|
761
|
-
|
762
|
-
fn get_number_of_spillslots_for_value(
|
763
|
-
rc: RegClass,
|
764
|
-
_vector_scale: u32,
|
765
|
-
_isa_flags: &Self::F,
|
766
|
-
) -> u32 {
|
767
|
-
// We allocate in terms of 8-byte slots.
|
768
|
-
match rc {
|
769
|
-
RegClass::Int => 1,
|
770
|
-
RegClass::Float => 2,
|
771
|
-
RegClass::Vector => unreachable!(),
|
772
|
-
}
|
773
|
-
}
|
774
|
-
|
775
|
-
/// Get the current virtual-SP offset from an instruction-emission state.
|
776
|
-
fn get_virtual_sp_offset_from_state(s: &EmitState) -> i64 {
|
777
|
-
s.virtual_sp_offset
|
778
|
-
}
|
779
|
-
|
780
|
-
/// Get the nominal-SP-to-FP offset from an instruction-emission state.
|
781
|
-
fn get_nominal_sp_to_fp(s: &EmitState) -> i64 {
|
782
|
-
s.initial_sp_offset
|
783
|
-
}
|
784
|
-
|
785
|
-
fn get_machine_env(_flags: &settings::Flags, _call_conv: isa::CallConv) -> &MachineEnv {
|
786
|
-
static MACHINE_ENV: OnceLock<MachineEnv> = OnceLock::new();
|
787
|
-
MACHINE_ENV.get_or_init(create_machine_env)
|
788
|
-
}
|
789
|
-
|
790
|
-
fn get_regs_clobbered_by_call(_call_conv_of_callee: isa::CallConv) -> PRegSet {
|
791
|
-
CLOBBERS
|
792
|
-
}
|
793
|
-
|
794
|
-
fn get_ext_mode(
|
795
|
-
_call_conv: isa::CallConv,
|
796
|
-
specified: ir::ArgumentExtension,
|
797
|
-
) -> ir::ArgumentExtension {
|
798
|
-
specified
|
799
|
-
}
|
800
|
-
|
801
|
-
fn compute_frame_layout(
|
802
|
-
call_conv: isa::CallConv,
|
803
|
-
flags: &settings::Flags,
|
804
|
-
_sig: &Signature,
|
805
|
-
regs: &[Writable<RealReg>],
|
806
|
-
_is_leaf: bool,
|
807
|
-
stack_args_size: u32,
|
808
|
-
fixed_frame_storage_size: u32,
|
809
|
-
mut outgoing_args_size: u32,
|
810
|
-
) -> FrameLayout {
|
811
|
-
assert!(
|
812
|
-
!flags.enable_pinned_reg(),
|
813
|
-
"Pinned register not supported on s390x"
|
814
|
-
);
|
815
|
-
|
816
|
-
let mut regs: Vec<Writable<RealReg>> = regs
|
817
|
-
.iter()
|
818
|
-
.cloned()
|
819
|
-
.filter(|r| is_reg_saved_in_prologue(call_conv, r.to_reg()))
|
820
|
-
.collect();
|
821
|
-
|
822
|
-
// If the front end asks to preserve frame pointers (which we do not
|
823
|
-
// really have in the s390x ABI), we use the stack backchain instead.
|
824
|
-
// For this to work in all cases, we must allocate a stack frame with
|
825
|
-
// at least the outgoing register save area even in leaf functions.
|
826
|
-
// Update our caller's outgoing_args_size to reflect this.
|
827
|
-
if flags.preserve_frame_pointers() {
|
828
|
-
if outgoing_args_size < REG_SAVE_AREA_SIZE {
|
829
|
-
outgoing_args_size = REG_SAVE_AREA_SIZE;
|
830
|
-
}
|
831
|
-
}
|
832
|
-
|
833
|
-
// We need to save/restore the link register in non-leaf functions.
|
834
|
-
// This is not included in the clobber list because we have excluded
|
835
|
-
// call instructions via the is_included_in_clobbers callback.
|
836
|
-
// We also want to enforce saving the link register in leaf functions
|
837
|
-
// for stack unwinding, if we're asked to preserve frame pointers.
|
838
|
-
if outgoing_args_size > 0 {
|
839
|
-
let link_reg = Writable::from_reg(RealReg::from(gpr_preg(14)));
|
840
|
-
if !regs.contains(&link_reg) {
|
841
|
-
regs.push(link_reg);
|
842
|
-
}
|
843
|
-
}
|
844
|
-
|
845
|
-
// Sort registers for deterministic code output. We can do an unstable
|
846
|
-
// sort because the registers will be unique (there are no dups).
|
847
|
-
regs.sort_unstable_by_key(|r| PReg::from(r.to_reg()).index());
|
848
|
-
|
849
|
-
// Compute clobber size. We only need to count FPR save slots.
|
850
|
-
let mut clobber_size = 0;
|
851
|
-
for reg in ®s {
|
852
|
-
match reg.to_reg().class() {
|
853
|
-
RegClass::Int => {}
|
854
|
-
RegClass::Float => {
|
855
|
-
clobber_size += 8;
|
856
|
-
}
|
857
|
-
RegClass::Vector => unreachable!(),
|
858
|
-
}
|
859
|
-
}
|
860
|
-
|
861
|
-
// Return FrameLayout structure.
|
862
|
-
FrameLayout {
|
863
|
-
stack_args_size,
|
864
|
-
setup_area_size: 0,
|
865
|
-
clobber_size,
|
866
|
-
fixed_frame_storage_size,
|
867
|
-
outgoing_args_size,
|
868
|
-
clobbered_callee_saves: regs,
|
869
|
-
}
|
870
|
-
}
|
871
|
-
}
|
872
|
-
|
873
|
-
fn is_reg_saved_in_prologue(_call_conv: isa::CallConv, r: RealReg) -> bool {
|
874
|
-
match r.class() {
|
875
|
-
RegClass::Int => {
|
876
|
-
// r6 - r15 inclusive are callee-saves.
|
877
|
-
r.hw_enc() >= 6 && r.hw_enc() <= 15
|
878
|
-
}
|
879
|
-
RegClass::Float => {
|
880
|
-
// f8 - f15 inclusive are callee-saves.
|
881
|
-
r.hw_enc() >= 8 && r.hw_enc() <= 15
|
882
|
-
}
|
883
|
-
RegClass::Vector => unreachable!(),
|
884
|
-
}
|
885
|
-
}
|
886
|
-
|
887
|
-
fn get_clobbered_gpr_fpr(
|
888
|
-
clobbered_callee_saves: &[Writable<RealReg>],
|
889
|
-
) -> (u8, SmallVec<[Writable<RealReg>; 8]>) {
|
890
|
-
// Collect clobbered registers. Note we save/restore GPR always as
|
891
|
-
// a block of registers using LOAD MULTIPLE / STORE MULTIPLE, starting
|
892
|
-
// with the clobbered GPR with the lowest number up to %r15. We
|
893
|
-
// return the number of that first GPR (or 16 if none is to be saved).
|
894
|
-
let mut clobbered_fpr = SmallVec::new();
|
895
|
-
let mut first_clobbered_gpr = 16;
|
896
|
-
|
897
|
-
for ® in clobbered_callee_saves.iter() {
|
898
|
-
match reg.to_reg().class() {
|
899
|
-
RegClass::Int => {
|
900
|
-
let enc = reg.to_reg().hw_enc();
|
901
|
-
if enc < first_clobbered_gpr {
|
902
|
-
first_clobbered_gpr = enc;
|
903
|
-
}
|
904
|
-
}
|
905
|
-
RegClass::Float => clobbered_fpr.push(reg),
|
906
|
-
RegClass::Vector => unreachable!(),
|
907
|
-
}
|
908
|
-
}
|
909
|
-
|
910
|
-
(first_clobbered_gpr, clobbered_fpr)
|
911
|
-
}
|
912
|
-
|
913
|
-
const fn clobbers() -> PRegSet {
|
914
|
-
PRegSet::empty()
|
915
|
-
.with(gpr_preg(0))
|
916
|
-
.with(gpr_preg(1))
|
917
|
-
.with(gpr_preg(2))
|
918
|
-
.with(gpr_preg(3))
|
919
|
-
.with(gpr_preg(4))
|
920
|
-
.with(gpr_preg(5))
|
921
|
-
// v0 - v7 inclusive and v16 - v31 inclusive are
|
922
|
-
// caller-saves. The upper 64 bits of v8 - v15 inclusive are
|
923
|
-
// also caller-saves. However, because we cannot currently
|
924
|
-
// represent partial registers to regalloc2, we indicate here
|
925
|
-
// that every vector register is caller-save. Because this
|
926
|
-
// function is used at *callsites*, approximating in this
|
927
|
-
// direction (save more than necessary) is conservative and
|
928
|
-
// thus safe.
|
929
|
-
//
|
930
|
-
// Note that we exclude clobbers from a call instruction when
|
931
|
-
// a call instruction's callee has the same ABI as the caller
|
932
|
-
// (the current function body); this is safe (anything
|
933
|
-
// clobbered by callee can be clobbered by caller as well) and
|
934
|
-
// avoids unnecessary saves of v8-v15 in the prologue even
|
935
|
-
// though we include them as defs here.
|
936
|
-
.with(vr_preg(0))
|
937
|
-
.with(vr_preg(1))
|
938
|
-
.with(vr_preg(2))
|
939
|
-
.with(vr_preg(3))
|
940
|
-
.with(vr_preg(4))
|
941
|
-
.with(vr_preg(5))
|
942
|
-
.with(vr_preg(6))
|
943
|
-
.with(vr_preg(7))
|
944
|
-
.with(vr_preg(8))
|
945
|
-
.with(vr_preg(9))
|
946
|
-
.with(vr_preg(10))
|
947
|
-
.with(vr_preg(11))
|
948
|
-
.with(vr_preg(12))
|
949
|
-
.with(vr_preg(13))
|
950
|
-
.with(vr_preg(14))
|
951
|
-
.with(vr_preg(15))
|
952
|
-
.with(vr_preg(16))
|
953
|
-
.with(vr_preg(17))
|
954
|
-
.with(vr_preg(18))
|
955
|
-
.with(vr_preg(19))
|
956
|
-
.with(vr_preg(20))
|
957
|
-
.with(vr_preg(21))
|
958
|
-
.with(vr_preg(22))
|
959
|
-
.with(vr_preg(23))
|
960
|
-
.with(vr_preg(24))
|
961
|
-
.with(vr_preg(25))
|
962
|
-
.with(vr_preg(26))
|
963
|
-
.with(vr_preg(27))
|
964
|
-
.with(vr_preg(28))
|
965
|
-
.with(vr_preg(29))
|
966
|
-
.with(vr_preg(30))
|
967
|
-
.with(vr_preg(31))
|
968
|
-
}
|
969
|
-
|
970
|
-
const CLOBBERS: PRegSet = clobbers();
|
971
|
-
|
972
|
-
fn create_machine_env() -> MachineEnv {
|
973
|
-
MachineEnv {
|
974
|
-
preferred_regs_by_class: [
|
975
|
-
vec![
|
976
|
-
// no r0; can't use for addressing?
|
977
|
-
// no r1; it is our spilltmp.
|
978
|
-
gpr_preg(2),
|
979
|
-
gpr_preg(3),
|
980
|
-
gpr_preg(4),
|
981
|
-
gpr_preg(5),
|
982
|
-
],
|
983
|
-
vec![
|
984
|
-
vr_preg(0),
|
985
|
-
vr_preg(1),
|
986
|
-
vr_preg(2),
|
987
|
-
vr_preg(3),
|
988
|
-
vr_preg(4),
|
989
|
-
vr_preg(5),
|
990
|
-
vr_preg(6),
|
991
|
-
vr_preg(7),
|
992
|
-
vr_preg(16),
|
993
|
-
vr_preg(17),
|
994
|
-
vr_preg(18),
|
995
|
-
vr_preg(19),
|
996
|
-
vr_preg(20),
|
997
|
-
vr_preg(21),
|
998
|
-
vr_preg(22),
|
999
|
-
vr_preg(23),
|
1000
|
-
vr_preg(24),
|
1001
|
-
vr_preg(25),
|
1002
|
-
vr_preg(26),
|
1003
|
-
vr_preg(27),
|
1004
|
-
vr_preg(28),
|
1005
|
-
vr_preg(29),
|
1006
|
-
vr_preg(30),
|
1007
|
-
vr_preg(31),
|
1008
|
-
],
|
1009
|
-
// Vector Regclass is unused
|
1010
|
-
vec![],
|
1011
|
-
],
|
1012
|
-
non_preferred_regs_by_class: [
|
1013
|
-
vec![
|
1014
|
-
gpr_preg(6),
|
1015
|
-
gpr_preg(7),
|
1016
|
-
gpr_preg(8),
|
1017
|
-
gpr_preg(9),
|
1018
|
-
gpr_preg(10),
|
1019
|
-
gpr_preg(11),
|
1020
|
-
gpr_preg(12),
|
1021
|
-
gpr_preg(13),
|
1022
|
-
gpr_preg(14),
|
1023
|
-
// no r15; it is the stack pointer.
|
1024
|
-
],
|
1025
|
-
vec![
|
1026
|
-
vr_preg(8),
|
1027
|
-
vr_preg(9),
|
1028
|
-
vr_preg(10),
|
1029
|
-
vr_preg(11),
|
1030
|
-
vr_preg(12),
|
1031
|
-
vr_preg(13),
|
1032
|
-
vr_preg(14),
|
1033
|
-
vr_preg(15),
|
1034
|
-
],
|
1035
|
-
// Vector Regclass is unused
|
1036
|
-
vec![],
|
1037
|
-
],
|
1038
|
-
fixed_stack_slots: vec![],
|
1039
|
-
scratch_by_class: [None, None, None],
|
1040
|
-
}
|
1041
|
-
}
|