vhdl_tb 0.7.0 → 0.7.5

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
checksums.yaml CHANGED
@@ -1,7 +1,7 @@
1
1
  ---
2
2
  SHA256:
3
- metadata.gz: 60412d4e16c8f944834bc400eea61eb617c2006713e12125a51c38f15ffc39af
4
- data.tar.gz: 9a35251fc2315d50c88fb29d0e0ffd7be194db91cce91bc2af1937122f5f0a30
3
+ metadata.gz: d7f7b2e505776bf00148cc42e65b506ba3b5368c01f77004d487f9fb70cb0b6a
4
+ data.tar.gz: 2af2e0abfed315c9830de2d50a53b73de239e1e39ba5f56965cd41a4e01b50a8
5
5
  SHA512:
6
- metadata.gz: 9dcaaae2c60bf8c91536c9e8a5c8f6f2c5ec7a57728dcbeb338b11300247f96bdd708c8609bb65b7932bd5c1936cdb026c0c3f04cae9146c327e71640eac158e
7
- data.tar.gz: '0229d739111e76d6523876542dde9c0017d154725c6177116d15d5ca86ee77c8a832526d59de64a7550cba467a8c8d90fdf6e7ed985bffd3662ec9dd55fbc8d5'
6
+ metadata.gz: d34267cb16bf1413777547f7314a4669fe98841ee7f965ae09f2635fbc8648324ae348a9cbf2b9b66026da5003b09da2c47b650a5b6529046a2815e9b6909af4
7
+ data.tar.gz: 1a1b7a75777ddfeb3d68a7e48db728a7afe213abb4cc92258009e1cda62b9b4ec51c0f0219ce673b9eae66ab4fc97f7799237dbe2bf58b45f4a34a096573a9f3
data/lib/ast.rb CHANGED
@@ -23,4 +23,11 @@ module VHDL_TB
23
23
  "#{self.name}(#{self.lhs} #{self.dir} #{self.rhs})"
24
24
  end
25
25
  end
26
+
27
+
28
+ Binary=Struct.new(:lhs,:op,:rhs) do
29
+ def to_s
30
+ "#{self.lhs} #{self.op} #{self.rhs}"
31
+ end
32
+ end
26
33
  end
@@ -4,6 +4,7 @@ require 'optparse'
4
4
 
5
5
  require_relative 'ast'
6
6
  require_relative 'parser'
7
+ require_relative 'version'
7
8
 
8
9
  module VHDL_TB
9
10
 
@@ -11,8 +12,6 @@ module VHDL_TB
11
12
 
12
13
  class Compiler
13
14
 
14
- VERSION = "0.7.0"
15
-
16
15
  def initialize
17
16
  #puts __dir__
18
17
  banner
@@ -107,7 +107,7 @@ module VHDL_TB
107
107
  keyword 'xorkeyword '
108
108
 
109
109
  #.............................................................
110
- token :comments => /\A\-\-(.*)$/
110
+ token :comment => /\A\-\-(.*)$/
111
111
  token :selected_name => /\w+(\.\w+)+/ # /\S+\w+\.\w+/
112
112
  token :identifier => /[a-zA-Z]\w*/
113
113
 
@@ -126,6 +126,7 @@ module VHDL_TB
126
126
  token :plus => /\A\+/
127
127
  token :minus => /\A\-/
128
128
  token :times => /\A\*/
129
+ token :div => /\A\//
129
130
 
130
131
  token :sassign => /\A\<\=/
131
132
  token :imply => /\A\=\>/
@@ -136,6 +137,7 @@ module VHDL_TB
136
137
  token :gt => /\A\>/
137
138
  token :lt => /\A\</
138
139
  token :urange => /\A<>/
140
+ token :dot => /\A\./
139
141
  #............................................................
140
142
  token :newline => /[\n]/
141
143
  token :space => /[ \t\r]+/
@@ -3,8 +3,6 @@ require_relative 'generic_parser'
3
3
  require_relative 'ast'
4
4
  require_relative 'lexer'
5
5
 
6
- require 'pp'
7
-
8
6
  module VHDL_TB
9
7
 
10
8
  class Parser < GenericParser
@@ -143,24 +141,35 @@ module VHDL_TB
143
141
 
144
142
  def parse_type
145
143
  type=Identifier.new
146
- type.tok=expect(:identifier)
147
- if showNext.is_a? :lparen
148
- acceptIt
149
- name=type.tok
150
- type=VectorType.new
151
- type.name=name
152
- type.lhs=parse_expression
153
- if showNext.is_a? [:downto,:to]
154
- type.dir=acceptIt
144
+ case showNext.kind
145
+ when :identifier
146
+ type.tok=expect(:identifier)
147
+ if showNext.is_a? :lparen
148
+ acceptIt
149
+ name=type.tok
150
+ type=VectorType.new
151
+ type.name=name
152
+ type.lhs=parse_expression
153
+ if showNext.is_a? [:downto,:to]
154
+ type.dir=acceptIt
155
+ end
156
+ type.rhs=parse_expression
157
+ expect :rparen
155
158
  end
156
- type.rhs=parse_expression
157
- expect :rparen
159
+ else
160
+ type.tok=acceptIt # natural,...
158
161
  end
159
162
  type
160
163
  end
161
164
 
162
165
  def parse_expression
163
- parse_term
166
+ e1=parse_term
167
+ while showNext.is_a? [:plus,:minus,:times,:div]
168
+ op=acceptIt
169
+ e2=parse_term
170
+ e1=Binary.new(e1,op,e2)
171
+ end
172
+ return e1
164
173
  end
165
174
 
166
175
  def parse_term
@@ -0,0 +1,3 @@
1
+ module VHDL_TB
2
+ VERSION="0.7.5"
3
+ end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: vhdl_tb
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.7.0
4
+ version: 0.7.5
5
5
  platform: ruby
6
6
  authors:
7
7
  - Jean-Christophe Le Lann
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2018-10-12 00:00:00.000000000 Z
11
+ date: 2019-11-08 00:00:00.000000000 Z
12
12
  dependencies: []
13
13
  description: A simple testbench generator for VHDL
14
14
  email: jean-christophe.le_lann@ensta-bretagne.fr
@@ -28,6 +28,7 @@ files:
28
28
  - lib/parser.rb
29
29
  - lib/template.tb.vhd
30
30
  - lib/token.rb
31
+ - lib/version.rb
31
32
  - tests/circuit.vhd
32
33
  homepage: http://rubygems.org/gems/vhdl_tb
33
34
  licenses:
@@ -48,8 +49,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
48
49
  - !ruby/object:Gem::Version
49
50
  version: '0'
50
51
  requirements: []
51
- rubyforge_project:
52
- rubygems_version: 2.7.7
52
+ rubygems_version: 3.0.6
53
53
  signing_key:
54
54
  specification_version: 4
55
55
  summary: VHDL Testbench generator