vhdl_tb 0.6.3 → 0.6.5
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- checksums.yaml +4 -4
- data/lib/ast.rb +1 -1
- data/lib/compiler.rb +4 -7
- data/lib/lexer.rb +31 -20
- data/lib/parser.rb +1 -1
- data/lib/template.tb.vhd +1 -1
- metadata +2 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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1
1
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---
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2
2
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SHA1:
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3
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-
metadata.gz:
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4
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-
data.tar.gz:
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3
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+
metadata.gz: cd1879cca3683122f2deaf4d3e42937f5a4fe870
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4
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+
data.tar.gz: 700d2f736b29de611e5b2834ea0e500e8e189a90
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5
5
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SHA512:
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6
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-
metadata.gz:
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7
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data.tar.gz:
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6
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+
metadata.gz: c131814294a059dbe6eb5eaf1a557be6a0326cbcf0fb81014e5c608feb2ed77fbb737cdbc085c331a85c164ab5ce6eeb6015b15f4eb7058e733cdcbf17ba0aea
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7
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+
data.tar.gz: 5f300c1af6f426f300d7a87478e44cf4de5d3daacef47df740628508a017c1fe92c2ccddb1d70ae5e04ac975ca97c4d2a90673d77dabe2102e7961d2bfe38ce4
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data/lib/ast.rb
CHANGED
data/lib/compiler.rb
CHANGED
@@ -11,7 +11,7 @@ module VHDL_TB
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11
11
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class Compiler
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-
VERSION = "0.6.
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+
VERSION = "0.6.5"
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def initialize
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#puts __dir__
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@@ -21,10 +21,9 @@ module VHDL_TB
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end
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def banner
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-
puts "-- "+"="*
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puts "
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-
puts "-- "+"="*
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-
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24
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+
#puts "-- "+"="*30
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puts "==> VHDL testbench generator #{VERSION} <=="
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#puts "-- "+"="*30
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end
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29
28
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def analyze_options args
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@@ -115,8 +114,6 @@ module VHDL_TB
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115
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end
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end
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-
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-
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end
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end
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data/lib/lexer.rb
CHANGED
@@ -4,28 +4,39 @@ class Lexer < GenericLexer
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4
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def initialize
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super
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ignore /\s+/
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7
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+
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8
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#comments
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9
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+
token :comment => /--(.*)$/
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10
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+
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#....keywords
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8
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-
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-
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-
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-
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-
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-
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-
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-
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-
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token :
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token :
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token :
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token :
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-
token :
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token :
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keyword :entity
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keyword :is
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keyword :generic
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keyword :port
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keyword :in
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keyword :to
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keyword :downto
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keyword :out
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keyword :end
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keyword :architecture
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keyword :of
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+
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#punctuation
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token :vassign => /\:\=/
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token :sassign => /\<\=/
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token :lparen => /\(/
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token :rparen => /\)/
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token :semicolon => /\;/
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token :colon => /\:/
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token :dot => /\./
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token :comma => /\,/
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token :rightarrow => /\=\>/
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token :"-" => /\-/
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token :"=" => /\=/
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#terminals
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token :id => /[a-zA-Z_][a-zA-Z0-9_]*/i
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token :int_lit => /[0-9]+/
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-
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39
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+
token :char_lit => /'[a-zA-Z0-9_]*'/
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token :str_lit => /\"(.*)\"/
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end
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31
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end
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data/lib/parser.rb
CHANGED
data/lib/template.tb.vhd
CHANGED
@@ -1,5 +1,5 @@
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1
1
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-----------------------------------------------------------------
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2
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-
-- This file was generated automatically by
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2
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+
-- This file was generated automatically by vhdl_tb Ruby utility
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-- date : <%=Time.now.strftime("(d/m/y) %d/%m/%Y %H:%M")%>
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-- Author : Jean-Christophe Le Lann - 2014
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-----------------------------------------------------------------
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metadata
CHANGED
@@ -1,14 +1,14 @@
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1
1
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--- !ruby/object:Gem::Specification
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2
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name: vhdl_tb
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version: !ruby/object:Gem::Version
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4
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-
version: 0.6.
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4
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+
version: 0.6.5
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5
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platform: ruby
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authors:
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- Jean-Christophe Le Lann
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autorequire:
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bindir: bin
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cert_chain: []
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11
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-
date: 2018-
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+
date: 2018-06-01 00:00:00.000000000 Z
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dependencies: []
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description: A simple testbench generator for VHDL
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email: jean-christophe.le_lann@ensta-bretagne.fr
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