vhdl_tb 0.2

checksums.yaml

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+---
+SHA1:
+  metadata.gz: 61e50cf3e02216bb813808b913f5df66188ed468
+  data.tar.gz: 5bb80eccc0368b0626d49662f2910f152d0b52ad
+SHA512:
+  metadata.gz: 86aa3ba40f08469e02b7b7fac6a86e6489685d46ef22e09f75c8d224c1e4cade76733039598a11d373ab5c1c0b8f5b61b9b23d3732a2e5553d6b0e9b6b791146
+  data.tar.gz: 8aecc52f8f78b2b5c74d09063e2fabccd0e5969ce70b6e8ed82ec9521853e84736bf127a9d708882d27683c36caac0c03d24dedecfbe0c381eb07d47e644912c

data/bin/tbgen

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+#!/usr/bin/env ruby
+
+require_relative '../lib/vhdl_tb'
+generator=VhdlTb.new
+generator.analyze_options(ARGV)
+generator.generate

data/bin/vhdl_tb

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+#!/usr/bin/env ruby
+
+require_relative '../lib/vhdl_tb'
+generator=VhdlTb.new
+generator.analyze_options(ARGV)
+generator.generate

data/lib/template.tb.vhd

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+-----------------------------------------------------------------
+-- This file was generated automatically by tb_gen Ruby utility
+-- date : <%=Time.now.strftime("(d/m/y) %d/%m/%Y %H:%M")%>
+-- Author : Jean-Christophe Le Lann - 2014
+-----------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity <%=@tb.name%> is
+end entity;
+
+architecture bhv of <%=@tb.name%> is
+
+  constant HALF_PERIOD : time := 5 ns;
+
+  signal clk     : std_logic := '0';
+  signal reset_n : std_logic := '0';
+  signal sreset  : std_logic := '0';
+  signal running : boolean   := true;
+
+  procedure wait_cycles(n : natural) is
+   begin
+     for i in 1 to n loop
+       wait until rising_edge(clk);
+     end loop;
+   end procedure;
+
+<%=@entity.ports.collect do |port|
+  "  signal #{port.name.rjust(@max_length)} : #{port.type}" if not @symtable.include?(port.name)
+  end.compact.join(";\n")%>;
+
+begin
+  -------------------------------------------------------------------
+  -- clock and reset
+  -------------------------------------------------------------------
+  reset_n <= '0','1' after 666 ns;
+
+  clk <= not(clk) after HALF_PERIOD when running else clk;
+
+  --------------------------------------------------------------------
+  -- Design Under Test
+  --------------------------------------------------------------------
+  dut : entity work.<%=@entity.name%>(<%=@arch.name%>)
+         port map (
+  <%=@entity.ports.collect{|port| "\t   #{port.name.ljust(@max_length)} => #{port.name}"}.join(",\n")%>);
+
+  --------------------------------------------------------------------
+  -- sequential stimuli
+  --------------------------------------------------------------------
+  stim : process
+   begin
+     report "running testbench for <%=@entity.name%>(<%=@arch.name%>)";
+     report "waiting for asynchronous reset";
+     wait until reset_n='1';
+     report "applying stimuli...";
+     wait_cycles(100);
+     report "end of simulation";
+     running <=false;
+     wait;
+   end process;
+
+end bhv;

data/lib/vhdl_tb.rb

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+require 'erb'
+require 'pp'
+require 'optparse'
+
+Entity       = Struct.new("Entity",:name,:ports)
+Architecture = Struct.new("Architecture",:name,:entity)
+Port         = Struct.new("Port",:name,:dir,:type)
+Testbench    = Struct.new("Testbench",:name)
+
+class VhdlTb
+
+  VERSION = "0.2"
+
+  def initialize
+    #puts __dir__
+    banner
+    @engine=ERB.new(IO.read "#{__dir__}/template.tb.vhd")
+  end
+
+  def banner
+    puts "-- "+"="*60
+    puts "-- VHDL testbench generator -- Jean-Christophe Le Lann 2017"
+    puts "-- "+"="*60
+
+  end
+
+  def analyze_options args
+    args << "-h" if args.empty?
+
+    opt_parser = OptionParser.new do |opts|
+      opts.banner = "Usage: vhdl_tb (or tbgen) <filename>"
+
+      opts.on("-v", "--version", "Prints version") do |n|
+        puts VERSION
+        abort
+      end
+
+      opts.on("-h", "--help", "Prints this help") do
+        puts "Generates testbench in VHDL, from a given file containing an Entity-Architecture couple."
+        puts
+        puts opts
+        abort
+      end
+    end
+
+    begin
+      opt_parser.parse!(args)
+      @args=args
+
+    rescue Exception => e
+      puts e
+      #puts e.backtrace
+      exit
+    end
+  end
+
+  def generate entity_filename=@args.first
+    @symtable=[]
+    @symtable << "clk"
+    @symtable << "reset_n"
+    @symtable << "sreset"
+    analyze(entity_filename)
+    tb_txt=@engine.result(binding)
+    tb_filename="#{@tb.name}.vhd"
+    File.open(tb_filename,'w'){|f| f.puts tb_txt}
+    puts "testbench generated : #{tb_filename}"
+  end
+
+  def analyze entity_filename
+    puts "analyzing VHDL file : #{entity_filename}"
+    code=IO.read(entity_filename)
+    regexp_entity=/entity\s+(\w+)\s+is\s+port\s*\((.*)\).*end\s+/im
+    entity_matched = regexp_entity.match(code)
+    name,iotext=*entity_matched.captures
+
+    ioregexp=/(\w+)\s*:\s*(\w+)\s+(.*)\s*;?/ix
+    iotab= iotext.scan(ioregexp)
+    io= to_port(iotab)
+    puts "entity found        : #{name} (#{io.size} ports)"
+    @entity=Entity.new(name,io)
+
+    regexp_arch=/architecture\s+(\w+)\s+of\s+(\w+)/im
+    arch_matched = regexp_arch.match(code)
+    arch_name,entity_name=*arch_matched.captures
+    @arch=Architecture.new(arch_name,entity_name)
+    @tb=Testbench.new(@entity.name+"_tb")
+  end
+
+  def to_port iotab
+    @max_length=0
+    iotab.collect do |io|
+      name,dir,type=io
+      type=type.split(";")[0] #suppress comments
+      @max_length=name.size if name.size>@max_length
+      Port.new(name,dir,type)
+    end
+  end
+
+end
+
+if $PROGRAM_NAME == __FILE__
+  raise "you need to provide a VHDL file that contains the entity to test" if ARGV.size==0
+  filename=ARGV[0]
+  VhdlTb.new.generate(filename)
+end

data/tests/circuit.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity circuit is
+   port(
+     reset_n : in std_logic;
+     clock   : in std_logic;
+     a,b     : in unsigned(7 downto 0);
+     f       : in unsigned(7 downto 0)
+   );
+end circuit;
+
+architecture rtl of circuit is
+begin
+end rtl;

metadata

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+--- !ruby/object:Gem::Specification
+name: vhdl_tb
+version: !ruby/object:Gem::Version
+  version: '0.2'
+platform: ruby
+authors:
+- Jean-Christophe Le Lann
+autorequire: 
+bindir: bin
+cert_chain: []
+date: 2017-10-16 00:00:00.000000000 Z
+dependencies: []
+description: A simple testbench generator for VHDL
+email: jean-christophe.le_lann@ensta-bretagne.fr
+executables:
+- vhdl_tb
+- tbgen
+extensions: []
+extra_rdoc_files: []
+files:
+- bin/tbgen
+- bin/vhdl_tb
+- lib/template.tb.vhd
+- lib/vhdl_tb.rb
+- tests/circuit.vhd
+homepage: http://rubygems.org/gems/vhdl_tb
+licenses:
+- MIT
+metadata: {}
+post_install_message: 
+rdoc_options: []
+require_paths:
+- lib
+required_ruby_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+required_rubygems_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+requirements: []
+rubyforge_project: 
+rubygems_version: 2.6.12
+signing_key: 
+specification_version: 4
+summary: VHDL Testbench generator
+test_files: []