vhdl_help 0.4.1 → 0.4.2

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA1:
-  metadata.gz: 7ad12d40e966b06c2ac4574336caec040268b817
-  data.tar.gz: 4d1a32a437d0c1283d553d13d684bbd17c45f37f
+  metadata.gz: 857ffe4c3fd8be5eed3fe3319514e61e8d933466
+  data.tar.gz: 7a344f4ed091dcfd84cf872c1af1685019e9d75f
 SHA512:
-  metadata.gz: b9769286eca4b9f33a4dda931337aef192abae664b98086646f889235340659864393d04a2a6e30cd7d18e78d8f64645018e8564a060e22831cfdd9e8a3ed1cf
-  data.tar.gz: 3e31d1b597c7ac291cbafc28778d3f84a031751e50a418c545b608b1ec82170ed4d238a9e353bf4c05978d93aeb8dbd4ac1468c21656126e73a04cd807877e0e
+  metadata.gz: b2ce45e4c740368df4df2ae852bdf20d2f1111fab7bcc0dc38942dd8e775fbea616172a5c598061be86d608870f0fd3f8dc5cea4c4b7ebc91f0a72989fb64d99
+  data.tar.gz: e0db31838aff28f73d364f356a3e73489ee73a157d1fe7a4f17dd3efcfe2b42e3229c0218e967f93ba11b6a35be14ece46e1e601fe5fa87764df50edc95b19c9

data/lib/templates/file_read.vhd

@@ -0,0 +1,36 @@
+stimuli_proc : process
+   file F : text;
+   variable L: line;
+   variable status : file_open_status;
+   variable data : integer;
+   variable nb_samples : natural := 0;
+  begin
+
+    report "n (window size) = " & integer'image(n);
+    report "sample_width    = " & integer'image(sample_width);
+    report "output_width    = " & integer'image(output_width);
+
+    FILE_OPEN(status,F,"samples.txt",read_mode);
+    if status/=open_ok then
+      report "problem to open stimulus file samples.text" severity error;
+    else
+      sample <= to_signed(0,sample_width);
+      sample_valid <= '0';
+      wait until reset_n='1';
+      report "size of moving average : " & integer'image(n);
+      report "starting samples...";
+      while not(ENDFILE(f)) loop
+        nb_samples:=nb_samples+1;
+        wait until rising_edge(clk);
+        readline(F,l);
+        read(l,data);
+        sample <= to_signed(data,sample_width);
+        sample_valid <= '1';
+      end loop;
+      sample_valid <= '0';
+      report "end of simulation";
+      report integer'image(nb_samples) & " samples processed.";
+    end if;
+    running <= false;
+    wait;
+  end process;

data/lib/templates/file_write.vhd

@@ -0,0 +1,28 @@
+-- procedure WRITE(L : inout LINE; VALUE : in integer; JUSTIFIED: in SIDE := right; FIELD: in WIDTH := 0);
+
+
+signal o_valid        : std_logic;
+signal o_add          : std_logic_vector(7 downto 0);
+
+--SKIPPED
+
+p_dump  : process(i_rstb,i_clk)
+  file test_vector      : text open write_mode is "output_file.txt";
+  variable row          : line;
+begin
+
+  if (i_rstb='0') then
+  -- SKIPPED
+  elsif(rising_edge(i_clk)) then
+    if(o_valid = '1') then
+      write(row,o_add, right, 15);
+
+      write(row,conv_integer(o_add), right, 15);
+      hwrite(row,o_add, right, 15);
+      hwrite(row,"00000000"&o_add, right, 15);
+
+      writeline(test_vector,row);
+
+    end if;
+  end if;
+end process p_dump;

data/lib/templates/sw_emulation.vhd

@@ -0,0 +1,63 @@
+embedded_software_emulation : process
+    procedure clean  is
+    begin
+      ce <= '0';
+      we <= '0';
+      address <= (others=>'0');
+      datain  <= (others=>'0');
+      wait_cycles(1);
+    end procedure;
+
+    procedure write_bus(addr : unsigned; data : std_logic_vector) is
+    begin
+      wait_cycles(1);
+      ce <= '1';
+      we <= '1';
+      address <= addr;
+      datain  <= data;
+      wait_cycles(1);
+      ce <= '0';
+      we <= '0';
+      address <= (others=>'0');
+      datain  <= (others=>'0');
+    end procedure;
+
+    procedure read_bus(addr:unsigned) is
+    begin
+      wait_cycles(1);
+      ce <= '1';
+      we <= '0';
+      address <= addr;
+      wait_cycles(1);
+      ce <= '0';
+      address <= (others=>'0');
+      datain  <= (others=>'0');
+    end procedure;
+
+    variable reg_val : unsigned(63 downto 0);
+   begin
+     clean;
+     report "running testbench for ip_ms_mergesort";
+     report "waiting for asynchronous reset";
+     wait until reset_n='1';
+     wait_cycles(10);
+     report "applying stimuli...";
+     write_bus(ADDR_REG_AP_START,x"0000000000000001");
+     write_bus(ADDR_REG_AP_START,x"0000000000000000");
+
+     polling: while true loop
+       read_bus(ADDR_REG_AP_DONE);
+       reg_val := unsigned(dataout);
+       report "dataout = " & integer'image(to_integer(reg_val(31 downto 0)));
+       if reg_val=x"0000000000000001" then
+         exit polling;
+       end if;
+     end loop;
+     work.tunnels.dump_memory <= true;
+     report "";
+     wait_cycles(30);
+     report "end of simulation";
+     running <=false;
+     wait;
+
+   end process;

data/lib/vhdl_helper.rb

@@ -5,7 +5,7 @@ require 'optparse'
 
 class VhdlHelper
 
-  VERSION = "0.4.1"
+  VERSION = "0.4.2"
 
   def initialize
     puts "-- "+"="*60
@@ -62,6 +62,7 @@ class VhdlHelper
     path=__dir__+"/templates/*.vhd"
     files=Dir[path]
     concepts=files.collect{|filename| filename.split("/").last.match(/(.*).vhd/)[1]}
+    concepts.sort!
     concepts.each do |concept|
       puts "- #{concept}"
     end

metadata

@@ -1,7 +1,7 @@
 --- !ruby/object:Gem::Specification
 name: vhdl_help
 version: !ruby/object:Gem::Version
-  version: 0.4.1
+  version: 0.4.2
 platform: ruby
 authors:
 - Jean-Christophe Le Lann
@@ -22,11 +22,14 @@ files:
 - lib/templates/conversions.vhd
 - lib/templates/counter.vhd
 - lib/templates/entity.vhd
+- lib/templates/file_read.vhd
+- lib/templates/file_write.vhd
 - lib/templates/fsm.vhd
 - lib/templates/header.vhd
 - lib/templates/memory.vhd
 - lib/templates/procedure.vhd
 - lib/templates/skeleton.vhd
+- lib/templates/sw_emulation.vhd
 - lib/templates/testbench.vhd
 - lib/vhdl_helper.rb
 homepage: http://rubygems.org/gems/vhdl_help