vhdl_help 0.4.1 → 0.4.2
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- checksums.yaml +4 -4
- data/lib/templates/file_read.vhd +36 -0
- data/lib/templates/file_write.vhd +28 -0
- data/lib/templates/sw_emulation.vhd +63 -0
- data/lib/vhdl_helper.rb +2 -1
- metadata +4 -1
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA1:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 857ffe4c3fd8be5eed3fe3319514e61e8d933466
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4
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data.tar.gz: 7a344f4ed091dcfd84cf872c1af1685019e9d75f
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: b2ce45e4c740368df4df2ae852bdf20d2f1111fab7bcc0dc38942dd8e775fbea616172a5c598061be86d608870f0fd3f8dc5cea4c4b7ebc91f0a72989fb64d99
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7
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data.tar.gz: e0db31838aff28f73d364f356a3e73489ee73a157d1fe7a4f17dd3efcfe2b42e3229c0218e967f93ba11b6a35be14ece46e1e601fe5fa87764df50edc95b19c9
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@@ -0,0 +1,36 @@
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stimuli_proc : process
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file F : text;
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variable L: line;
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variable status : file_open_status;
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variable data : integer;
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variable nb_samples : natural := 0;
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begin
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report "n (window size) = " & integer'image(n);
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report "sample_width = " & integer'image(sample_width);
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report "output_width = " & integer'image(output_width);
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FILE_OPEN(status,F,"samples.txt",read_mode);
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if status/=open_ok then
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report "problem to open stimulus file samples.text" severity error;
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else
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sample <= to_signed(0,sample_width);
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sample_valid <= '0';
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wait until reset_n='1';
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report "size of moving average : " & integer'image(n);
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report "starting samples...";
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while not(ENDFILE(f)) loop
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nb_samples:=nb_samples+1;
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wait until rising_edge(clk);
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readline(F,l);
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read(l,data);
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sample <= to_signed(data,sample_width);
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sample_valid <= '1';
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end loop;
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sample_valid <= '0';
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report "end of simulation";
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report integer'image(nb_samples) & " samples processed.";
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end if;
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running <= false;
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wait;
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end process;
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@@ -0,0 +1,28 @@
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-- procedure WRITE(L : inout LINE; VALUE : in integer; JUSTIFIED: in SIDE := right; FIELD: in WIDTH := 0);
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signal o_valid : std_logic;
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signal o_add : std_logic_vector(7 downto 0);
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--SKIPPED
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p_dump : process(i_rstb,i_clk)
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file test_vector : text open write_mode is "output_file.txt";
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variable row : line;
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begin
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if (i_rstb='0') then
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-- SKIPPED
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elsif(rising_edge(i_clk)) then
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if(o_valid = '1') then
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write(row,o_add, right, 15);
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write(row,conv_integer(o_add), right, 15);
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hwrite(row,o_add, right, 15);
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hwrite(row,"00000000"&o_add, right, 15);
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writeline(test_vector,row);
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end if;
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end if;
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end process p_dump;
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@@ -0,0 +1,63 @@
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embedded_software_emulation : process
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procedure clean is
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begin
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ce <= '0';
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we <= '0';
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address <= (others=>'0');
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datain <= (others=>'0');
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wait_cycles(1);
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end procedure;
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procedure write_bus(addr : unsigned; data : std_logic_vector) is
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begin
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wait_cycles(1);
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ce <= '1';
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we <= '1';
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address <= addr;
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datain <= data;
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wait_cycles(1);
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ce <= '0';
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we <= '0';
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address <= (others=>'0');
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datain <= (others=>'0');
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end procedure;
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procedure read_bus(addr:unsigned) is
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begin
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wait_cycles(1);
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ce <= '1';
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we <= '0';
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address <= addr;
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wait_cycles(1);
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ce <= '0';
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address <= (others=>'0');
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datain <= (others=>'0');
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end procedure;
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variable reg_val : unsigned(63 downto 0);
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begin
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clean;
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report "running testbench for ip_ms_mergesort";
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report "waiting for asynchronous reset";
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wait until reset_n='1';
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wait_cycles(10);
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report "applying stimuli...";
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write_bus(ADDR_REG_AP_START,x"0000000000000001");
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write_bus(ADDR_REG_AP_START,x"0000000000000000");
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polling: while true loop
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read_bus(ADDR_REG_AP_DONE);
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reg_val := unsigned(dataout);
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report "dataout = " & integer'image(to_integer(reg_val(31 downto 0)));
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if reg_val=x"0000000000000001" then
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exit polling;
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end if;
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end loop;
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work.tunnels.dump_memory <= true;
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report "";
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wait_cycles(30);
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report "end of simulation";
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running <=false;
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wait;
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end process;
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data/lib/vhdl_helper.rb
CHANGED
@@ -5,7 +5,7 @@ require 'optparse'
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5
5
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6
6
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class VhdlHelper
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7
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8
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VERSION = "0.4.
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VERSION = "0.4.2"
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9
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def initialize
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11
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puts "-- "+"="*60
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@@ -62,6 +62,7 @@ class VhdlHelper
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path=__dir__+"/templates/*.vhd"
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63
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files=Dir[path]
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64
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concepts=files.collect{|filename| filename.split("/").last.match(/(.*).vhd/)[1]}
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concepts.sort!
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concepts.each do |concept|
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puts "- #{concept}"
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end
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metadata
CHANGED
@@ -1,7 +1,7 @@
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1
1
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--- !ruby/object:Gem::Specification
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2
2
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name: vhdl_help
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version: !ruby/object:Gem::Version
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version: 0.4.
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version: 0.4.2
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platform: ruby
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authors:
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- Jean-Christophe Le Lann
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@@ -22,11 +22,14 @@ files:
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- lib/templates/conversions.vhd
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23
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- lib/templates/counter.vhd
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24
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- lib/templates/entity.vhd
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- lib/templates/file_read.vhd
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26
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- lib/templates/file_write.vhd
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27
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- lib/templates/fsm.vhd
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- lib/templates/header.vhd
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- lib/templates/memory.vhd
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28
30
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- lib/templates/procedure.vhd
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29
31
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- lib/templates/skeleton.vhd
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32
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- lib/templates/sw_emulation.vhd
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30
33
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- lib/templates/testbench.vhd
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31
34
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- lib/vhdl_helper.rb
|
32
35
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homepage: http://rubygems.org/gems/vhdl_help
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