vhdl_help 0.2 → 0.3
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- checksums.yaml +4 -4
- data/lib/templates/memory.vhd +27 -8
- data/lib/vhdl_helper.rb +1 -1
- metadata +3 -3
checksums.yaml
CHANGED
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@@ -1,7 +1,7 @@
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1
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---
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SHA1:
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-
metadata.gz:
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data.tar.gz:
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3
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metadata.gz: dc9ff642cff46fecb79dfa6a055afaa21c4cc798
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4
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data.tar.gz: 23db7b8291fa720f35273add71558048b67b3a23
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5
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SHA512:
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6
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-
metadata.gz:
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data.tar.gz:
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metadata.gz: 8af0a219cce34d84d884804738c6eeee91a55160b7208a0ca872809c292cda985ce9edd84176d5acd73ac17d80b8217c16ca9701fa694de716dd8533f11dfb24
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7
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+
data.tar.gz: 3449b0c1bfd0726c1bb4c3bde1cd07ed514774361cb956e449693c94324196c456d9cfe44cd82eee8a7307efe076f240efab21c42220599ba2e43e89a69579eb
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data/lib/templates/memory.vhd
CHANGED
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@@ -1,21 +1,40 @@
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1
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+
library ieee;
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2
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+
use ieee.std_logic_1164.all;
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3
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+
use ieee.numeric_std.all;
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1
4
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2
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-
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5
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+
entity ram is
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6
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port(
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7
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reset_n : in std_logic;
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8
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clk : in std_logic;
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9
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wr : in std_logic;
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10
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address : in unsigned(7 downto 0);
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11
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datain : in std_logic_vector(7 downto 0);
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12
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dataout : out std_logic_vector(7 downto 0)
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13
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);
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14
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end entity;
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3
15
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4
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-
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5
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-
signal mem : memory_type;
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16
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architecture rtl of ram is
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6
17
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18
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type memory_type is array(0 to 255) of std_logic_vector(7 downto 0);
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19
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signal mem : memory_type;
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20
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signal addr_r : unsigned(7 downto 0);
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7
21
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begin
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22
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9
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-
write_p:process(reset_n,clk)
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10
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-
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23
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write_p : process(reset_n, clk)
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24
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begin
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25
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if reset_n = '0' then
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11
26
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for i in 0 to 255 loop
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12
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-
mem(i) <= (others=>'0');
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27
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+
mem(i) <= (others => '0');
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13
28
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end loop;
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29
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+
addr_r <= to_unsigned(0, 8);
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14
30
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elsif rising_edge(clk) then
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15
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-
if wr='1' then
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16
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-
mem(to_integer(
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31
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+
if wr = '1' then
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32
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mem(to_integer(address)) <= datain;
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17
33
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end if;
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34
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addr_r <= address;
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18
35
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end if;
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19
36
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end process;
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20
37
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38
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+
dataout <= mem(to_integer(addr_r));
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39
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+
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21
40
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end rtl;
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data/lib/vhdl_helper.rb
CHANGED
metadata
CHANGED
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@@ -1,14 +1,14 @@
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1
1
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--- !ruby/object:Gem::Specification
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2
2
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name: vhdl_help
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3
3
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version: !ruby/object:Gem::Version
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4
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-
version: '0.
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4
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version: '0.3'
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5
5
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platform: ruby
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6
6
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authors:
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7
7
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- Jean-Christophe Le Lann
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8
8
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autorequire:
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9
9
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bindir: bin
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10
10
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cert_chain: []
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11
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-
date:
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11
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+
date: 2018-03-09 00:00:00.000000000 Z
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12
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dependencies: []
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13
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description: A simple snippets generator for VHDL
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14
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email: jean-christophe.le_lann@ensta-bretagne.fr
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@@ -49,7 +49,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
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49
49
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version: '0'
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50
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requirements: []
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51
51
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rubyforge_project:
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52
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-
rubygems_version: 2.6.
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52
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+
rubygems_version: 2.6.14
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53
53
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signing_key:
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54
54
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specification_version: 4
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55
55
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summary: VHDL Snippets Generator
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