vhdl_help 0.1

checksums.yaml

@@ -0,0 +1,7 @@
+---
+SHA1:
+  metadata.gz: 3a2aec5ff639c532645351dad1ff4f2bf3a57592
+  data.tar.gz: 60ebd00aae9fe2cddc24d5a5fc11616a8537ecc9
+SHA512:
+  metadata.gz: 7d2e48c0f2b426f501bef330853c9dbee9a9a54bb214ab08fbd702898c8e47a7e90932e09f048db56f2747420c5d808605ec93ea308de4fc17445e92889efa09
+  data.tar.gz: a7c3480e1043ade625e875f017f516bfa7e5cd13288862986755d278753df48b47057770e59c0139d639832755c8cece5b4ddb76eca40519a72678f6952ae153

data/bin/vhdl_help

@@ -0,0 +1,6 @@
+#!/usr/bin/env ruby
+
+require_relative '../lib/vhdl_helper'
+helper=VhdlHelper.new
+helper.analyze_options(ARGV)
+helper.help

data/lib/templates/clock.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb is
+end tb;
+
+architecture bhv of tb is
+
+  constant HALF_PERIOD : time := 5 ns; --100Mhz
+  signal running : boolean := true;
+  signal clk : std_logic := '0';
+
+begin
+
+  -- clock generator
+  clk <= not clk a after HALF_PERIOD when running else clk;
+
+
+end bhv;

data/lib/templates/conversions.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb is
+end tb;
+
+architecture bhv of tb is
+
+  signal stdlv : std_logic_vector(31 downto 0);
+  signal u32   : unsigned(11 downto 0);
+  signal u16   : unsigned(11 downto 0);
+  signal u12   : unsigned(11 downto 0);
+  signal s12   : signed(11 downto 0);
+
+begin
+  stdlv <= x"deedbeef";
+  u32   <= unsigned(stdlv);
+  u12   <= resize(u32,12);
+
+  s12 <= resize(signed(stdlv),12);
+
+  u16 <= resize(to_unsigned(42,12),16);
+
+end bhv;

data/lib/templates/counter.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter is
+  generic(N : natural := 8)
+  port(
+    reset_n : in std_logic;
+    clk     : in std_logic;
+    enable  : in std_logic;
+    value   : out unsigned(N-1 downto 0)
+  );
+end counter;
+
+architecture rtl of counter is
+  signal count : unsigned(N-1 downto 0);
+begin
+
+  counting: process(reset_n,clk)
+  begin
+    if reset_n='0' then
+      count <= to_unsigned(0,N);
+    elsif rising_edge(clk) then
+      if enable='1' then
+        count <= count + 1;
+      end if
+    end if;
+  end process;
+
+  value <= count;
+end rtl;

data/lib/templates/entity.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter is
+  generic(N : natural := 8)
+  port(
+    reset_n : in std_logic;
+    clk     : in std_logic;
+    enable  : in std_logic;
+    value   : out unsigned(N-1 downto 0)
+  );
+end counter;

data/lib/templates/fsm.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity fsm is
+  port(
+    reset_n : in std_logic;
+    clk : in std_logic;
+    go : in std_logic;
+    f  : out unsigned(7 downto 0)
+  );
+end fsm;
+
+architecture rtl_1 of fsm is
+
+  type state_type is (IDLE,PING,PONG);
+  signal state_r,state_c : state_type;
+  signal output_f : unsigned(7 downto 0);
+
+begin
+
+  tick : process(reset_n,clk)
+  begin
+    if reset_n='0' then
+      state_r <= IDLE;
+    elsif rising_edge(clk) then
+      state_r <= state_c;
+    end if;
+  end process;
+
+  comb:process(go)
+    begin
+      state_c <= state_r; --default assigment
+      case state_r is
+        when IDLE =>
+          if go='1' then
+            state_c <= PING;
+          end if;
+        when PING =>
+          state_c <= PONG;
+        when PONG =>
+          state_c <= PING;
+        when others =>
+          null;
+      end case;
+  end process;
+
+  output_gen :process(reset_n,clk)
+   begin
+     if reset_n='0' then
+       output_f <= (others=>'0');
+     elsif rising_edge(clk) then
+       if state_r=PONG then
+         output_f <= output_f + 1;
+       end if;
+     end if;
+   end process;
+
+  f <= output_f;
+end rtl_1;

data/lib/templates/header.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;

data/lib/templates/memory.vhd

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+
+architecture rtl of example_memory is
+
+  type memory_type is array(0 to 255) of std_logic_vector(7 downto 0);
+  signal mem : memory_type;
+
+begin
+
+  write_p:process(reset_n,clk)
+    if reset_n='0' then
+      for i in 0 to 255 loop
+        mem(i) <= (others=>'0');
+      end loop;
+    elsif rising_edge(clk) then
+      if wr='1' then
+        mem(to_integer(unsigned(addr)) <= datain;
+      end if;
+    end if;
+  end process;
+
+end rtl;

data/lib/templates/procedure.vhd

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+  -- procedure in a process
+  stim:process
+    procedure wait_cycles(n : natural)
+    begin
+      for i in 0 to n-1 loop
+        wait until rising_edge(clk);
+      end loop;
+    end procedure;
+  begin
+    report "starting simulation";
+    wait until reset_n='0';
+
+    wait_cycles(100);
+    report "100 clock cycles elapsed";
+    wait; --forever
+  end process;
+
+end bhv;

data/lib/templates/skeleton.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity example is
+  generic(N : natural := 8)
+  port(
+    reset_n : in std_logic;
+    clk     : in std_logic;
+    enable  : in std_logic;
+
+  );
+end example ;
+
+architecture rtl of example is
+  -- constant CST : natural := 42;
+  -- type regs is array(0 to 10) of ...
+  -- signal x : unsigned(N-1 downto 0);
+begin
+
+  -- synchronous (a.k.a 'clocked') process
+  process(reset_n,clk)
+  begin
+    if reset_n='0' then
+      -- ...
+    elsif rising_edge(clk) then
+      if enable='1' then
+        -- ...
+      end if
+    end if;
+  end process;
+
+  -- conditional assignment
+  z <= a when c1 else
+       b when c2 else
+       d;
+
+  -- component instanciation
+  inst_0: use work.decoder(RTL)
+    generic map(param => 42)
+    port map(
+      reset_n => reset_n,
+      clk     => clk
+    );
+
+end rtl;

data/lib/templates/testbench.vhd

@@ -0,0 +1,58 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb is
+end tb;
+
+architecture bhv of tb is
+  
+  constant HALF_PERIOD : time := 5 ns; --100Mhz
+  signal running : boolean := true;
+  signal clk : std_logic := '0';
+
+begin
+
+  -- clock generator
+  clk <= not clk a after HALF_PERIOD when running else clk;
+
+  -- asynchronous reset
+  reset_n  <= '0','1' after 123 ns;
+
+  -- circuit under test
+  DUT: entity work.my_circuit(RTL)
+    port map(
+      reset_n => reset_n,
+      clk => clk,
+      input_a => a,
+      output_f => f
+    )
+
+  -- stimuli
+  stim:process
+  begin
+    report "starting simulation";
+    wait until reset_n='0';
+
+    report "waiting 100 clock cycles";
+    for i in 0 to 100 loop
+      wait until rising_edge(clk);
+    end loop;
+
+    report "starting test vector";
+    wait until rising_edge(clk);
+    a <= to_unsigned(1,8);
+
+    wait until rising_edge(clk);
+    a <= to_unsigned(2,8);
+
+    report "waiting 100 clock cycles";
+    for i in 0 to 100 loop
+      wait until rising_edge(clk);
+    end loop;
+
+    running <= false;
+    wait; --forever
+  end process;
+
+end bhv;

data/lib/vhdl_helper.rb

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+require 'erb'
+require 'pp'
+# compiler options
+require 'optparse'
+
+class VhdlHelper
+
+  VERSION = "0.1"
+
+  def initialize
+    puts "-- "+"="*60
+    puts "-- VHDL Helper. #{VERSION}. JC Le Lann 2017"
+    puts "-- "+"="*60
+    @date = Time.now.strftime('%c')
+    @options={}
+  end
+
+  def analyze_options args
+    args << "-h" if args.empty?
+
+    opt_parser = OptionParser.new do |opts|
+      opts.banner = "Usage: vhdl_help <keyword>"
+
+      opts.on("-k", "--keywords" ,"list concepts handled for far") do |n|
+        show_keywords
+        abort
+      end
+
+      opts.on("-gen", "generates a VHDL file") do |n|
+        @options[:gen]=true
+      end
+
+      opts.on("--version", "Prints version") do |n|
+        puts VERSION
+        abort
+      end
+
+      opts.on("-h", "--help", "Prints this help") do
+        puts "Provides basic code examples in VHDL"
+        puts opts
+        exit
+      end
+    end
+
+    begin
+      opt_parser.parse!(args)
+      @args=args
+    rescue Exception => e
+      puts e
+      exit
+    end
+  end
+
+  # main method
+  def help
+    @args.each{|arg| generate(arg)}
+  end
+
+  def show_keywords
+    puts "Here are the keywords I know about :"
+    files=__dir__+"../templates/*.vhd"
+    concepts=files.collect{|filename| filename.split("/").last.match(/(.*).vhd/)[1]}
+    concepts.each do |concept|
+      puts "- #{concept}"
+    end
+  end
+
+  def header filename
+    code=[]
+    code << "-- generated : #{@date}"
+    code << "-- design    : #{filename}"
+    code << "-- author    : "
+    code << "-- "+"="*60
+    code.join("\n")
+  end
+
+  def write_file code,filename
+    vhdl=[]
+    vhdl << header(filename)
+    vhdl << code
+    vhdl=vhdl.join("\n")
+    puts vhdl
+    if @options[:gen]
+      File.open(filename,'w'){|f| f.puts vhdl}
+      puts "VHDL code written in : #{filename}"
+    end
+  end
+
+  def generate what
+    filename=__dir__+"/templates/#{what}.vhd"
+    unless File.exist? filename
+      puts "Sorry...I cannot help you concerning '#{what}'"
+    else
+      template=IO.read(filename)
+      renderer = ERB.new(template,nil,'>')
+      code = renderer.result(binding)
+      write_file code,"#{what}.vhd"
+    end
+  end
+
+end
+
+if $PROGRAM_NAME == __FILE__
+  filename=ARGV.first
+  raise "need an argument !" if filename.nil?
+  helper=VhdlHelper.new
+  helper.analyze_options(ARGV)
+  helper.help
+end

metadata

@@ -0,0 +1,56 @@
+--- !ruby/object:Gem::Specification
+name: vhdl_help
+version: !ruby/object:Gem::Version
+  version: '0.1'
+platform: ruby
+authors:
+- Jean-Christophe Le Lann
+autorequire: 
+bindir: bin
+cert_chain: []
+date: 2017-10-16 00:00:00.000000000 Z
+dependencies: []
+description: A simple snippets generator for VHDL
+email: jean-christophe.le_lann@ensta-bretagne.fr
+executables:
+- vhdl_help
+extensions: []
+extra_rdoc_files: []
+files:
+- bin/vhdl_help
+- lib/templates/clock.vhd
+- lib/templates/conversions.vhd
+- lib/templates/counter.vhd
+- lib/templates/entity.vhd
+- lib/templates/fsm.vhd
+- lib/templates/header.vhd
+- lib/templates/memory.vhd
+- lib/templates/procedure.vhd
+- lib/templates/skeleton.vhd
+- lib/templates/testbench.vhd
+- lib/vhdl_helper.rb
+homepage: http://rubygems.org/gems/vhdl_help
+licenses:
+- MIT
+metadata: {}
+post_install_message: 
+rdoc_options: []
+require_paths:
+- lib
+required_ruby_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+required_rubygems_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+requirements: []
+rubyforge_project: 
+rubygems_version: 2.6.12
+signing_key: 
+specification_version: 4
+summary: VHDL Snippets Generator
+test_files: []