vhdl_doctest 0.0.2 → 0.0.3

data/lib/vhdl_doctest.rb

@@ -5,6 +5,7 @@ require "vhdl_doctest/types"
 require "vhdl_doctest/test_file"
 require "vhdl_doctest/test_case"
 require "vhdl_doctest/dut"
+require "vhdl_doctest/test_parser"
 
 module VhdlDoctest
   # Your code goes here...

data/lib/vhdl_doctest/dut.rb

@@ -22,15 +22,15 @@ module VhdlDoctest
       def parse
         entity = @vhdl.match(/entity\s+(.*)\s+is/)[1]
         ports = extract_ports
-        cases = extract_test_cases
+        cases = TestParser.parse(ports, @vhdl)
 
-        [entity, ports, cases.map{ |c| TestCase.new(Hash[ports.zip(c)]) }]
+        [entity, ports, cases]
       end
 
       def extract_ports
         return @ports if @ports
         @ports = []
-        definitions = @vhdl.match(/entity.*is\s+port\s*\((.*)\);\s*end/m)[1]
+        definitions = @vhdl.match(/entity.*is\s+port\s*\((.*?)\);\s*end/m)[1]
         definitions.split("\n").each do |l|
           names, attributes = l.strip.gsub(/;$/, '').split(":")
           next unless attributes
@@ -41,32 +41,6 @@ module VhdlDoctest
         end
         @ports
       end
-
-      def extract_test_cases
-        definitions = @vhdl.match(/-- TEST\n(.*)-- \/TEST/m)[1]
-        header, *body = definitions.split("\n").map { |l| l[3..-1].split("|").map(&:strip) }
-
-        header.each_with_index do |h, idx|
-          radix = 10
-          if h.include?(' ')
-            case h[-1]
-            when 'b'
-              radix = 2
-            when 'h', 'x'
-              radix = 16
-            end
-          end
-          prev = ''
-          body.each do |l|
-            if l[idx].empty?
-              l[idx] = prev
-            else
-              prev = l[idx] = l[idx].to_i(radix)
-            end
-          end
-        end
-        body
-      end
     end
   end
 end

data/lib/vhdl_doctest/test_case.rb

@@ -1,7 +1,12 @@
 module VhdlDoctest
   class TestCase
+    attr_reader :in_mapping, :out_mapping
     def initialize(mapping)
       @in_mapping, @out_mapping = mapping.partition{ |port, _| port.in? }
+      if @in_mapping.find { |_, v| v == :dont_care }
+        raise NotImplementedError.new("Don't care for input value is not supported")
+      end
+      @out_mapping.select!{ |k, v| v != :dont_care }
     end
 
     def to_vhdl
@@ -16,8 +21,12 @@ module VhdlDoctest
     end
 
     def assertion
-      cond = @out_mapping.map { |port, value| port.equation(value) }.join(" and ")
       inputs = @in_mapping.map { |port, value| "#{port.name} = #{value}" }.join(", ")
+      if @out_mapping.empty?
+        warn "There is no assertion for #{inputs}."
+        return ''
+      end
+      cond = @out_mapping.map { |port, value| port.equation(value) }.join(" and ")
       expected = @out_mapping.map { |port, value| "#{port.name} = #{value}" }.join(", ")
       actual = @out_mapping.map { |port, value| "#{port.name} = \" & to_string(#{port.name}) & \"" }.join(", ")
       %Q{assert #{ cond } report "FAILED: #{inputs} expected to #{expected}, but #{actual}" severity warning;}

data/lib/vhdl_doctest/test_parser.rb

@@ -0,0 +1,105 @@
+module VhdlDoctest
+  class OutOfRangeSymbolError < RuntimeError
+    def initialize(port, radix, bad_value)
+      @port, @bad_value = port, bad_value
+
+      @radix = case radix
+               when 2;  'binary'
+               when 10; 'decimal'
+               when 16; 'hex'
+               end
+    end
+
+    def to_s
+      "#@port expects #@radix, but received #@bad_value"
+    end
+  end
+
+  module TestParser
+    extend self
+    def parse(ports, vhdl)
+      names, vectors = extract_values(vhdl)
+      defined_ports = names.map { |name| ports.find { |p| p.name == name } }
+      vectors.map { |v| TestCase.new(Hash[defined_ports.zip(v)]) }
+    end
+
+    private
+    def assert_in_range(port_name, radix, string)
+      symbols = case radix
+                when 2
+                  %w{ 0 1 }
+                when 10
+                  ("0".."9").to_a + %w{ - }
+                when 16
+                  ("0".."9").to_a + ("a".."f").to_a
+                else
+                  []
+                end
+
+      unless string.split(//).all? { |s| symbols.include? s }
+        raise OutOfRangeSymbolError.new(port_name, radix, string)
+      end
+    end
+
+    def remove_comment(line)
+      line.match(/--\s*([^#]*)/)[1]
+    rescue
+      raise "line: #{line} is not formatted correctly"
+    end
+
+    def extract_fields(line)
+      line.split("|").map(&:strip)
+    end
+
+    def test_definitions(vhdl)
+      lines = vhdl.match(/-- TEST\n(.*)-- \/TEST/m)[1].split("\n")
+      lines.partition { |l| l.include? 'alias' }
+    rescue
+      raise "Test definition not found"
+    end
+
+    def radix(attr)
+      if attr
+        case attr[-1]
+        when 'b';      2
+        when 'h', 'x'; 16
+        end
+      else
+        10
+      end
+    end
+
+    def replace_aliases(defs, table)
+      pairs = defs.map { |l| l.match(/alias\s+(.*)\s+(.*)$/)[1..2] }
+      table.each { |l| pairs.each { |p| l.gsub!(p[0], p[1]) } }
+      table
+    end
+
+    def extract_values(vhdl)
+      table = replace_aliases(*test_definitions(vhdl))
+      header, *body = table.map { |l| extract_fields remove_comment l }
+      port_names = []
+
+      header.each_with_index do |h, idx|
+        port_name, attr = h.split(' ', 2)
+        port_names << port_name
+        prev = ''
+        radix = radix(attr)
+        body.each do |l|
+          if l[idx].empty?
+            l[idx] = prev
+          else
+            if l[idx].strip.match(/^-+$/)
+              l[idx] = :dont_care
+            else
+              assert_in_range(port_name, radix, l[idx])
+              l[idx] = l[idx].to_i(radix)
+            end
+            prev = l[idx]
+          end
+        end
+      end
+      [port_names, body]
+    end
+  end
+end

data/lib/vhdl_doctest/types.rb

@@ -11,6 +11,7 @@ module VhdlDoctest
           return result
         end
       end
+      raise "Type for #{str} is not found."
     end
   end
 end

data/lib/vhdl_doctest/types/std_logic.rb

@@ -14,7 +14,7 @@ module VhdlDoctest::Types
     end
 
     def self.parse(str)
-      new if str.strip == 'std_logic'
+      new if str.strip.downcase == 'std_logic'
     end
   end
 end

data/lib/vhdl_doctest/types/std_logic_vector.rb

@@ -13,8 +13,13 @@ module VhdlDoctest::Types
     end
 
     def self.parse(str)
-      if str.strip.match(/\Astd_logic_vector\s*\((\d+)\s+downto\s+0\)\Z/i)
-        new($1.to_i + 1)
+      str = str.strip
+      if str.match(/\Astd_logic_vector/i)
+        if str.strip.match(/\((\d+)\s+downto\s+0\)\Z/i)
+          new($1.to_i + 1)
+        else
+          raise "#{ str } is std_logic_vector, but not 'x downto 0'"
+        end
       end
     end
   end

data/lib/vhdl_doctest/version.rb

@@ -1,3 +1,3 @@
 module VhdlDoctest
-  VERSION = "0.0.2"
+  VERSION = "0.0.3"
 end

data/spec/test_parser_spec.rb

@@ -0,0 +1,165 @@
+require 'spec_helper'
+
+module VhdlDoctest
+  # Expect TestCase to set given hash pairs as stimulus
+  RSpec::Matchers.define :set do |expected|
+    match do |actual|
+      expected.all? { |k, v| actual.in_mapping.
+        find { |port, value| port.name == k.to_s && v == value } }
+    end
+  end
+
+  # Expect TestCase to assert given hash pairs
+  RSpec::Matchers.define :assert do |expected|
+    match do |actual|
+      expected.all? { |k, v| actual.out_mapping.
+        find { |port, value| port.name == k.to_s && (v == nil || v == value) } }
+    end
+  end
+
+  describe TestParser do
+    let(:ports) {[
+        Port.new("a",       :in, Types::StdLogicVector.new(32)),
+        Port.new("b",       :in, Types::StdLogicVector.new(32)),
+        Port.new("control", :in, Types::StdLogicVector.new(3)),
+        Port.new("output",  :out, Types::StdLogicVector.new(32)),
+        Port.new("zero",    :out, Types::StdLogic.new)
+      ]}
+    subject(:cases) { TestParser.parse(ports, input) }
+
+    describe 'header only' do
+      let(:input) { %q{
+-- TEST
+-- a | b | control | output | zero
+-- /TEST
+}}
+      it 'should not fail to parse' do
+        expect(cases).to have(0).items
+      end
+    end
+
+    describe 'single case' do
+      let(:input) { %q{
+-- TEST
+-- a | b | control | output | zero
+-- 3 | 5 | 2       | 8      | 0
+-- /TEST
+}}
+
+      it { should have(1).item }
+      its(:first) { should set(a: 3, b: 5, control: 2) }
+      its(:first) { should assert(output: 8, zero: 0) }
+    end
+
+    describe 'two cases with an empty column' do
+      let(:input) { %q{
+-- TEST
+-- a | b | control | output | zero
+-- 3 | 5 | 2       | 8      | 0
+-- 9 |   | 2       | 14     | 0
+-- /TEST
+}}
+
+      it { should have(2).items }
+      its(:last) { should set(a: 9, b: 5, control: 2) }
+    end
+
+    describe 'field redix specification' do
+      let(:input) { %q{
+-- TEST
+-- a h | b x | control b | output | zero
+-- 10  | 20  | 010       | 8      | 0
+-- /TEST
+}}
+
+      specify { cases.first.should set(a: 16, b: 32, control: 2) }
+    end
+
+    describe 'wrong input for redix' do
+      let(:input) { %q{
+-- TEST
+-- a h | b x | control b | output | zero
+-- 10  | 20  | 012       | 8      | 0
+-- /TEST
+}}
+
+      it { expect{ cases }.to raise_error(OutOfRangeSymbolError, /control.*binary.*012/) }
+    end
+
+    describe 'dont care in assertion' do
+      let(:input) { %q{
+-- TEST
+-- a   | b   | control b | output | zero
+-- 10  | 20  | 010       | 30     | 0
+-- 10  | -10 |           | 0      | -
+-- /TEST
+}}
+
+      specify { cases[0].should assert(output: 30, zero: 0) }
+      specify { cases[1].should set(a: 10, b: -10, control: 2) }
+      specify { cases[1].should_not assert([:zero]) }
+    end
+
+    describe 'dont care in stimuli' do
+      let(:input) { %q{
+-- TEST
+-- a   | b   | control b | output | zero
+-- 10  | -   | 010       | 30     | 0
+-- /TEST
+}}
+
+      specify { expect{ cases }.to raise_error(NotImplementedError) }
+    end
+
+    describe 'all assertions are dont_care' do
+      let(:input) { %q{
+-- TEST
+-- a   | b   | control | output | zero
+-- 10  | -10 | 2       | -      | -
+-- /TEST
+}}
+
+      specify { cases.first.to_vhdl.should_not match /assert/ }
+    end
+
+    describe 'partial specification' do
+      let(:input) { %q{
+-- TEST
+-- a   | b   | control | zero
+-- 10  | -10 | 2       | 1
+-- /TEST
+}}
+
+      specify { cases.first.should assert(zero: 1) }
+      specify { cases.first.should_not assert([:control]) }
+    end
+
+    describe 'comment' do
+      let(:input) { %q{
+-- TEST
+-- a   | b   | control | zero # header
+-- 10  | -10 | 2       | 1    # case1
+-- 10  |     | 2       | 1    # case2 # important
+-- /TEST
+}}
+
+      specify { cases.first.should assert(zero: 1) }
+      specify { cases.last.should assert(zero: 1) }
+    end
+
+    describe 'alias' do
+      let(:input) { %q{
+-- TEST
+-- alias TRUE 1
+-- alias FALSE 0
+-- a   | b   | control | zero
+-- 10  | -10 | 2       | TRUE
+-- 10  | 10  | 2       | FALSE
+-- /TEST
+}}
+
+      specify { cases.first.should assert(zero: 1) }
+      specify { cases.last.should assert(zero: 0) }
+    end
+  end
+end

data/spec/types_spec.rb

@@ -0,0 +1,39 @@
+require 'spec_helper'
+
+module VhdlDoctest
+  describe Types do
+    describe ".parse" do
+      subject { Types.parse(string) }
+
+      describe 'std_logic' do
+        let(:string) { 'std_logic' }
+        it { should be_a Types::StdLogic }
+      end
+
+      describe 'std_logic_vector' do
+        let(:string) { 'std_logic_vector(8 downto 0)' }
+        it { should be_a Types::StdLogicVector }
+      end
+
+      describe 'std_logic_vector, but not in format' do
+        let(:string) { 'std_logic_vector(0 upto 8)' }
+        specify { expect { subject }.to raise_error }
+      end
+
+      describe 'upcase STD_LOGIC' do
+        let(:string) { 'STD_LOGIC' }
+        it { should be_a Types::StdLogic }
+      end
+
+      describe 'upcase STD_LOGIC_VECTOR' do
+        let(:string) { 'STD_LOGIC_VECTOR(2 DOWNTO 0)' }
+        it { should be_a Types::StdLogicVector }
+      end
+
+      describe 'unknown' do
+        let(:string) { 'unkonwn' }
+        specify { expect { subject }.to raise_error }
+      end
+    end
+  end
+end

metadata

@@ -1,7 +1,7 @@
 --- !ruby/object:Gem::Specification
 name: vhdl_doctest
 version: !ruby/object:Gem::Version
-  version: 0.0.2
+  version: 0.0.3
   prerelease: 
 platform: ruby
 authors:
@@ -9,7 +9,7 @@ authors:
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2012-08-23 00:00:00.000000000 Z
+date: 2012-08-30 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rspec
@@ -64,6 +64,7 @@ files:
 - lib/vhdl_doctest/port.rb
 - lib/vhdl_doctest/test_case.rb
 - lib/vhdl_doctest/test_file.rb
+- lib/vhdl_doctest/test_parser.rb
 - lib/vhdl_doctest/test_runner.rb
 - lib/vhdl_doctest/types.rb
 - lib/vhdl_doctest/types/std_logic.rb
@@ -72,7 +73,9 @@ files:
 - spec/dut_spec.rb
 - spec/port_spec.rb
 - spec/spec_helper.rb
+- spec/test_parser_spec.rb
 - spec/test_runner_spec.rb
+- spec/types_spec.rb
 - vhdl_doctest.gemspec
 homepage: ''
 licenses: []
@@ -88,7 +91,7 @@ required_ruby_version: !ruby/object:Gem::Requirement
       version: '0'
       segments:
       - 0
-      hash: 574229357
+      hash: -473783249
 required_rubygems_version: !ruby/object:Gem::Requirement
   none: false
   requirements:
@@ -97,7 +100,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
       version: '0'
       segments:
       - 0
-      hash: 574229357
+      hash: -473783249
 requirements: []
 rubyforge_project: 
 rubygems_version: 1.8.24
@@ -108,4 +111,6 @@ test_files:
 - spec/dut_spec.rb
 - spec/port_spec.rb
 - spec/spec_helper.rb
+- spec/test_parser_spec.rb
 - spec/test_runner_spec.rb
+- spec/types_spec.rb