vhdl_doctest 0.0.1

data/.gitignore

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+*.gem
+*.rbc
+.bundle
+.config
+.yardoc
+Gemfile.lock
+InstalledFiles
+_yardoc
+coverage
+doc/
+lib/bundler/man
+pkg
+rdoc
+spec/reports
+test/tmp
+test/version_tmp
+tmp
+.rspec

data/Gemfile

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+source 'https://rubygems.org'
+
+# Specify your gem's dependencies in vhdl_doctest.gemspec
+gemspec
+
+group :guard do
+  gem 'guard-rspec'
+  gem 'guard-notifier-git_auto_commit'
+end

data/Guardfile

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+# A sample Guardfile
+# More info at https://github.com/guard/guard#readme
+
+require 'guard-notifier-git_auto_commit'
+
+guard 'rspec', :version => 2 do
+  watch(%r{^spec/.+_spec\.rb$})
+  watch(%r{^lib/vhdl_doctest/(.+)\.rb$})     { |m| "spec/#{m[1]}_spec.rb" }
+  watch('spec/spec_helper.rb')  { "spec" }
+end
+
+notification :git_auto_commit
+notification :notifysend

data/LICENSE

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+Copyright (c) 2012 tomykaira
+
+MIT License
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be
+included in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

data/README.md

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+# VhdlDoctest
+
+This is a simple doctest-like test runner for VHDL.
+
+## Dependency
+
+This uses GHDL for compiling and running VHDL.  Please download from [GHDL Main/Home Page](http://ghdl.free.fr), and install.
+
+## Installation
+
+    $ gem install vhdl_doctest
+
+Install GHDL from [GHDL Main/Home Page](http://ghdl.free.fr).
+
+## Usage
+
+White parameterized test in your VHDL file.  Current version is only for combination circuit.
+
+    entity alu is
+    
+      port (
+        a, b    : in  std_logic_vector(31 downto 0);
+        control : in  std_logic_vector(2 downto 0);
+        output  : out std_logic_vector(31 downto 0);
+        zero    : out std_logic);
+    
+    end alu;
+
+For this module, you can write the following test in the same file.  You should not miss `-- TEST` and `-- /TEST`.  Space after `--` is necessary.
+
+    -- TEST
+    -- a  |b   |control b|output|zero
+    -- 18 |9   |000      |0     |1
+    --    |    |001      |27    |0
+    --    |    |010      |27    |0
+    --    |    |110      |9     |0
+    --    |    |111      |0     |1
+    -- 18 |18  |111      |0     |1
+    -- 18 |19  |         |1     |0
+    -- 18 |100 |         |1     |0
+    -- /TEST
+
+- Each field should be separated with `|`.
+- If the header column includes space followed by "b" or "h" or "x", that column's values are interpreted as binary (for "b") or "hex" (for "h" or "x").  The default interpretation is decimal.
+- Blank field inherits the value of the previous row.
+- Edge cases are not supported.  If you find out a buggy case, tell me through [ITS in github](https://github.com/tomykaira/vhdl_doctest/issues).
+
+This generates code like this.
+
+    a <= "00000000000000000000000000010010";
+    b <= "00000000000000000000000000001001";
+    control <= "000";wait for 10 ns;
+    assert output = "00000000000000000000000000000000" and zero = '1' report "FAILED: a = 18, b = 9, control = 0 expected to output = 0, zero = 1, but output = " & to_string(output) & ", zero = " & to_string(zero) & "" severity warning;
+
+CAUTION: a file can have only one TEST block.
+
+## Issues And Features
+
+If you found a bug (or unexpected movement), let me know.  Please attach your vhd file (as far as possible), and describe your intention precisely.
+
+Any feature request is welcome.  I appreciate if it have an example, or a test case.
+
+## Contributing
+
+1. Fork it
+2. Create your feature branch (`git checkout -b my-new-feature`)
+3. Commit your changes (`git commit -am 'Added some feature'`)
+4. Write tests with rspec for your changes
+5. Push to the branch (`git push origin my-new-feature`)
+6. Create new Pull Request

data/Rakefile

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+#!/usr/bin/env rake
+require "bundler/gem_tasks"

data/bin/vhdl_doctest

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+#!/usr/bin/env ruby
+# encoding: UTF-8
+
+unless ARGV.size == 1 && File.file?(ARGV[0])
+  puts "Usage: vhdl_doctest VHDL_PATH"
+  exit 1
+end
+
+# resolve bin path, ignoring symlinks
+require "pathname"
+bin_file = Pathname.new(__FILE__).realpath
+
+# add self to libpath
+$:.unshift File.expand_path("../../lib", bin_file)
+
+require "vhdl_doctest"
+test = VhdlDoctest::DUT.parse(ARGV[0]).test_file
+
+VhdlDoctest::TestRunner.new(STDOUT, ARGV[0], test).run

data/examples/alu.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+-- TEST
+-- a  |b   |control b|output|zero
+-- 18 |9   |000      |0     |1
+--    |    |001      |27    |0
+--    |    |010      |27    |0
+--    |    |110      |9     |0
+--    |    |111      |0     |1
+-- 18 |18  |111      |0     |1
+-- 18 |19  |         |1     |0
+-- 18 |100 |         |1     |0
+-- /TEST
+
+entity alu is
+
+  port (
+    a, b    : in  std_logic_vector(31 downto 0);
+    control : in  std_logic_vector(2 downto 0);
+    output  : out std_logic_vector(31 downto 0);
+    zero    : out std_logic);
+
+end alu;
+
+architecture behave of alu is
+
+  signal bb : std_logic_vector(31 downto 0);
+  signal c : std_logic;
+  signal o0, o1, o2, o3 : std_logic_vector(31 downto 0);
+
+  signal out_buf : std_logic_vector(31 downto 0);
+
+begin  -- behave
+
+  c <= control(2);
+
+  bb <= not b when control(2) = '1' else b;
+
+  o0 <= a and bb;
+  o1 <= a or b;
+  o2 <= a + bb + c;
+  o3 <= x"0000000" & "000" & o2(31);
+
+  out_buf <= o0 when control(1 downto 0) = "00" else
+             o1 when control(1 downto 0) = "01" else
+             o2 when control(1 downto 0) = "10" else
+             o3 when control(1 downto 0) = "11";
+
+  output <= out_buf;
+  zero <= '1' when out_buf = x"00000000" else '0';
+
+end behave;

data/lib/vhdl_doctest/dut.rb

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+module VhdlDoctest
+  class DUT
+    def self.parse(path)
+      entity, ports, cases = DoctestParser.new(path).parse
+      new(entity, ports, cases)
+    end
+
+    attr_accessor :entity, :ports, :cases
+    def initialize(entity, ports, cases)
+      @entity, @ports, @cases = entity, ports, cases
+    end
+
+    def test_file
+      TestFile.new(@entity, @ports, @cases)
+    end
+
+    class DoctestParser
+      def initialize(path)
+        @vhdl = File.read(path)
+      end
+
+      def parse
+        entity = @vhdl.match(/entity\s+(.*)\s+is/)[1]
+        ports = extract_ports
+        cases = extract_test_cases
+
+        [entity, ports, cases.map{ |c| TestCase.new(Hash[ports.zip(c)]) }]
+      end
+
+      def extract_ports
+        return @ports if @ports
+        @ports = []
+        definitions = @vhdl.match(/entity.*is\s+port\s*\((.*)\);\s*end/m)[1]
+        definitions.split("\n").each do |l|
+          names, attributes = l.strip.gsub(/;$/, '').split(":")
+          next unless attributes
+          destination, type = attributes.strip.split(' ', 2)
+          names.split(',').each do |name|
+            @ports << Port.new(name.strip, destination.to_sym, VhdlDoctest::Types.parse(type))
+          end
+        end
+        @ports
+      end
+
+      def extract_test_cases
+        definitions = @vhdl.match(/-- TEST\n(.*)-- \/TEST/m)[1]
+        header, *body = definitions.split("\n").map { |l| l[3..-1].split("|").map(&:strip) }
+
+        header.each_with_index do |h, idx|
+          radix = 10
+          if h.include?(' ')
+            case h[-1]
+            when 'b'
+              radix = 2
+            when 'h', 'x'
+              radix = 16
+            end
+          end
+          prev = ''
+          body.each do |l|
+            if l[idx].empty?
+              l[idx] = prev
+            else
+              prev = l[idx] = l[idx].to_i(radix)
+            end
+          end
+        end
+        body
+      end
+    end
+  end
+end

data/lib/vhdl_doctest/port.rb

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+module VhdlDoctest
+  class Port
+    attr_reader :name
+
+    def initialize(name, direction, type)
+      @name, @direction, @type = name, direction, type
+    end
+
+    def port_definition
+      "#@name : #@direction #{@type.to_vhdl}"
+    end
+
+    def signal_definition
+      "signal #@name : #{@type.to_vhdl};"
+    end
+
+    def mapping
+      "#@name => #@name"
+    end
+
+    def assignment(value)
+      "#@name <= #{@type.format(value)};"
+    end
+
+    def equation(value)
+      "#@name = #{@type.format(value)}"
+    end
+
+    def in?
+      @direction == :in
+    end
+  end
+end

data/lib/vhdl_doctest/test_case.rb

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+module VhdlDoctest
+  class TestCase
+    def initialize(mapping)
+      @in_mapping, @out_mapping = mapping.partition{ |port, _| port.in? }
+    end
+
+    def to_vhdl
+      stimuli.join("\n") + "wait for 10 ns;\n" + assertion
+    end
+
+    private
+    def stimuli
+      @in_mapping.map do |port, value|
+        port.assignment(value)
+      end
+    end
+
+    def assertion
+      cond = @out_mapping.map { |port, value| port.equation(value) }.join(" and ")
+      inputs = @in_mapping.map { |port, value| "#{port.name} = #{value}" }.join(", ")
+      expected = @out_mapping.map { |port, value| "#{port.name} = #{value}" }.join(", ")
+      actual = @out_mapping.map { |port, value| "#{port.name} = \" & to_string(#{port.name}) & \"" }.join(", ")
+      %Q{assert #{ cond } report "FAILED: #{inputs} expected to #{expected}, but #{actual}" severity warning;}
+    end
+  end
+end

data/lib/vhdl_doctest/test_file.rb

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+module VhdlDoctest
+  class TestFile
+    attr_reader :cases
+
+    def initialize(dut_entity, ports, cases)
+      @dut_entity = dut_entity
+      @ports = ports
+      @cases = cases
+    end
+
+    def test_name
+      "testbench_" + @dut_entity
+    end
+
+    def path
+      if @path
+        @path
+      else
+        raise "This test file is not yet instantiated"
+      end
+    end
+
+    def create(dir)
+      @path = File.join(dir, test_name + ".vhd")
+      File.open(@path, 'w') do |f|
+        f << header + "\n\n"
+        f << "architecture sim of #{test_name} is\n"
+        f << dut_component
+        f << signals
+        f << UTILS
+        f << "begin"
+        f << dut_instantiation
+        f << testcases
+        f << "end sim;\n"
+      end
+    end
+
+    private
+    def header
+      %Q{-- This file is generated by vhdl_doctest
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity #{ test_name } is
+end #{ test_name };
+}
+    end
+
+    def dut_component
+      str = "component #{@dut_entity} port("
+      str << @ports.map { |port| port.port_definition }.join(";\n")
+      str << ");\nend component;"
+    end
+
+    def signals
+      @ports.map(&:signal_definition).join("\n")
+    end
+
+    def dut_instantiation
+      %Q{
+dut : #{ @dut_entity } port map (
+  #{ @ports.map(&:mapping).join(", ") }
+);
+}
+    end
+
+    def testcases
+      %Q{
+  process begin
+  #{@cases.map(&:to_vhdl).join("\n\n")}
+  wait;
+  end process;
+ }
+    end
+
+    UTILS = %Q{
+  function to_string (value : STD_ULOGIC) return STRING;
+  function to_string (value : STD_ULOGIC_VECTOR) return STRING;
+  function to_string (value : STD_LOGIC_VECTOR) return STRING;
+
+  alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
+  alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
+  function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
+  alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
+  function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
+  alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
+
+  alias TO_BSTRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
+  alias TO_BINARY_STRING is TO_STRING [STD_LOGIC_VECTOR return STRING];
+  function TO_OSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
+  alias TO_OCTAL_STRING is TO_OSTRING [STD_LOGIC_VECTOR return STRING];
+  function TO_HSTRING (VALUE : STD_LOGIC_VECTOR) return STRING;
+  alias TO_HEX_STRING is TO_HSTRING [STD_LOGIC_VECTOR return STRING];
+
+  type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
+  constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
+  constant NUS  : STRING(2 to 1) := (others => ' ');     -- null STRING
+
+  -----------------------------------------------------------------------------
+  -- New string functions for vhdl-200x fast track
+  -----------------------------------------------------------------------------
+  function to_string (value     : STD_ULOGIC) return STRING is
+    variable result : STRING (1 to 1);
+  begin
+    result (1) := MVL9_to_char (value);
+    return result;
+  end function to_string;
+  -------------------------------------------------------------------
+  -- TO_STRING (an alias called "to_bstring" is provide)
+  -------------------------------------------------------------------
+  function to_string (value     : STD_ULOGIC_VECTOR) return STRING is
+    alias ivalue    : STD_ULOGIC_VECTOR(1 to value'length) is value;
+    variable result : STRING(1 to value'length);
+  begin
+    if value'length < 1 then
+      return NUS;
+    else
+      for i in ivalue'range loop
+        result(i) := MVL9_to_char(iValue(i));
+      end loop;
+      return result;
+    end if;
+  end function to_string;
+
+  -------------------------------------------------------------------
+  -- TO_HSTRING
+  -------------------------------------------------------------------
+  function to_hstring (value     : STD_ULOGIC_VECTOR) return STRING is
+    constant ne     : INTEGER := (value'length+3)/4;
+    variable pad    : STD_ULOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
+    variable ivalue : STD_ULOGIC_VECTOR(0 to ne*4 - 1);
+    variable result : STRING(1 to ne);
+    variable quad   : STD_ULOGIC_VECTOR(0 to 3);
+  begin
+    if value'length < 1 then
+      return NUS;
+    else
+      if value (value'left) = 'Z' then
+        pad := (others => 'Z');
+      else
+        pad := (others => '0');
+      end if;
+      ivalue := pad & value;
+      for i in 0 to ne-1 loop
+        quad := To_X01Z(ivalue(4*i to 4*i+3));
+        case quad is
+          when x"0"   => result(i+1) := '0';
+          when x"1"   => result(i+1) := '1';
+          when x"2"   => result(i+1) := '2';
+          when x"3"   => result(i+1) := '3';
+          when x"4"   => result(i+1) := '4';
+          when x"5"   => result(i+1) := '5';
+          when x"6"   => result(i+1) := '6';
+          when x"7"   => result(i+1) := '7';
+          when x"8"   => result(i+1) := '8';
+          when x"9"   => result(i+1) := '9';
+          when x"A"   => result(i+1) := 'A';
+          when x"B"   => result(i+1) := 'B';
+          when x"C"   => result(i+1) := 'C';
+          when x"D"   => result(i+1) := 'D';
+          when x"E"   => result(i+1) := 'E';
+          when x"F"   => result(i+1) := 'F';
+          when "ZZZZ" => result(i+1) := 'Z';
+          when others => result(i+1) := 'X';
+        end case;
+      end loop;
+      return result;
+    end if;
+  end function to_hstring;
+
+  -------------------------------------------------------------------
+  -- TO_OSTRING
+  -------------------------------------------------------------------
+  function to_ostring (value     : STD_ULOGIC_VECTOR) return STRING is
+    constant ne     : INTEGER := (value'length+2)/3;
+    variable pad    : STD_ULOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
+    variable ivalue : STD_ULOGIC_VECTOR(0 to ne*3 - 1);
+    variable result : STRING(1 to ne);
+    variable tri    : STD_ULOGIC_VECTOR(0 to 2);
+  begin
+    if value'length < 1 then
+      return NUS;
+    else
+      if value (value'left) = 'Z' then
+        pad := (others => 'Z');
+      else
+        pad := (others => '0');
+      end if;
+      ivalue := pad & value;
+      for i in 0 to ne-1 loop
+        tri := To_X01Z(ivalue(3*i to 3*i+2));
+        case tri is
+          when o"0"   => result(i+1) := '0';
+          when o"1"   => result(i+1) := '1';
+          when o"2"   => result(i+1) := '2';
+          when o"3"   => result(i+1) := '3';
+          when o"4"   => result(i+1) := '4';
+          when o"5"   => result(i+1) := '5';
+          when o"6"   => result(i+1) := '6';
+          when o"7"   => result(i+1) := '7';
+          when "ZZZ"  => result(i+1) := 'Z';
+          when others => result(i+1) := 'X';
+        end case;
+      end loop;
+      return result;
+    end if;
+  end function to_ostring;
+
+  function to_string (value     : STD_LOGIC_VECTOR) return STRING is
+  begin
+    return to_string (to_stdulogicvector (value));
+  end function to_string;
+
+  function to_hstring (value     : STD_LOGIC_VECTOR) return STRING is
+  begin
+    return to_hstring (to_stdulogicvector (value));
+  end function to_hstring;
+
+  function to_ostring (value     : STD_LOGIC_VECTOR) return STRING  is
+  begin
+    return to_ostring (to_stdulogicvector (value));
+  end function to_ostring;
+}
+  end
+end

data/lib/vhdl_doctest/test_runner.rb

@@ -0,0 +1,47 @@
+module VhdlDoctest
+  class TestRunner
+    def initialize(out, dut_path, test_file)
+      @out = out
+      @dut_path = File.expand_path(dut_path)
+      @test_file = test_file
+    end
+
+    def run
+      create_files
+      run_test
+      report_result
+    end
+
+    private
+    def create_files
+      require 'tmpdir'
+      @dir = Dir.mktmpdir
+      @test_file.create(@dir)
+    end
+
+    def run_test
+      @result = ""
+
+      sh = File.join(@dir, "run.sh")
+      File.open(sh, 'w') do |f|
+        f << "#!/bin/sh -e\n\n"
+        f << "cd #{@dir}\n"
+        f << "ghdl -a --ieee=synopsys -fexplicit --warn-default-binding --warn-binding --warn-library --warn-body --warn-specs --warn-unused #{@dut_path} #{@test_file.path}\n"
+        f << "ghdl -e -Plibs/unisim --ieee=synopsys -fexplicit #{@test_file.test_name}\n"
+        f << "ghdl -r #{@test_file.test_name} --vcd=out.vcd --stop-time=10ms\n"
+      end
+
+      IO.popen("sh #{sh} 2>&1") do |f|
+        output = f.read
+        @result << output
+        @out << output
+      end
+    end
+
+    def report_result
+      failures = @result.split("\n").select { |l| l.include?('FAILED') }
+      @out << "\n#{@test_file.cases.size} examples, #{failures.size} failures\n"
+      @out << "\nTest directory: #{@dir}\n"
+    end
+  end
+end

data/lib/vhdl_doctest/types/std_logic.rb

@@ -0,0 +1,20 @@
+module VhdlDoctest::Types
+  class StdLogic
+    def to_vhdl
+      'std_logic'
+    end
+
+    def format(v)
+      if [0, 1].include? v.to_i
+        %Q{'#{v.to_i}'}
+      else
+        # TODO: define error class
+        raise "unacceptable value error #{v}"
+      end
+    end
+
+    def self.parse(str)
+      new if str.strip == 'std_logic'
+    end
+  end
+end

data/lib/vhdl_doctest/types/std_logic_vector.rb

@@ -0,0 +1,21 @@
+module VhdlDoctest::Types
+  class StdLogicVector
+    def initialize(length)
+      @length = length
+    end
+
+    def to_vhdl
+      "std_logic_vector(#{@length-1} downto 0)"
+    end
+
+    def format(v)
+      '"' + v.to_s(2).rjust(@length, '0')+ '"'
+    end
+
+    def self.parse(str)
+      if str.strip.match(/\Astd_logic_vector\s*\((\d+)\s+downto\s+0\)\Z/i)
+        new($1.to_i + 1)
+      end
+    end
+  end
+end

data/lib/vhdl_doctest/types.rb

@@ -0,0 +1,16 @@
+require 'vhdl_doctest/types/std_logic'
+require 'vhdl_doctest/types/std_logic_vector'
+
+module VhdlDoctest
+  module Types
+    def self.parse(str)
+      Types.constants.each do |c|
+        klass = const_get("#{c}")
+        next unless klass.respond_to?(:parse)
+        if result = klass.parse(str)
+          return result
+        end
+      end
+    end
+  end
+end

data/lib/vhdl_doctest/version.rb

@@ -0,0 +1,3 @@
+module VhdlDoctest
+  VERSION = "0.0.1"
+end

data/lib/vhdl_doctest.rb

@@ -0,0 +1,11 @@
+require "vhdl_doctest/version"
+require "vhdl_doctest/test_runner"
+require "vhdl_doctest/port"
+require "vhdl_doctest/types"
+require "vhdl_doctest/test_file"
+require "vhdl_doctest/test_case"
+require "vhdl_doctest/dut"
+
+module VhdlDoctest
+  # Your code goes here...
+end

data/spec/dut_spec.rb

@@ -0,0 +1,25 @@
+require 'spec_helper'
+
+module VhdlDoctest
+  sample_vhdl = 'examples/alu.vhd'
+  describe DUT do
+    subject { DUT.parse(sample_vhdl) }
+
+    its(:entity) { should == "alu" }
+    it { should have(5).ports }
+    it { should have(8).cases }
+
+    its('test_file.test_name') { should == 'testbench_alu' }
+    its(:test_file) { should have(8).cases }
+  end
+
+  describe DUT::DoctestParser do
+    describe 'ports' do
+      subject { described_class.new(sample_vhdl).extract_ports }
+
+      it { should have(5).items }
+      its('first.port_definition') { should == "a : in std_logic_vector(31 downto 0)" }
+      its('last.port_definition') { should == "zero : out std_logic" }
+    end
+  end
+end

data/spec/port_spec.rb

@@ -0,0 +1,35 @@
+require 'spec_helper'
+
+module VhdlDoctest
+  describe Port do
+    subject { Port.new('test', :in, Types::StdLogic.new) }
+
+    its(:mapping){ should == "test => test" }
+
+    describe '#assignment' do
+      subject { port.assignment(value) }
+
+      describe 'std_logic' do
+        let(:port) { Port.new('test', :in, Types::StdLogic.new) }
+
+        context 'value = 0' do
+          let(:value) { 0 }
+          it { should == "test <= '0';" }
+        end
+
+        context 'value = 1' do
+          let(:value) { 1 }
+          it { should == "test <= '1';" }
+        end
+      end
+      describe 'std_logic_vector(8)' do
+        let(:port) { Port.new('test', :in, Types::StdLogicVector.new(8)) }
+
+        context 'value = 0' do
+          let(:value) { 0 }
+          it { should == 'test <= "00000000";' }
+        end
+      end
+    end
+  end
+end

data/spec/spec_helper.rb

@@ -0,0 +1,19 @@
+# This file was generated by the `rspec --init` command. Conventionally, all
+# specs live under a `spec` directory, which RSpec adds to the `$LOAD_PATH`.
+# Require this file using `require "spec_helper"` to ensure that it is only
+# loaded once.
+#
+# See http://rubydoc.info/gems/rspec-core/RSpec/Core/Configuration
+
+require 'vhdl_doctest'
+RSpec.configure do |config|
+  config.treat_symbols_as_metadata_keys_with_true_values = true
+  config.run_all_when_everything_filtered = true
+  config.filter_run :focus
+
+  # Run specs in random order to surface order dependencies. If you find an
+  # order dependency and want to debug it, you can fix the order by providing
+  # the seed, which is printed after each run.
+  #     --seed 1234
+  config.order = 'random'
+end

data/spec/test_runner_spec.rb

@@ -0,0 +1,46 @@
+require 'spec_helper'
+
+module VhdlDoctest
+  describe TestRunner do
+    let(:dut_file) { "examples/alu.vhd/" }
+    describe "#run" do
+      context "3 successful examples" do
+        let(:out) { StringIO.new }
+        let(:file) { test_file([[18, 9, 0, 0, 1], [18, 18, 7, 0, 1], [18, 19, 7, 1, 0]]) }
+        subject { out.rewind; out.read }
+        before { described_class.new(out, dut_file, file).run }
+
+        it { should match "3 examples, 0 failures" }
+      end
+
+      context "1 successful examples" do
+        let(:out) { StringIO.new }
+        let(:file) { test_file([[18, 9, 0, 0, 1]]) }
+        subject { out.rewind; out.read }
+        before { described_class.new(out, dut_file, file).run }
+
+        it { should match "1 examples, 0 failures" }
+      end
+
+      context "1 failing examples" do
+        let(:out) { StringIO.new }
+        let(:file) { test_file([[18, 9, 0, 0, 0]]) }
+        subject { out.rewind; out.read }
+        before { described_class.new(out, dut_file, file).run }
+
+        it { should match "1 examples, 1 failures" }
+      end
+    end
+
+    def test_file(cases)
+      ports = [
+        Port.new("a",       :in, Types::StdLogicVector.new(32)),
+        Port.new("b",       :in, Types::StdLogicVector.new(32)),
+        Port.new("control", :in, Types::StdLogicVector.new(3)),
+        Port.new("output",  :out, Types::StdLogicVector.new(32)),
+        Port.new("zero",    :out, Types::StdLogic.new)
+      ]
+      TestFile.new("alu", ports, cases.map{ |c| TestCase.new(Hash[ports.zip(c)]) })
+    end
+  end
+end

data/vhdl_doctest.gemspec

@@ -0,0 +1,20 @@
+# -*- encoding: utf-8 -*-
+require File.expand_path('../lib/vhdl_doctest/version', __FILE__)
+
+Gem::Specification.new do |gem|
+  gem.authors       = ["tomykaira"]
+  gem.email         = ["tomykaira@gmail.com"]
+  gem.description   = %q{Run parameterized test for VHDL written in doctest-like format.}
+  gem.summary       = %q{Run parameterized test for VHDL written in doctest-like format.}
+  gem.homepage      = ""
+
+  gem.files         = `git ls-files`.split($\)
+  gem.executables   = gem.files.grep(%r{^bin/}).map{ |f| File.basename(f) }
+  gem.test_files    = gem.files.grep(%r{^(test|spec|features)/})
+  gem.name          = "vhdl_doctest"
+  gem.require_paths = ["lib"]
+  gem.version       = VhdlDoctest::VERSION
+
+  gem.add_development_dependency 'rspec', '~> 2.11'
+  gem.add_development_dependency 'rake'
+end

metadata

@@ -0,0 +1,111 @@
+--- !ruby/object:Gem::Specification
+name: vhdl_doctest
+version: !ruby/object:Gem::Version
+  version: 0.0.1
+  prerelease: 
+platform: ruby
+authors:
+- tomykaira
+autorequire: 
+bindir: bin
+cert_chain: []
+date: 2012-08-23 00:00:00.000000000 Z
+dependencies:
+- !ruby/object:Gem::Dependency
+  name: rspec
+  requirement: !ruby/object:Gem::Requirement
+    none: false
+    requirements:
+    - - ~>
+      - !ruby/object:Gem::Version
+        version: '2.11'
+  type: :development
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    none: false
+    requirements:
+    - - ~>
+      - !ruby/object:Gem::Version
+        version: '2.11'
+- !ruby/object:Gem::Dependency
+  name: rake
+  requirement: !ruby/object:Gem::Requirement
+    none: false
+    requirements:
+    - - ! '>='
+      - !ruby/object:Gem::Version
+        version: '0'
+  type: :development
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    none: false
+    requirements:
+    - - ! '>='
+      - !ruby/object:Gem::Version
+        version: '0'
+description: Run parameterized test for VHDL written in doctest-like format.
+email:
+- tomykaira@gmail.com
+executables:
+- vhdl_doctest
+extensions: []
+extra_rdoc_files: []
+files:
+- .gitignore
+- Gemfile
+- Guardfile
+- LICENSE
+- README.md
+- Rakefile
+- bin/vhdl_doctest
+- examples/alu.vhd
+- lib/vhdl_doctest.rb
+- lib/vhdl_doctest/dut.rb
+- lib/vhdl_doctest/port.rb
+- lib/vhdl_doctest/test_case.rb
+- lib/vhdl_doctest/test_file.rb
+- lib/vhdl_doctest/test_runner.rb
+- lib/vhdl_doctest/types.rb
+- lib/vhdl_doctest/types/std_logic.rb
+- lib/vhdl_doctest/types/std_logic_vector.rb
+- lib/vhdl_doctest/version.rb
+- spec/dut_spec.rb
+- spec/port_spec.rb
+- spec/spec_helper.rb
+- spec/test_runner_spec.rb
+- vhdl_doctest.gemspec
+homepage: ''
+licenses: []
+post_install_message: 
+rdoc_options: []
+require_paths:
+- lib
+required_ruby_version: !ruby/object:Gem::Requirement
+  none: false
+  requirements:
+  - - ! '>='
+    - !ruby/object:Gem::Version
+      version: '0'
+      segments:
+      - 0
+      hash: 39814003
+required_rubygems_version: !ruby/object:Gem::Requirement
+  none: false
+  requirements:
+  - - ! '>='
+    - !ruby/object:Gem::Version
+      version: '0'
+      segments:
+      - 0
+      hash: 39814003
+requirements: []
+rubyforge_project: 
+rubygems_version: 1.8.24
+signing_key: 
+specification_version: 3
+summary: Run parameterized test for VHDL written in doctest-like format.
+test_files:
+- spec/dut_spec.rb
+- spec/port_spec.rb
+- spec/spec_helper.rb
+- spec/test_runner_spec.rb