vertigo_vhdl 0.8.6 → 0.8.7

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 67916f8023b4daaaa9e3b2ee7405a880bbcd71ad70733b087ec4e0d1f63ccc2d
-  data.tar.gz: df9ae80fb38ea82afbfa7bc79d128448dc979342770a28493061463cae623d3e
+  metadata.gz: eb22a79a9fe6c4cfeeb9293cea9e7c08d0b70c6a220261f00476fa79200cd930
+  data.tar.gz: a6e30af8d8f623f1fe4f411b845f31429637a377879443be9f9231620315ece1
 SHA512:
-  metadata.gz: a13be7a1c2bfdd4ed210bceab2231700f409f1e1b274073631629bf20909298fe0989a2485a14b269ecfb5058c6c3df37a31ba9f880a8e7a7fd261e3b0524475
-  data.tar.gz: ec0ae03dfae2b65a5a7f7a03aacc80e43cac31517d20ec0668b0e7542894ca4335f6273f62aacfc4fa68fef3e2c3d4983c1dd716f2857212715112b73ae93e90
+  metadata.gz: de3f891d744486704a4b253a00e9a19da00e1ba8a0d1716729a97ed21f010f3f41dfc1cb92824d6112c4c3256d5b61bd4478d31bec693d89c4df749c74b2715d
+  data.tar.gz: bf8e2e13ddfbc9f02d1037cd9bf50450643a0e17a88f9f451c09656fb294ce5508e5abaa5c4b48212b79b9c480621989f9db797c23a373c80acc52ea363c448c

data/lib/vertigo/tb_generator.rb

@@ -1,9 +1,12 @@
 module Vertigo
 
   class TestBenchGenerator
+
     attr_accessor :ast
     attr_accessor :entity,:arch
     attr_accessor :clk,:rst
+    attr_accessor :options
+
     def initialize options={}
       @options=options
       @supplemental_libs_h=options[:supplemental_libs_h]||{}
@@ -17,7 +20,8 @@ module Vertigo
       @tb_name=@entity_name+"_tb"
       tb_filename=@tb_name+".vhd"
       File.open(tb_filename,'w'){|f| f.puts vhdl_tb}
-      puts "=> generated testbench : #{tb_filename}"
+      puts "=> generated testbench : #{tb_filename}" unless options[:mute]
+      return tb_filename
     end
 
     def line n=80
@@ -157,27 +161,27 @@ module Vertigo
         puts msg="ERROR : no entity found"
         raise msg
       end
-      puts "=> found entity '#{entity.name.str}'"
+      puts "=> found entity '#{entity.name.str}'" unless options[:mute]
       @arch=ast.design_units.find{|du| du.is_a? Architecture}
       if @arch.nil?
         puts msg="ERROR : no architecture found"
         raise msg
       end
 
-      puts "=> found architecture '#{arch.name.str}'"
+      puts "=> found architecture '#{arch.name.str}'" unless options[:mute]
       @entity_name=@entity.name.str
       @arch_name=@arch.name.str
       [@entity,@arch]
     end
 
     def detecting_clk_and_reset entity_arch
-      puts "=> detecting clock and reset"
+      puts "=> detecting clock and reset" unless options[:mute]
       entity,arch=entity_arch
       inputs=entity.ports.select{|port| port.is_a?(Input)}
       @clk = inputs.sort_by{|input| levenshtein_distance(input.name.str,"clk")}.first
       @rst = inputs.sort_by{|input| levenshtein_distance(input.name.str,"reset_n")}.first
-      puts "\t-most probable clk   : #{@clk.name.str}"
-      puts "\t-most probable reset : #{@rst.name.str}"
+      puts "\t-most probable clk   : #{@clk.name.str}" unless options[:mute]
+      puts "\t-most probable reset : #{@rst.name.str}" unless options[:mute]
       @max_length_str=entity.ports.map{|port| port.name.str.size}.max
       @excluded=[@clk,@rst]
       @reset_name=@rst.name.str

data/lib/vertigo/version.rb

@@ -1,3 +1,3 @@
 module Vertigo
-  VERSION="0.8.6"
+  VERSION="0.8.7"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: vertigo_vhdl
 version: !ruby/object:Gem::Version
-  version: 0.8.6
+  version: 0.8.7
 platform: ruby
 authors:
 - Jean-Christophe Le Lann
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2021-03-23 00:00:00.000000000 Z
+date: 2021-04-01 00:00:00.000000000 Z
 dependencies: []
 description: A Ruby handwritten VHDL parser and utilities
 email: jean-christophe.le_lann@ensta-bretagne.fr