vertigo_vhdl 0.8.5 → 0.8.6
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/vertigo/tb_generator.rb +9 -0
- data/lib/vertigo/version.rb +1 -1
- metadata +2 -2
checksums.yaml
CHANGED
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@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 67916f8023b4daaaa9e3b2ee7405a880bbcd71ad70733b087ec4e0d1f63ccc2d
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data.tar.gz: df9ae80fb38ea82afbfa7bc79d128448dc979342770a28493061463cae623d3e
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: a13be7a1c2bfdd4ed210bceab2231700f409f1e1b274073631629bf20909298fe0989a2485a14b269ecfb5058c6c3df37a31ba9f880a8e7a7fd261e3b0524475
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7
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data.tar.gz: ec0ae03dfae2b65a5a7f7a03aacc80e43cac31517d20ec0668b0e7542894ca4335f6273f62aacfc4fa68fef3e2c3d4983c1dd716f2857212715112b73ae93e90
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data/lib/vertigo/tb_generator.rb
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@@ -57,6 +57,15 @@ module Vertigo
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code << "end loop;"
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code.indent=2
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code << "end procedure;"
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code.newline
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code << "procedure toggle(signal s : inout std_logic) is"
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code << "begin"
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code << " wait until rising_edge(clk);"
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code << " s <=not(s);"
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code << " wait until rising_edge(clk);"
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code << " s <=not(s);"
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code << "end procedure;"
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code.newline
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@entity.ports.each do |port|
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port_name=port.name.str.ljust(@max_length_str)
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port_type=port.type.str
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data/lib/vertigo/version.rb
CHANGED
metadata
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@@ -1,14 +1,14 @@
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--- !ruby/object:Gem::Specification
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name: vertigo_vhdl
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version: !ruby/object:Gem::Version
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version: 0.8.
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version: 0.8.6
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platform: ruby
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authors:
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- Jean-Christophe Le Lann
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autorequire:
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bindir: bin
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cert_chain: []
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-
date: 2021-
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date: 2021-03-23 00:00:00.000000000 Z
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dependencies: []
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description: A Ruby handwritten VHDL parser and utilities
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email: jean-christophe.le_lann@ensta-bretagne.fr
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