vertigo_vhdl 0.8.4 → 0.8.5

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 74a318b6ff2aabefad1d87cde65a2bd2da79876f987feaf92eaffdd95c0e9429
-  data.tar.gz: 4a579a3012f0a2bcf6915f7ea33615f90f5b590219357ba1b44612ebe0fc593d
+  metadata.gz: 22b82b19e9b7744a6167a503e91914be19d58344d2853974a770933f559d6db6
+  data.tar.gz: 837894bc8b71d9fee64ad6214f55eea1add4174795abe6c96ad5c50840ea49af
 SHA512:
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-  data.tar.gz: 0dbe98eaf0f744585d05ba699ff9097d3ef63753c366a3124d598e371cc34dd0813935e0369f4d6e55a518ca97d335aa7f0d15074e4876b4bc90df891e88828c
+  metadata.gz: c7dc519c36112e25204c40399d25dac991c84887673e5a275aad94ab6c9127cfa6c02a67c6d6004754ae9669c4fe46dd316da69db12437c3ad8aba2531a6ca07
+  data.tar.gz: c002acb04a1cd830eda4b70d1e66c3ae3fa9ccc36fe740742c874eb8c3103829426778b01685ce2a7cba001f1deaf0b3551638295361b1505050e1bbb1dd81be

data/lib/vertigo/runner.rb

@@ -94,6 +94,8 @@ module Vertigo
         options[:mute]=true
       end
 
+
+
       parser.on("-v", "--version", "Show version number") do
         puts VERSION
         exit(true)

data/lib/vertigo/tb_generator.rb

@@ -16,7 +16,7 @@ module Vertigo
       vhdl_tb=gen_code()
       @tb_name=@entity_name+"_tb"
       tb_filename=@tb_name+".vhd"
-      File.open(tb_filename,'w'){|f| f.puts vhdl_tb.finalize}
+      File.open(tb_filename,'w'){|f| f.puts vhdl_tb}
       puts "=> generated testbench : #{tb_filename}"
     end
 
@@ -50,7 +50,7 @@ module Vertigo
       code << "procedure wait_cycles(n : natural) is "
       code << "begin"
       code.indent=4
-      code << "for i in 0 to n loop"
+      code << "for i in 0 to n-1 loop"
       code.indent=6
       code << "wait until rising_edge(#{@clk_name});"
       code.indent=4
@@ -70,7 +70,7 @@ module Vertigo
       code << gen_stim_process
       code.indent=0
       code << "end bhv;"
-      code
+      code.finalize
     end
 
     def gen_header
@@ -89,7 +89,7 @@ module Vertigo
       code << line
       code << comment("clock and reset")
       code << line
-      code << "#{@reset_name} <= '0','1' after 666 ns;"
+      code << "#{@reset_name} <= '0','1' after 123 ns;"
       code.newline
       code << "#{@clk_name} <= not(#{@clk_name}) after HALF_PERIOD when running else #{@clk_name};"
       code
@@ -105,10 +105,14 @@ module Vertigo
       code << "port map ("
       code.indent=4
 
-      @entity.ports.each do |port|
+      @entity.ports.each_with_index do |port,idx|
         port_name=port.name.str.ljust(@max_length_str)
         port_type=port.type.str
-        code << "#{port_name} => #{port_name},"
+        if idx < @entity.ports.size-1
+          code << "#{port_name} => #{port_name},"
+        else
+          code << "#{port_name} => #{port_name}"
+        end
       end
       code.indent=2
       code << ");"
@@ -127,7 +131,8 @@ module Vertigo
       code << "report \"running testbench for #{@entity_name}(#{@arch_name})\";"
       code << "report \"waiting for asynchronous reset\";"
       code << "wait until #{@reset_name}='1';"
-      code << "wait_cycles(100);"
+      code << "wait_cycles(10);"
+      code << "wait_cycles(10);"
       code << "report \"end of simulation\";"
       code << "running <= false;"
       code << "wait;"

data/lib/vertigo/version.rb

@@ -1,3 +1,3 @@
 module Vertigo
-  VERSION="0.8.4"
+  VERSION="0.8.5"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: vertigo_vhdl
 version: !ruby/object:Gem::Version
-  version: 0.8.4
+  version: 0.8.5
 platform: ruby
 authors:
 - Jean-Christophe Le Lann
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-05-27 00:00:00.000000000 Z
+date: 2021-01-23 00:00:00.000000000 Z
 dependencies: []
 description: A Ruby handwritten VHDL parser and utilities
 email: jean-christophe.le_lann@ensta-bretagne.fr