vertigo_vhdl 0.8.3 → 0.8.4

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: 974bdee997f8835d36bbcc8c63014ea238845ccb02b08d52f5d9bff9313481e1
+  metadata.gz: 74a318b6ff2aabefad1d87cde65a2bd2da79876f987feaf92eaffdd95c0e9429
+  data.tar.gz: 4a579a3012f0a2bcf6915f7ea33615f90f5b590219357ba1b44612ebe0fc593d
 SHA512:
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-  data.tar.gz: f71199e632d26cdecf13e6d0db8ed28f4cba9413ecb1c21bfffdd28ccb0bf30abf77c465f81c81959ef59a7ce869d2cd3255e758cc7f22c71336143e838a5da0
+  metadata.gz: a2cffee789933d35064fc383eb604e0167201d919d0681aff5becf2835e0b9c42d6e94dbf288072dd2404761b558aafad80703fd968d242ec878b34543a8b016
+  data.tar.gz: 0dbe98eaf0f744585d05ba699ff9097d3ef63753c366a3124d598e371cc34dd0813935e0369f4d6e55a518ca97d335aa7f0d15074e4876b4bc90df891e88828c

data/lib/vertigo/ast.rb

@@ -84,4 +84,11 @@ module Vertigo
     end
   end
 
+  class Architecture < AstNode
+    def << e
+      @body << e
+    end
+  end
+
+
 end

data/lib/vertigo/ast_vertigo_rkgen.rb

@@ -2,9 +2,9 @@
 # This code was generated by rkgen utility.
 # DO NOT MODIFY !
 # ============================================================
- 
+
 module Vertigo
- 
+
   class AstNode
     def accept(visitor, arg=nil)
        name = self.class.name.split(/::/).last
@@ -16,588 +16,588 @@ module Vertigo
       self.accept(ppr)
     end
   end
-   
+
   class Root < AstNode
     attr_accessor :design_units
     def initialize design_units=[]
       @design_units=design_units
     end
   end
-   
+
   class Comment < AstNode
     attr_accessor :str
     def initialize str=nil
       @str=str
     end
   end
-   
+
   class Library < AstNode
     attr_accessor :name
     def initialize name=nil
       @name=name
     end
   end
-   
+
   class Use < AstNode
     attr_accessor :library,:package,:element
     def initialize library=nil,package=nil,element=nil
       @library,@package,@element=library,package,element
     end
   end
-   
+
   class Entity < AstNode
     attr_accessor :name,:generics,:ports
     def initialize name=nil,generics=[],ports=[]
       @name,@generics,@ports=name,generics,ports
     end
   end
-   
+
   class Generic < AstNode
     attr_accessor :name,:type,:init
     def initialize name=nil,type=nil,init=nil
       @name,@type,@init=name,type,init
     end
   end
-   
+
   class Input < AstNode
     attr_accessor :name,:type,:init
     def initialize name=nil,type=nil,init=nil
       @name,@type,@init=name,type,init
     end
   end
-   
+
   class Output < AstNode
     attr_accessor :name,:type,:init
     def initialize name=nil,type=nil,init=nil
       @name,@type,@init=name,type,init
     end
   end
-   
+
   class InOut < AstNode
     attr_accessor :name,:type,:init
     def initialize name=nil,type=nil,init=nil
       @name,@type,@init=name,type,init
     end
   end
-   
+
   class Package < AstNode
     attr_accessor :name,:decls
     def initialize name=nil,decls=[]
       @name,@decls=name,decls
     end
   end
-   
+
   class PackageBody < AstNode
     attr_accessor :name,:decls
     def initialize name=nil,decls=[]
       @name,@decls=name,decls
     end
   end
-   
+
   class ProcedureDecl < AstNode
     attr_accessor :name,:formal_args,:decls,:body
     def initialize name=nil,formal_args=[],decls=[],body=nil
       @name,@formal_args,@decls,@body=name,formal_args,decls,body
     end
   end
-   
+
   class FormalArg < AstNode
     attr_accessor :signal,:direction,:name,:type
     def initialize signal=nil,direction=nil,name=nil,type=nil
       @signal,@direction,@name,@type=signal,direction,name,type
     end
   end
-   
+
   class ProcedureCall < AstNode
     attr_accessor :name,:actual_args
     def initialize name=nil,actual_args=[]
       @name,@actual_args=name,actual_args
     end
   end
-   
+
   class Architecture < AstNode
     attr_accessor :name,:entity_name,:decls,:body
     def initialize name=nil,entity_name=nil,decls=[],body=nil
       @name,@entity_name,@decls,@body=name,entity_name,decls,body
     end
   end
-   
+
   class Body < AstNode
     attr_accessor :elements
     def initialize elements=[]
       @elements=elements
     end
   end
-   
+
   class Process < AstNode
     attr_accessor :sensitivity,:decls,:body
     def initialize sensitivity=nil,decls=[],body=nil
       @sensitivity,@decls,@body=sensitivity,decls,body
     end
   end
-   
+
   class Sensitivity < AstNode
     attr_accessor :elements
     def initialize elements=[]
       @elements=elements
     end
   end
-   
+
   class EntityInstance < AstNode
     attr_accessor :full_name,:arch_name,:generic_map,:port_map
     def initialize full_name=nil,arch_name=nil,generic_map=nil,port_map=nil
       @full_name,@arch_name,@generic_map,@port_map=full_name,arch_name,generic_map,port_map
     end
   end
-   
+
   class ComponentDecl < AstNode
     attr_accessor :name,:generics,:ports
     def initialize name=nil,generics=[],ports=[]
       @name,@generics,@ports=name,generics,ports
     end
   end
-   
+
   class ComponentInstance < AstNode
     attr_accessor :name,:generic_map,:port_map
     def initialize name=nil,generic_map=nil,port_map=nil
       @name,@generic_map,@port_map=name,generic_map,port_map
     end
   end
-   
+
   class PortMap < AstNode
     attr_accessor :elements
     def initialize elements=[]
       @elements=elements
     end
   end
-   
+
   class GenericMap < AstNode
     attr_accessor :elements
     def initialize elements=[]
       @elements=elements
     end
   end
-   
+
   class Map < AstNode
     attr_accessor :lhs,:rhs
     def initialize lhs=nil,rhs=nil
       @lhs,@rhs=lhs,rhs
     end
   end
-   
+
   class AttributeDecl < AstNode
     attr_accessor :name,:type
     def initialize name=nil,type=nil
       @name,@type=name,type
     end
   end
-   
+
   class AttributeSpec < AstNode
     attr_accessor :name,:entity_spec,:expr
     def initialize name=nil,entity_spec=nil,expr=nil
       @name,@entity_spec,@expr=name,entity_spec,expr
     end
   end
-   
+
   class EntitySpec < AstNode
     attr_accessor :elements,:entity_class
     def initialize elements=[],entity_class=nil
       @elements,@entity_class=elements,entity_class
     end
   end
-   
+
   class SigAssign < AstNode
     attr_accessor :lhs,:rhs
     def initialize lhs=nil,rhs=nil
       @lhs,@rhs=lhs,rhs
     end
   end
-   
+
   class VarAssign < AstNode
     attr_accessor :lhs,:rhs
     def initialize lhs=nil,rhs=nil
       @lhs,@rhs=lhs,rhs
     end
   end
-   
+
   class Wait < AstNode
     attr_accessor :until_,:for_
     def initialize until_=nil,for_=nil
       @until_,@for_=until_,for_
     end
   end
-   
+
   class If < AstNode
     attr_accessor :cond,:body,:elsifs,:else_
     def initialize cond=nil,body=nil,elsifs=[],else_=nil
       @cond,@body,@elsifs,@else_=cond,body,elsifs,else_
     end
   end
-   
+
   class Elsif < AstNode
     attr_accessor :cond,:body
     def initialize cond=nil,body=nil
       @cond,@body=cond,body
     end
   end
-   
+
   class Else < AstNode
     attr_accessor :body
     def initialize body=nil
       @body=body
     end
   end
-   
+
   class Case < AstNode
     attr_accessor :expr,:whens
     def initialize expr=nil,whens=[]
       @expr,@whens=expr,whens
     end
   end
-   
+
   class CaseWhen < AstNode
     attr_accessor :expr,:body
     def initialize expr=nil,body=nil
       @expr,@body=expr,body
     end
   end
-   
+
   class Alternative < AstNode
     attr_accessor :elements
     def initialize elements=[]
       @elements=elements
     end
   end
-   
+
   class NullStmt < AstNode
     attr_accessor :dummy
     def initialize dummy=nil
       @dummy=dummy
     end
   end
-   
+
   class Assert < AstNode
     attr_accessor :cond,:report,:severity
     def initialize cond=nil,report=nil,severity=nil
       @cond,@report,@severity=cond,report,severity
     end
   end
-   
+
   class Report < AstNode
     attr_accessor :expr,:severity
     def initialize expr=nil,severity=nil
       @expr,@severity=expr,severity
     end
   end
-   
+
   class Severity < AstNode
     attr_accessor :type
     def initialize type=nil
       @type=type
     end
   end
-   
+
   class Return < AstNode
     attr_accessor :expr
     def initialize expr=nil
       @expr=expr
     end
   end
-   
+
   class WithSelect < AstNode
     attr_accessor :with_expr,:assigned,:selected_whens
     def initialize with_expr=nil,assigned=nil,selected_whens=[]
       @with_expr,@assigned,@selected_whens=with_expr,assigned,selected_whens
     end
   end
-   
+
   class SelectedWhen < AstNode
     attr_accessor :lhs,:rhs
     def initialize lhs=nil,rhs=nil
       @lhs,@rhs=lhs,rhs
     end
   end
-   
+
   class IfGenerate < AstNode
     attr_accessor :cond,:body
     def initialize cond=nil,body=nil
       @cond,@body=cond,body
     end
   end
-   
+
   class ForGenerate < AstNode
     attr_accessor :index,:range,:decls,:body
     def initialize index=nil,range=nil,decls=[],body=nil
       @index,@range,@decls,@body=index,range,decls,body
     end
   end
-   
+
   class IsolatedRange < AstNode
     attr_accessor :lhs,:rhs
     def initialize lhs=nil,rhs=nil
       @lhs,@rhs=lhs,rhs
     end
   end
-   
+
   class TypeDecl < AstNode
     attr_accessor :name,:spec
     def initialize name=nil,spec=nil
       @name,@spec=name,spec
     end
   end
-   
+
   class SubTypeDecl < AstNode
     attr_accessor :name,:spec
     def initialize name=nil,spec=nil
       @name,@spec=name,spec
     end
   end
-   
+
   class EnumDecl < AstNode
     attr_accessor :elements
     def initialize elements=[]
       @elements=elements
     end
   end
-   
+
   class RecordDecl < AstNode
     attr_accessor :elements
     def initialize elements=[]
       @elements=elements
     end
   end
-   
+
   class RecordItem < AstNode
     attr_accessor :name,:type
     def initialize name=nil,type=nil
       @name,@type=name,type
     end
   end
-   
+
   class ArrayDecl < AstNode
     attr_accessor :dim_decls,:type
     def initialize dim_decls=[],type=nil
       @dim_decls,@type=dim_decls,type
     end
   end
-   
+
   class ArrayDimDecl < AstNode
     attr_accessor :type_mark,:range
     def initialize type_mark=nil,range=nil
       @type_mark,@range=type_mark,range
     end
   end
-   
+
   class Constant < AstNode
     attr_accessor :name,:type,:expr
     def initialize name=nil,type=nil,expr=nil
       @name,@type,@expr=name,type,expr
     end
   end
-   
+
   class Signal < AstNode
     attr_accessor :name,:type,:init
     def initialize name=nil,type=nil,init=nil
       @name,@type,@init=name,type,init
     end
   end
-   
+
   class Variable < AstNode
     attr_accessor :name,:type,:init
     def initialize name=nil,type=nil,init=nil
       @name,@type,@init=name,type,init
     end
   end
-   
+
   class Alias < AstNode
     attr_accessor :designator,:type,:name,:signature
     def initialize designator=nil,type=nil,name=nil,signature=nil
       @designator,@type,@name,@signature=designator,type,name,signature
     end
   end
-   
+
   class StdType < AstNode
     attr_accessor :ident
     def initialize ident=nil
       @ident=ident
     end
   end
-   
+
   class RangedType < AstNode
     attr_accessor :type,:range
     def initialize type=nil,range=nil
       @type,@range=type,range
     end
   end
-   
+
   class NamedType < AstNode
     attr_accessor :ident
     def initialize ident=nil
       @ident=ident
     end
   end
-   
+
   class ArrayType < AstNode
     attr_accessor :name,:discrete_ranges
     def initialize name=nil,discrete_ranges=[]
       @name,@discrete_ranges=name,discrete_ranges
     end
   end
-   
+
   class DiscreteRange < AstNode
     attr_accessor :lhs,:dir,:rhs
     def initialize lhs=nil,dir=nil,rhs=nil
       @lhs,@dir,@rhs=lhs,dir,rhs
     end
   end
-   
+
   class Parenth < AstNode
     attr_accessor :expr
     def initialize expr=nil
       @expr=expr
     end
   end
-   
+
   class Waveform < AstNode
     attr_accessor :elements
     def initialize elements=[]
       @elements=elements
     end
   end
-   
+
   class CondExpr < AstNode
     attr_accessor :whens,:else_
     def initialize whens=[],else_=nil
       @whens,@else_=whens,else_
     end
   end
-   
+
   class When < AstNode
     attr_accessor :expr,:cond
     def initialize expr=nil,cond=nil
       @expr,@cond=expr,cond
     end
   end
-   
+
   class Binary < AstNode
     attr_accessor :lhs,:op,:rhs
     def initialize lhs=nil,op=nil,rhs=nil
       @lhs,@op,@rhs=lhs,op,rhs
     end
   end
-   
+
   class After < AstNode
     attr_accessor :lhs,:rhs
     def initialize lhs=nil,rhs=nil
       @lhs,@rhs=lhs,rhs
     end
   end
-   
+
   class Timed < AstNode
     attr_accessor :lhs,:rhs
     def initialize lhs=nil,rhs=nil
       @lhs,@rhs=lhs,rhs
     end
   end
-   
+
   class Attributed < AstNode
     attr_accessor :lhs,:rhs
     def initialize lhs=nil,rhs=nil
       @lhs,@rhs=lhs,rhs
     end
   end
-   
+
   class Concat < AstNode
     attr_accessor :lhs,:rhs
     def initialize lhs=nil,rhs=nil
       @lhs,@rhs=lhs,rhs
     end
   end
-   
+
   class Qualified < AstNode
     attr_accessor :lhs,:rhs
     def initialize lhs=nil,rhs=nil
       @lhs,@rhs=lhs,rhs
     end
   end
-   
+
   class Sliced < AstNode
     attr_accessor :expr,:lhs,:dir,:rhs
     def initialize expr=nil,lhs=nil,dir=nil,rhs=nil
       @expr,@lhs,@dir,@rhs=expr,lhs,dir,rhs
     end
   end
-   
+
   class Ident < AstNode
     attr_accessor :tok
     def initialize tok=nil
       @tok=tok
     end
   end
-   
+
   class IntLit < AstNode
     attr_accessor :tok
     def initialize tok=nil
       @tok=tok
     end
   end
-   
+
   class CharLit < AstNode
     attr_accessor :tok
     def initialize tok=nil
       @tok=tok
     end
   end
-   
+
   class BoolLit < AstNode
     attr_accessor :tok
     def initialize tok=nil
       @tok=tok
     end
   end
-   
+
   class SelectedName < AstNode
     attr_accessor :lhs,:rhs
     def initialize lhs=nil,rhs=nil
       @lhs,@rhs=lhs,rhs
     end
   end
-   
+
   class FuncProtoDecl < AstNode
     attr_accessor :name,:formal_args,:return_type
     def initialize name=nil,formal_args=[],return_type=nil
       @name,@formal_args,@return_type=name,formal_args,return_type
     end
   end
-   
+
   class FuncDecl < AstNode
     attr_accessor :name,:formal_args,:return_type,:decls,:body
     def initialize name=nil,formal_args=[],return_type=nil,decls=nil,body=nil
       @name,@formal_args,@return_type,@decls,@body=name,formal_args,return_type,decls,body
     end
   end
-   
+
   class FuncCall < AstNode
     attr_accessor :name,:actual_args
     def initialize name=nil,actual_args=[]
       @name,@actual_args=name,actual_args
     end
   end
-   
+
   class Aggregate < AstNode
     attr_accessor :elements
     def initialize elements=[]
       @elements=elements
     end
   end
-   
+
   class Label < AstNode
     attr_accessor :ident
     def initialize ident=nil
       @ident=ident
     end
   end
-   
+
   class Assoc < AstNode
     attr_accessor :lhs,:rhs
     def initialize lhs=nil,rhs=nil

data/lib/vertigo/parser.rb

@@ -197,11 +197,16 @@ module Vertigo
       }
     end
 
+    # do accept :: signal a_outputs : A_lib.A_pkg.outputs_t;
     def parse_type
       case showNext.kind
       when :ident
         type=NamedType.new
         type.ident=Ident.new(acceptIt)
+        while selected_name=selected_name?
+          selected_name.lhs=type.ident
+          type.ident=selected_name
+        end
       else
         type=StdType.new
         type.ident=Ident.new(acceptIt) # natural,...
@@ -723,7 +728,12 @@ module Vertigo
     def parse_entity_instanciation
       ret=EntityInstance.new
       expect :entity
-      ret.full_name=parse_term # ENSURE :selected_name
+      ret.full_name=parse_term # now ENSURE :selected_name
+      case fc=ret.full_name
+      when FuncCall
+        ret.full_name=fc.name
+        ret.arch_name=fc.actual_args.first
+      end
       if showNext.is_a?(:lparen)
         acceptIt
         ret.arch_name=Ident.new(expect :ident)

data/lib/vertigo/pretty_printer.rb

@@ -427,6 +427,7 @@ module Vertigo
       label=inst.label.accept(self) if inst.label
       full_name=inst.full_name.accept(self)
       arch_name=inst.arch_name.accept(self) if inst.arch_name
+      arch_name="(#{arch_name})" if inst.arch_name
       gen_map  =inst.generic_map.accept(self) if inst.generic_map
       port_map =inst.port_map.accept(self) if inst.port_map
       code << "#{label}entity #{full_name}#{arch_name}"

data/lib/vertigo/tb_generator.rb

@@ -1,5 +1,3 @@
-require 'erb'
-
 module Vertigo
 
   class TestBenchGenerator
@@ -13,16 +11,131 @@ module Vertigo
 
     def generate_from ast
       @ast=ast
-      entity_arch=find_entity_arch
-      detecting_clk_and_reset entity_arch
-      @tb_name=entity_arch.first.name.str+'_tb'
-      erb=ERB.new(IO.read "#{__dir__}/template.tb.vhd")
-      vhdl_tb=erb.result(binding)
+      entity_arch=find_entity_arch()
+      detecting_clk_and_reset(entity_arch)
+      vhdl_tb=gen_code()
+      @tb_name=@entity_name+"_tb"
       tb_filename=@tb_name+".vhd"
-      File.open(tb_filename,'w'){|f| f.puts vhdl_tb}
+      File.open(tb_filename,'w'){|f| f.puts vhdl_tb.finalize}
       puts "=> generated testbench : #{tb_filename}"
     end
 
+    def line n=80
+      "-"*n
+    end
+
+    def comment str
+      "-- #{str}"
+    end
+
+    def gen_code
+      code=Code.new
+      code << gen_header
+      code << "library ieee;"
+      code << "use ieee.std_logic_1164.all;"
+      code << "use ieee.numeric_std.all;"
+      code.newline
+      code << "entity #{@entity_name}_tb is"
+      code << "end entity;"
+      code.newline
+      code << "architecture bhv of #{@entity_name}_tb is"
+      code.indent=2
+      code << "constant HALF_PERIOD : time :=5 ns;"
+      code.newline
+      code << "signal #{@clk_name} : std_logic := '0';"
+      code << "signal #{@reset_name} : std_logic := '0';"
+      code.newline
+      code << "signal running : boolean := true;"
+      code.newline
+      code << "procedure wait_cycles(n : natural) is "
+      code << "begin"
+      code.indent=4
+      code << "for i in 0 to n loop"
+      code.indent=6
+      code << "wait until rising_edge(#{@clk_name});"
+      code.indent=4
+      code << "end loop;"
+      code.indent=2
+      code << "end procedure;"
+      @entity.ports.each do |port|
+        port_name=port.name.str.ljust(@max_length_str)
+        port_type=port.type.str
+        code << "signal #{port_name} : #{port_type};" unless @excluded.include?(port)
+      end
+      code.indent=0
+      code << "begin"
+      code.indent=2
+      code << gen_clock_and_reset
+      code << instanciate_dut
+      code << gen_stim_process
+      code.indent=0
+      code << "end bhv;"
+      code
+    end
+
+    def gen_header
+      code=Code.new
+      code << line
+      code << "-- this file was generated automatically by Vertigo Ruby utility"
+      code << "-- date : (d/m/y h:m) #{Time.now.strftime("%d/%m/%Y %k:%M")}"
+      code << "-- author : Jean-Christophe Le Lann - 2014"
+      code << line
+      code.newline
+      code
+    end
+
+    def gen_clock_and_reset
+      code=Code.new
+      code << line
+      code << comment("clock and reset")
+      code << line
+      code << "#{@reset_name} <= '0','1' after 666 ns;"
+      code.newline
+      code << "#{@clk_name} <= not(#{@clk_name}) after HALF_PERIOD when running else #{@clk_name};"
+      code
+    end
+
+    def instanciate_dut
+      code=Code.new
+      code << line
+      code << comment("Design Under Test")
+      code << line
+      code << "dut : entity work.#{@entity_name}(#{@arch_name})"
+      code.indent=2
+      code << "port map ("
+      code.indent=4
+
+      @entity.ports.each do |port|
+        port_name=port.name.str.ljust(@max_length_str)
+        port_type=port.type.str
+        code << "#{port_name} => #{port_name},"
+      end
+      code.indent=2
+      code << ");"
+      code.indent=0
+      code
+    end
+
+    def gen_stim_process
+      code=Code.new
+      code << line
+      code << comment("sequential stimuli")
+      code << line
+      code << "stim : process"
+      code << "begin"
+      code.indent=2
+      code << "report \"running testbench for #{@entity_name}(#{@arch_name})\";"
+      code << "report \"waiting for asynchronous reset\";"
+      code << "wait until #{@reset_name}='1';"
+      code << "wait_cycles(100);"
+      code << "report \"end of simulation\";"
+      code << "running <= false;"
+      code << "wait;"
+      code.indent=0
+      code << "end process;"
+      code
+    end
+
     private
     def find_entity_arch
       @entity=ast.design_units.find{|du| du.is_a? Entity}
@@ -38,6 +151,8 @@ module Vertigo
       end
 
       puts "=> found architecture '#{arch.name.str}'"
+      @entity_name=@entity.name.str
+      @arch_name=@arch.name.str
       [@entity,@arch]
     end
 
@@ -46,11 +161,13 @@ module Vertigo
       entity,arch=entity_arch
       inputs=entity.ports.select{|port| port.is_a?(Input)}
       @clk = inputs.sort_by{|input| levenshtein_distance(input.name.str,"clk")}.first
-      @rst = inputs.sort_by{|input| levenshtein_distance(input.name.str,"reset")}.first
+      @rst = inputs.sort_by{|input| levenshtein_distance(input.name.str,"reset_n")}.first
       puts "\t-most probable clk   : #{@clk.name.str}"
       puts "\t-most probable reset : #{@rst.name.str}"
       @max_length_str=entity.ports.map{|port| port.name.str.size}.max
       @excluded=[@clk,@rst]
+      @reset_name=@rst.name.str
+      @clk_name=@clk.name.str
     end
 
     def levenshtein_distance(s, t)

data/lib/vertigo/version.rb

@@ -1,3 +1,3 @@
 module Vertigo
-  VERSION="0.8.3"
+  VERSION="0.8.4"
 end

data/tests/parser_tests/pingpong.vhd

@@ -0,0 +1,34 @@
+-- generated automatically by NewageHLS
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library newage_lib;
+use newage_lib.type_package.all;
+
+
+entity PingPong_sys is
+  port(
+    reset_n : in std_logic;
+    clk : in std_logic;
+    sreset : in std_logic;
+    go : in std_logic;
+    done : out std_logic;
+    inputs : in inputs_t;
+    outputs : out outputs_t;
+    reqs : out reqs_t;
+    acks : in acks_t);
+end entity PingPong_sys;
+
+architecture RTL of PingPong_sys is
+begin
+
+  inst_0 : entity Player1_lib.ping(RTL)
+    port map(
+    );
+
+  inst_1 : entity Player2_lib.pong(RTL)
+    port map(
+    );
+
+end RTL;

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: vertigo_vhdl
 version: !ruby/object:Gem::Version
-  version: 0.8.3
+  version: 0.8.4
 platform: ruby
 authors:
 - Jean-Christophe Le Lann
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-05-04 00:00:00.000000000 Z
+date: 2020-05-27 00:00:00.000000000 Z
 dependencies: []
 description: A Ruby handwritten VHDL parser and utilities
 email: jean-christophe.le_lann@ensta-bretagne.fr
@@ -31,7 +31,6 @@ files:
 - lib/vertigo/pretty_printer.rb
 - lib/vertigo/runner.rb
 - lib/vertigo/tb_generator.rb
-- lib/vertigo/template.tb.vhd
 - lib/vertigo/token.rb
 - lib/vertigo/version.rb
 - lib/vertigo/vertigo.rkg
@@ -40,6 +39,7 @@ files:
 - tests/ghdl_tests/fsm_synth.vhd
 - tests/ghdl_tests/test_fsm.vhd
 - tests/parser_tests/else.vhd
+- tests/parser_tests/pingpong.vhd
 - tests/parser_tests/test_MUST_fail.vhd
 - tests/parser_tests/test_accelerator.vhd
 - tests/parser_tests/test_accelerator_pp.vhd

data/lib/vertigo/template.tb.vhd

@@ -1,72 +0,0 @@
------------------------------------------------------------------
--- This file was generated automatically by Vertigo Ruby utility
--- date : <%=Time.now.strftime("(d/m/y) %d/%m/%Y %H:%M")%>
--- Author : Jean-Christophe Le Lann - 2014
------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-<%@supplemental_libs_h.each do |lib,packages|%>
-library <%=lib%>;
-<%packages.each do |package|%>
-use <%=lib%>.<%=package%>.all;
-<%end%>
-<%end%>
-
-entity <%=@tb_name%> is
-end entity;
-
-architecture bhv of <%=@tb_name%> is
-
-  constant HALF_PERIOD : time := 5 ns;
-
-  signal <%=clk.name.str%> : std_logic := '0';
-  signal <%=rst.name.str%> : std_logic := '0';
-
-  signal running : boolean   := true;
-
-  procedure wait_cycles(n : natural) is
-   begin
-     for i in 1 to n loop
-       wait until rising_edge(clk);
-     end loop;
-   end procedure;
-
-<%=@entity.ports.collect do |port|
-  "  signal #{port.name.str.ljust(@max_length_str)} : #{port.type.str}" if not @excluded.include?(port)
-  end.compact.join(";\n")%>;
-
-begin
-  -------------------------------------------------------------------
-  -- clock and reset
-  -------------------------------------------------------------------
-  reset_n <= '0','1' after 666 ns;
-
-  clk <= not(clk) after HALF_PERIOD when running else clk;
-
-  --------------------------------------------------------------------
-  -- Design Under Test
-  --------------------------------------------------------------------
-  dut : entity work.<%=@entity.name.str%>(<%=@arch.name.str%>)
-        <%=@generics%>
-        port map ( <%map=@entity.ports.collect do |port| "\t  #{port.name.str} => #{port.name.str}" end%>
-<%=map.join(",\n")%>
-        );
-
-  --------------------------------------------------------------------
-  -- sequential stimuli
-  --------------------------------------------------------------------
-  stim : process
-   begin
-     report "running testbench for <%=@entity.name.str%>(<%=@arch.name.str%>)";
-     report "waiting for asynchronous reset";
-     wait until reset_n='1';
-     wait_cycles(100);
-     report "applying stimuli...";
-     wait_cycles(100);
-     report "end of simulation";
-     running <=false;
-     wait;
-   end process;
-
-end bhv;