vertigo_vhdl 0.8.2 → 0.8.7
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- checksums.yaml +4 -4
- data/lib/vertigo/ast.rb +7 -0
- data/lib/vertigo/ast_vertigo_rkgen.rb +86 -86
- data/lib/vertigo/parser.rb +11 -1
- data/lib/vertigo/pretty_printer.rb +1 -0
- data/lib/vertigo/runner.rb +2 -0
- data/lib/vertigo/tb_generator.rb +149 -14
- data/lib/vertigo/version.rb +1 -1
- data/tests/parser_tests/pingpong.vhd +34 -0
- metadata +3 -3
- data/lib/vertigo/template.tb.vhd +0 -72
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
---
|
2
2
|
SHA256:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: eb22a79a9fe6c4cfeeb9293cea9e7c08d0b70c6a220261f00476fa79200cd930
|
4
|
+
data.tar.gz: a6e30af8d8f623f1fe4f411b845f31429637a377879443be9f9231620315ece1
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: de3f891d744486704a4b253a00e9a19da00e1ba8a0d1716729a97ed21f010f3f41dfc1cb92824d6112c4c3256d5b61bd4478d31bec693d89c4df749c74b2715d
|
7
|
+
data.tar.gz: bf8e2e13ddfbc9f02d1037cd9bf50450643a0e17a88f9f451c09656fb294ce5508e5abaa5c4b48212b79b9c480621989f9db797c23a373c80acc52ea363c448c
|
data/lib/vertigo/ast.rb
CHANGED
@@ -2,9 +2,9 @@
|
|
2
2
|
# This code was generated by rkgen utility.
|
3
3
|
# DO NOT MODIFY !
|
4
4
|
# ============================================================
|
5
|
-
|
5
|
+
|
6
6
|
module Vertigo
|
7
|
-
|
7
|
+
|
8
8
|
class AstNode
|
9
9
|
def accept(visitor, arg=nil)
|
10
10
|
name = self.class.name.split(/::/).last
|
@@ -16,588 +16,588 @@ module Vertigo
|
|
16
16
|
self.accept(ppr)
|
17
17
|
end
|
18
18
|
end
|
19
|
-
|
19
|
+
|
20
20
|
class Root < AstNode
|
21
21
|
attr_accessor :design_units
|
22
22
|
def initialize design_units=[]
|
23
23
|
@design_units=design_units
|
24
24
|
end
|
25
25
|
end
|
26
|
-
|
26
|
+
|
27
27
|
class Comment < AstNode
|
28
28
|
attr_accessor :str
|
29
29
|
def initialize str=nil
|
30
30
|
@str=str
|
31
31
|
end
|
32
32
|
end
|
33
|
-
|
33
|
+
|
34
34
|
class Library < AstNode
|
35
35
|
attr_accessor :name
|
36
36
|
def initialize name=nil
|
37
37
|
@name=name
|
38
38
|
end
|
39
39
|
end
|
40
|
-
|
40
|
+
|
41
41
|
class Use < AstNode
|
42
42
|
attr_accessor :library,:package,:element
|
43
43
|
def initialize library=nil,package=nil,element=nil
|
44
44
|
@library,@package,@element=library,package,element
|
45
45
|
end
|
46
46
|
end
|
47
|
-
|
47
|
+
|
48
48
|
class Entity < AstNode
|
49
49
|
attr_accessor :name,:generics,:ports
|
50
50
|
def initialize name=nil,generics=[],ports=[]
|
51
51
|
@name,@generics,@ports=name,generics,ports
|
52
52
|
end
|
53
53
|
end
|
54
|
-
|
54
|
+
|
55
55
|
class Generic < AstNode
|
56
56
|
attr_accessor :name,:type,:init
|
57
57
|
def initialize name=nil,type=nil,init=nil
|
58
58
|
@name,@type,@init=name,type,init
|
59
59
|
end
|
60
60
|
end
|
61
|
-
|
61
|
+
|
62
62
|
class Input < AstNode
|
63
63
|
attr_accessor :name,:type,:init
|
64
64
|
def initialize name=nil,type=nil,init=nil
|
65
65
|
@name,@type,@init=name,type,init
|
66
66
|
end
|
67
67
|
end
|
68
|
-
|
68
|
+
|
69
69
|
class Output < AstNode
|
70
70
|
attr_accessor :name,:type,:init
|
71
71
|
def initialize name=nil,type=nil,init=nil
|
72
72
|
@name,@type,@init=name,type,init
|
73
73
|
end
|
74
74
|
end
|
75
|
-
|
75
|
+
|
76
76
|
class InOut < AstNode
|
77
77
|
attr_accessor :name,:type,:init
|
78
78
|
def initialize name=nil,type=nil,init=nil
|
79
79
|
@name,@type,@init=name,type,init
|
80
80
|
end
|
81
81
|
end
|
82
|
-
|
82
|
+
|
83
83
|
class Package < AstNode
|
84
84
|
attr_accessor :name,:decls
|
85
85
|
def initialize name=nil,decls=[]
|
86
86
|
@name,@decls=name,decls
|
87
87
|
end
|
88
88
|
end
|
89
|
-
|
89
|
+
|
90
90
|
class PackageBody < AstNode
|
91
91
|
attr_accessor :name,:decls
|
92
92
|
def initialize name=nil,decls=[]
|
93
93
|
@name,@decls=name,decls
|
94
94
|
end
|
95
95
|
end
|
96
|
-
|
96
|
+
|
97
97
|
class ProcedureDecl < AstNode
|
98
98
|
attr_accessor :name,:formal_args,:decls,:body
|
99
99
|
def initialize name=nil,formal_args=[],decls=[],body=nil
|
100
100
|
@name,@formal_args,@decls,@body=name,formal_args,decls,body
|
101
101
|
end
|
102
102
|
end
|
103
|
-
|
103
|
+
|
104
104
|
class FormalArg < AstNode
|
105
105
|
attr_accessor :signal,:direction,:name,:type
|
106
106
|
def initialize signal=nil,direction=nil,name=nil,type=nil
|
107
107
|
@signal,@direction,@name,@type=signal,direction,name,type
|
108
108
|
end
|
109
109
|
end
|
110
|
-
|
110
|
+
|
111
111
|
class ProcedureCall < AstNode
|
112
112
|
attr_accessor :name,:actual_args
|
113
113
|
def initialize name=nil,actual_args=[]
|
114
114
|
@name,@actual_args=name,actual_args
|
115
115
|
end
|
116
116
|
end
|
117
|
-
|
117
|
+
|
118
118
|
class Architecture < AstNode
|
119
119
|
attr_accessor :name,:entity_name,:decls,:body
|
120
120
|
def initialize name=nil,entity_name=nil,decls=[],body=nil
|
121
121
|
@name,@entity_name,@decls,@body=name,entity_name,decls,body
|
122
122
|
end
|
123
123
|
end
|
124
|
-
|
124
|
+
|
125
125
|
class Body < AstNode
|
126
126
|
attr_accessor :elements
|
127
127
|
def initialize elements=[]
|
128
128
|
@elements=elements
|
129
129
|
end
|
130
130
|
end
|
131
|
-
|
131
|
+
|
132
132
|
class Process < AstNode
|
133
133
|
attr_accessor :sensitivity,:decls,:body
|
134
134
|
def initialize sensitivity=nil,decls=[],body=nil
|
135
135
|
@sensitivity,@decls,@body=sensitivity,decls,body
|
136
136
|
end
|
137
137
|
end
|
138
|
-
|
138
|
+
|
139
139
|
class Sensitivity < AstNode
|
140
140
|
attr_accessor :elements
|
141
141
|
def initialize elements=[]
|
142
142
|
@elements=elements
|
143
143
|
end
|
144
144
|
end
|
145
|
-
|
145
|
+
|
146
146
|
class EntityInstance < AstNode
|
147
147
|
attr_accessor :full_name,:arch_name,:generic_map,:port_map
|
148
148
|
def initialize full_name=nil,arch_name=nil,generic_map=nil,port_map=nil
|
149
149
|
@full_name,@arch_name,@generic_map,@port_map=full_name,arch_name,generic_map,port_map
|
150
150
|
end
|
151
151
|
end
|
152
|
-
|
152
|
+
|
153
153
|
class ComponentDecl < AstNode
|
154
154
|
attr_accessor :name,:generics,:ports
|
155
155
|
def initialize name=nil,generics=[],ports=[]
|
156
156
|
@name,@generics,@ports=name,generics,ports
|
157
157
|
end
|
158
158
|
end
|
159
|
-
|
159
|
+
|
160
160
|
class ComponentInstance < AstNode
|
161
161
|
attr_accessor :name,:generic_map,:port_map
|
162
162
|
def initialize name=nil,generic_map=nil,port_map=nil
|
163
163
|
@name,@generic_map,@port_map=name,generic_map,port_map
|
164
164
|
end
|
165
165
|
end
|
166
|
-
|
166
|
+
|
167
167
|
class PortMap < AstNode
|
168
168
|
attr_accessor :elements
|
169
169
|
def initialize elements=[]
|
170
170
|
@elements=elements
|
171
171
|
end
|
172
172
|
end
|
173
|
-
|
173
|
+
|
174
174
|
class GenericMap < AstNode
|
175
175
|
attr_accessor :elements
|
176
176
|
def initialize elements=[]
|
177
177
|
@elements=elements
|
178
178
|
end
|
179
179
|
end
|
180
|
-
|
180
|
+
|
181
181
|
class Map < AstNode
|
182
182
|
attr_accessor :lhs,:rhs
|
183
183
|
def initialize lhs=nil,rhs=nil
|
184
184
|
@lhs,@rhs=lhs,rhs
|
185
185
|
end
|
186
186
|
end
|
187
|
-
|
187
|
+
|
188
188
|
class AttributeDecl < AstNode
|
189
189
|
attr_accessor :name,:type
|
190
190
|
def initialize name=nil,type=nil
|
191
191
|
@name,@type=name,type
|
192
192
|
end
|
193
193
|
end
|
194
|
-
|
194
|
+
|
195
195
|
class AttributeSpec < AstNode
|
196
196
|
attr_accessor :name,:entity_spec,:expr
|
197
197
|
def initialize name=nil,entity_spec=nil,expr=nil
|
198
198
|
@name,@entity_spec,@expr=name,entity_spec,expr
|
199
199
|
end
|
200
200
|
end
|
201
|
-
|
201
|
+
|
202
202
|
class EntitySpec < AstNode
|
203
203
|
attr_accessor :elements,:entity_class
|
204
204
|
def initialize elements=[],entity_class=nil
|
205
205
|
@elements,@entity_class=elements,entity_class
|
206
206
|
end
|
207
207
|
end
|
208
|
-
|
208
|
+
|
209
209
|
class SigAssign < AstNode
|
210
210
|
attr_accessor :lhs,:rhs
|
211
211
|
def initialize lhs=nil,rhs=nil
|
212
212
|
@lhs,@rhs=lhs,rhs
|
213
213
|
end
|
214
214
|
end
|
215
|
-
|
215
|
+
|
216
216
|
class VarAssign < AstNode
|
217
217
|
attr_accessor :lhs,:rhs
|
218
218
|
def initialize lhs=nil,rhs=nil
|
219
219
|
@lhs,@rhs=lhs,rhs
|
220
220
|
end
|
221
221
|
end
|
222
|
-
|
222
|
+
|
223
223
|
class Wait < AstNode
|
224
224
|
attr_accessor :until_,:for_
|
225
225
|
def initialize until_=nil,for_=nil
|
226
226
|
@until_,@for_=until_,for_
|
227
227
|
end
|
228
228
|
end
|
229
|
-
|
229
|
+
|
230
230
|
class If < AstNode
|
231
231
|
attr_accessor :cond,:body,:elsifs,:else_
|
232
232
|
def initialize cond=nil,body=nil,elsifs=[],else_=nil
|
233
233
|
@cond,@body,@elsifs,@else_=cond,body,elsifs,else_
|
234
234
|
end
|
235
235
|
end
|
236
|
-
|
236
|
+
|
237
237
|
class Elsif < AstNode
|
238
238
|
attr_accessor :cond,:body
|
239
239
|
def initialize cond=nil,body=nil
|
240
240
|
@cond,@body=cond,body
|
241
241
|
end
|
242
242
|
end
|
243
|
-
|
243
|
+
|
244
244
|
class Else < AstNode
|
245
245
|
attr_accessor :body
|
246
246
|
def initialize body=nil
|
247
247
|
@body=body
|
248
248
|
end
|
249
249
|
end
|
250
|
-
|
250
|
+
|
251
251
|
class Case < AstNode
|
252
252
|
attr_accessor :expr,:whens
|
253
253
|
def initialize expr=nil,whens=[]
|
254
254
|
@expr,@whens=expr,whens
|
255
255
|
end
|
256
256
|
end
|
257
|
-
|
257
|
+
|
258
258
|
class CaseWhen < AstNode
|
259
259
|
attr_accessor :expr,:body
|
260
260
|
def initialize expr=nil,body=nil
|
261
261
|
@expr,@body=expr,body
|
262
262
|
end
|
263
263
|
end
|
264
|
-
|
264
|
+
|
265
265
|
class Alternative < AstNode
|
266
266
|
attr_accessor :elements
|
267
267
|
def initialize elements=[]
|
268
268
|
@elements=elements
|
269
269
|
end
|
270
270
|
end
|
271
|
-
|
271
|
+
|
272
272
|
class NullStmt < AstNode
|
273
273
|
attr_accessor :dummy
|
274
274
|
def initialize dummy=nil
|
275
275
|
@dummy=dummy
|
276
276
|
end
|
277
277
|
end
|
278
|
-
|
278
|
+
|
279
279
|
class Assert < AstNode
|
280
280
|
attr_accessor :cond,:report,:severity
|
281
281
|
def initialize cond=nil,report=nil,severity=nil
|
282
282
|
@cond,@report,@severity=cond,report,severity
|
283
283
|
end
|
284
284
|
end
|
285
|
-
|
285
|
+
|
286
286
|
class Report < AstNode
|
287
287
|
attr_accessor :expr,:severity
|
288
288
|
def initialize expr=nil,severity=nil
|
289
289
|
@expr,@severity=expr,severity
|
290
290
|
end
|
291
291
|
end
|
292
|
-
|
292
|
+
|
293
293
|
class Severity < AstNode
|
294
294
|
attr_accessor :type
|
295
295
|
def initialize type=nil
|
296
296
|
@type=type
|
297
297
|
end
|
298
298
|
end
|
299
|
-
|
299
|
+
|
300
300
|
class Return < AstNode
|
301
301
|
attr_accessor :expr
|
302
302
|
def initialize expr=nil
|
303
303
|
@expr=expr
|
304
304
|
end
|
305
305
|
end
|
306
|
-
|
306
|
+
|
307
307
|
class WithSelect < AstNode
|
308
308
|
attr_accessor :with_expr,:assigned,:selected_whens
|
309
309
|
def initialize with_expr=nil,assigned=nil,selected_whens=[]
|
310
310
|
@with_expr,@assigned,@selected_whens=with_expr,assigned,selected_whens
|
311
311
|
end
|
312
312
|
end
|
313
|
-
|
313
|
+
|
314
314
|
class SelectedWhen < AstNode
|
315
315
|
attr_accessor :lhs,:rhs
|
316
316
|
def initialize lhs=nil,rhs=nil
|
317
317
|
@lhs,@rhs=lhs,rhs
|
318
318
|
end
|
319
319
|
end
|
320
|
-
|
320
|
+
|
321
321
|
class IfGenerate < AstNode
|
322
322
|
attr_accessor :cond,:body
|
323
323
|
def initialize cond=nil,body=nil
|
324
324
|
@cond,@body=cond,body
|
325
325
|
end
|
326
326
|
end
|
327
|
-
|
327
|
+
|
328
328
|
class ForGenerate < AstNode
|
329
329
|
attr_accessor :index,:range,:decls,:body
|
330
330
|
def initialize index=nil,range=nil,decls=[],body=nil
|
331
331
|
@index,@range,@decls,@body=index,range,decls,body
|
332
332
|
end
|
333
333
|
end
|
334
|
-
|
334
|
+
|
335
335
|
class IsolatedRange < AstNode
|
336
336
|
attr_accessor :lhs,:rhs
|
337
337
|
def initialize lhs=nil,rhs=nil
|
338
338
|
@lhs,@rhs=lhs,rhs
|
339
339
|
end
|
340
340
|
end
|
341
|
-
|
341
|
+
|
342
342
|
class TypeDecl < AstNode
|
343
343
|
attr_accessor :name,:spec
|
344
344
|
def initialize name=nil,spec=nil
|
345
345
|
@name,@spec=name,spec
|
346
346
|
end
|
347
347
|
end
|
348
|
-
|
348
|
+
|
349
349
|
class SubTypeDecl < AstNode
|
350
350
|
attr_accessor :name,:spec
|
351
351
|
def initialize name=nil,spec=nil
|
352
352
|
@name,@spec=name,spec
|
353
353
|
end
|
354
354
|
end
|
355
|
-
|
355
|
+
|
356
356
|
class EnumDecl < AstNode
|
357
357
|
attr_accessor :elements
|
358
358
|
def initialize elements=[]
|
359
359
|
@elements=elements
|
360
360
|
end
|
361
361
|
end
|
362
|
-
|
362
|
+
|
363
363
|
class RecordDecl < AstNode
|
364
364
|
attr_accessor :elements
|
365
365
|
def initialize elements=[]
|
366
366
|
@elements=elements
|
367
367
|
end
|
368
368
|
end
|
369
|
-
|
369
|
+
|
370
370
|
class RecordItem < AstNode
|
371
371
|
attr_accessor :name,:type
|
372
372
|
def initialize name=nil,type=nil
|
373
373
|
@name,@type=name,type
|
374
374
|
end
|
375
375
|
end
|
376
|
-
|
376
|
+
|
377
377
|
class ArrayDecl < AstNode
|
378
378
|
attr_accessor :dim_decls,:type
|
379
379
|
def initialize dim_decls=[],type=nil
|
380
380
|
@dim_decls,@type=dim_decls,type
|
381
381
|
end
|
382
382
|
end
|
383
|
-
|
383
|
+
|
384
384
|
class ArrayDimDecl < AstNode
|
385
385
|
attr_accessor :type_mark,:range
|
386
386
|
def initialize type_mark=nil,range=nil
|
387
387
|
@type_mark,@range=type_mark,range
|
388
388
|
end
|
389
389
|
end
|
390
|
-
|
390
|
+
|
391
391
|
class Constant < AstNode
|
392
392
|
attr_accessor :name,:type,:expr
|
393
393
|
def initialize name=nil,type=nil,expr=nil
|
394
394
|
@name,@type,@expr=name,type,expr
|
395
395
|
end
|
396
396
|
end
|
397
|
-
|
397
|
+
|
398
398
|
class Signal < AstNode
|
399
399
|
attr_accessor :name,:type,:init
|
400
400
|
def initialize name=nil,type=nil,init=nil
|
401
401
|
@name,@type,@init=name,type,init
|
402
402
|
end
|
403
403
|
end
|
404
|
-
|
404
|
+
|
405
405
|
class Variable < AstNode
|
406
406
|
attr_accessor :name,:type,:init
|
407
407
|
def initialize name=nil,type=nil,init=nil
|
408
408
|
@name,@type,@init=name,type,init
|
409
409
|
end
|
410
410
|
end
|
411
|
-
|
411
|
+
|
412
412
|
class Alias < AstNode
|
413
413
|
attr_accessor :designator,:type,:name,:signature
|
414
414
|
def initialize designator=nil,type=nil,name=nil,signature=nil
|
415
415
|
@designator,@type,@name,@signature=designator,type,name,signature
|
416
416
|
end
|
417
417
|
end
|
418
|
-
|
418
|
+
|
419
419
|
class StdType < AstNode
|
420
420
|
attr_accessor :ident
|
421
421
|
def initialize ident=nil
|
422
422
|
@ident=ident
|
423
423
|
end
|
424
424
|
end
|
425
|
-
|
425
|
+
|
426
426
|
class RangedType < AstNode
|
427
427
|
attr_accessor :type,:range
|
428
428
|
def initialize type=nil,range=nil
|
429
429
|
@type,@range=type,range
|
430
430
|
end
|
431
431
|
end
|
432
|
-
|
432
|
+
|
433
433
|
class NamedType < AstNode
|
434
434
|
attr_accessor :ident
|
435
435
|
def initialize ident=nil
|
436
436
|
@ident=ident
|
437
437
|
end
|
438
438
|
end
|
439
|
-
|
439
|
+
|
440
440
|
class ArrayType < AstNode
|
441
441
|
attr_accessor :name,:discrete_ranges
|
442
442
|
def initialize name=nil,discrete_ranges=[]
|
443
443
|
@name,@discrete_ranges=name,discrete_ranges
|
444
444
|
end
|
445
445
|
end
|
446
|
-
|
446
|
+
|
447
447
|
class DiscreteRange < AstNode
|
448
448
|
attr_accessor :lhs,:dir,:rhs
|
449
449
|
def initialize lhs=nil,dir=nil,rhs=nil
|
450
450
|
@lhs,@dir,@rhs=lhs,dir,rhs
|
451
451
|
end
|
452
452
|
end
|
453
|
-
|
453
|
+
|
454
454
|
class Parenth < AstNode
|
455
455
|
attr_accessor :expr
|
456
456
|
def initialize expr=nil
|
457
457
|
@expr=expr
|
458
458
|
end
|
459
459
|
end
|
460
|
-
|
460
|
+
|
461
461
|
class Waveform < AstNode
|
462
462
|
attr_accessor :elements
|
463
463
|
def initialize elements=[]
|
464
464
|
@elements=elements
|
465
465
|
end
|
466
466
|
end
|
467
|
-
|
467
|
+
|
468
468
|
class CondExpr < AstNode
|
469
469
|
attr_accessor :whens,:else_
|
470
470
|
def initialize whens=[],else_=nil
|
471
471
|
@whens,@else_=whens,else_
|
472
472
|
end
|
473
473
|
end
|
474
|
-
|
474
|
+
|
475
475
|
class When < AstNode
|
476
476
|
attr_accessor :expr,:cond
|
477
477
|
def initialize expr=nil,cond=nil
|
478
478
|
@expr,@cond=expr,cond
|
479
479
|
end
|
480
480
|
end
|
481
|
-
|
481
|
+
|
482
482
|
class Binary < AstNode
|
483
483
|
attr_accessor :lhs,:op,:rhs
|
484
484
|
def initialize lhs=nil,op=nil,rhs=nil
|
485
485
|
@lhs,@op,@rhs=lhs,op,rhs
|
486
486
|
end
|
487
487
|
end
|
488
|
-
|
488
|
+
|
489
489
|
class After < AstNode
|
490
490
|
attr_accessor :lhs,:rhs
|
491
491
|
def initialize lhs=nil,rhs=nil
|
492
492
|
@lhs,@rhs=lhs,rhs
|
493
493
|
end
|
494
494
|
end
|
495
|
-
|
495
|
+
|
496
496
|
class Timed < AstNode
|
497
497
|
attr_accessor :lhs,:rhs
|
498
498
|
def initialize lhs=nil,rhs=nil
|
499
499
|
@lhs,@rhs=lhs,rhs
|
500
500
|
end
|
501
501
|
end
|
502
|
-
|
502
|
+
|
503
503
|
class Attributed < AstNode
|
504
504
|
attr_accessor :lhs,:rhs
|
505
505
|
def initialize lhs=nil,rhs=nil
|
506
506
|
@lhs,@rhs=lhs,rhs
|
507
507
|
end
|
508
508
|
end
|
509
|
-
|
509
|
+
|
510
510
|
class Concat < AstNode
|
511
511
|
attr_accessor :lhs,:rhs
|
512
512
|
def initialize lhs=nil,rhs=nil
|
513
513
|
@lhs,@rhs=lhs,rhs
|
514
514
|
end
|
515
515
|
end
|
516
|
-
|
516
|
+
|
517
517
|
class Qualified < AstNode
|
518
518
|
attr_accessor :lhs,:rhs
|
519
519
|
def initialize lhs=nil,rhs=nil
|
520
520
|
@lhs,@rhs=lhs,rhs
|
521
521
|
end
|
522
522
|
end
|
523
|
-
|
523
|
+
|
524
524
|
class Sliced < AstNode
|
525
525
|
attr_accessor :expr,:lhs,:dir,:rhs
|
526
526
|
def initialize expr=nil,lhs=nil,dir=nil,rhs=nil
|
527
527
|
@expr,@lhs,@dir,@rhs=expr,lhs,dir,rhs
|
528
528
|
end
|
529
529
|
end
|
530
|
-
|
530
|
+
|
531
531
|
class Ident < AstNode
|
532
532
|
attr_accessor :tok
|
533
533
|
def initialize tok=nil
|
534
534
|
@tok=tok
|
535
535
|
end
|
536
536
|
end
|
537
|
-
|
537
|
+
|
538
538
|
class IntLit < AstNode
|
539
539
|
attr_accessor :tok
|
540
540
|
def initialize tok=nil
|
541
541
|
@tok=tok
|
542
542
|
end
|
543
543
|
end
|
544
|
-
|
544
|
+
|
545
545
|
class CharLit < AstNode
|
546
546
|
attr_accessor :tok
|
547
547
|
def initialize tok=nil
|
548
548
|
@tok=tok
|
549
549
|
end
|
550
550
|
end
|
551
|
-
|
551
|
+
|
552
552
|
class BoolLit < AstNode
|
553
553
|
attr_accessor :tok
|
554
554
|
def initialize tok=nil
|
555
555
|
@tok=tok
|
556
556
|
end
|
557
557
|
end
|
558
|
-
|
558
|
+
|
559
559
|
class SelectedName < AstNode
|
560
560
|
attr_accessor :lhs,:rhs
|
561
561
|
def initialize lhs=nil,rhs=nil
|
562
562
|
@lhs,@rhs=lhs,rhs
|
563
563
|
end
|
564
564
|
end
|
565
|
-
|
565
|
+
|
566
566
|
class FuncProtoDecl < AstNode
|
567
567
|
attr_accessor :name,:formal_args,:return_type
|
568
568
|
def initialize name=nil,formal_args=[],return_type=nil
|
569
569
|
@name,@formal_args,@return_type=name,formal_args,return_type
|
570
570
|
end
|
571
571
|
end
|
572
|
-
|
572
|
+
|
573
573
|
class FuncDecl < AstNode
|
574
574
|
attr_accessor :name,:formal_args,:return_type,:decls,:body
|
575
575
|
def initialize name=nil,formal_args=[],return_type=nil,decls=nil,body=nil
|
576
576
|
@name,@formal_args,@return_type,@decls,@body=name,formal_args,return_type,decls,body
|
577
577
|
end
|
578
578
|
end
|
579
|
-
|
579
|
+
|
580
580
|
class FuncCall < AstNode
|
581
581
|
attr_accessor :name,:actual_args
|
582
582
|
def initialize name=nil,actual_args=[]
|
583
583
|
@name,@actual_args=name,actual_args
|
584
584
|
end
|
585
585
|
end
|
586
|
-
|
586
|
+
|
587
587
|
class Aggregate < AstNode
|
588
588
|
attr_accessor :elements
|
589
589
|
def initialize elements=[]
|
590
590
|
@elements=elements
|
591
591
|
end
|
592
592
|
end
|
593
|
-
|
593
|
+
|
594
594
|
class Label < AstNode
|
595
595
|
attr_accessor :ident
|
596
596
|
def initialize ident=nil
|
597
597
|
@ident=ident
|
598
598
|
end
|
599
599
|
end
|
600
|
-
|
600
|
+
|
601
601
|
class Assoc < AstNode
|
602
602
|
attr_accessor :lhs,:rhs
|
603
603
|
def initialize lhs=nil,rhs=nil
|
data/lib/vertigo/parser.rb
CHANGED
@@ -197,11 +197,16 @@ module Vertigo
|
|
197
197
|
}
|
198
198
|
end
|
199
199
|
|
200
|
+
# do accept :: signal a_outputs : A_lib.A_pkg.outputs_t;
|
200
201
|
def parse_type
|
201
202
|
case showNext.kind
|
202
203
|
when :ident
|
203
204
|
type=NamedType.new
|
204
205
|
type.ident=Ident.new(acceptIt)
|
206
|
+
while selected_name=selected_name?
|
207
|
+
selected_name.lhs=type.ident
|
208
|
+
type.ident=selected_name
|
209
|
+
end
|
205
210
|
else
|
206
211
|
type=StdType.new
|
207
212
|
type.ident=Ident.new(acceptIt) # natural,...
|
@@ -723,7 +728,12 @@ module Vertigo
|
|
723
728
|
def parse_entity_instanciation
|
724
729
|
ret=EntityInstance.new
|
725
730
|
expect :entity
|
726
|
-
ret.full_name=parse_term # ENSURE :selected_name
|
731
|
+
ret.full_name=parse_term # now ENSURE :selected_name
|
732
|
+
case fc=ret.full_name
|
733
|
+
when FuncCall
|
734
|
+
ret.full_name=fc.name
|
735
|
+
ret.arch_name=fc.actual_args.first
|
736
|
+
end
|
727
737
|
if showNext.is_a?(:lparen)
|
728
738
|
acceptIt
|
729
739
|
ret.arch_name=Ident.new(expect :ident)
|
@@ -427,6 +427,7 @@ module Vertigo
|
|
427
427
|
label=inst.label.accept(self) if inst.label
|
428
428
|
full_name=inst.full_name.accept(self)
|
429
429
|
arch_name=inst.arch_name.accept(self) if inst.arch_name
|
430
|
+
arch_name="(#{arch_name})" if inst.arch_name
|
430
431
|
gen_map =inst.generic_map.accept(self) if inst.generic_map
|
431
432
|
port_map =inst.port_map.accept(self) if inst.port_map
|
432
433
|
code << "#{label}entity #{full_name}#{arch_name}"
|
data/lib/vertigo/runner.rb
CHANGED
data/lib/vertigo/tb_generator.rb
CHANGED
@@ -1,11 +1,12 @@
|
|
1
|
-
require 'erb'
|
2
|
-
|
3
1
|
module Vertigo
|
4
2
|
|
5
3
|
class TestBenchGenerator
|
4
|
+
|
6
5
|
attr_accessor :ast
|
7
6
|
attr_accessor :entity,:arch
|
8
7
|
attr_accessor :clk,:rst
|
8
|
+
attr_accessor :options
|
9
|
+
|
9
10
|
def initialize options={}
|
10
11
|
@options=options
|
11
12
|
@supplemental_libs_h=options[:supplemental_libs_h]||{}
|
@@ -13,14 +14,144 @@ module Vertigo
|
|
13
14
|
|
14
15
|
def generate_from ast
|
15
16
|
@ast=ast
|
16
|
-
entity_arch=find_entity_arch
|
17
|
-
detecting_clk_and_reset
|
18
|
-
|
19
|
-
|
20
|
-
vhdl_tb=erb.result(binding)
|
17
|
+
entity_arch=find_entity_arch()
|
18
|
+
detecting_clk_and_reset(entity_arch)
|
19
|
+
vhdl_tb=gen_code()
|
20
|
+
@tb_name=@entity_name+"_tb"
|
21
21
|
tb_filename=@tb_name+".vhd"
|
22
22
|
File.open(tb_filename,'w'){|f| f.puts vhdl_tb}
|
23
|
-
puts "=> generated testbench : #{tb_filename}"
|
23
|
+
puts "=> generated testbench : #{tb_filename}" unless options[:mute]
|
24
|
+
return tb_filename
|
25
|
+
end
|
26
|
+
|
27
|
+
def line n=80
|
28
|
+
"-"*n
|
29
|
+
end
|
30
|
+
|
31
|
+
def comment str
|
32
|
+
"-- #{str}"
|
33
|
+
end
|
34
|
+
|
35
|
+
def gen_code
|
36
|
+
code=Code.new
|
37
|
+
code << gen_header
|
38
|
+
code << "library ieee;"
|
39
|
+
code << "use ieee.std_logic_1164.all;"
|
40
|
+
code << "use ieee.numeric_std.all;"
|
41
|
+
code.newline
|
42
|
+
code << "entity #{@entity_name}_tb is"
|
43
|
+
code << "end entity;"
|
44
|
+
code.newline
|
45
|
+
code << "architecture bhv of #{@entity_name}_tb is"
|
46
|
+
code.indent=2
|
47
|
+
code << "constant HALF_PERIOD : time :=5 ns;"
|
48
|
+
code.newline
|
49
|
+
code << "signal #{@clk_name} : std_logic := '0';"
|
50
|
+
code << "signal #{@reset_name} : std_logic := '0';"
|
51
|
+
code.newline
|
52
|
+
code << "signal running : boolean := true;"
|
53
|
+
code.newline
|
54
|
+
code << "procedure wait_cycles(n : natural) is "
|
55
|
+
code << "begin"
|
56
|
+
code.indent=4
|
57
|
+
code << "for i in 0 to n-1 loop"
|
58
|
+
code.indent=6
|
59
|
+
code << "wait until rising_edge(#{@clk_name});"
|
60
|
+
code.indent=4
|
61
|
+
code << "end loop;"
|
62
|
+
code.indent=2
|
63
|
+
code << "end procedure;"
|
64
|
+
code.newline
|
65
|
+
code << "procedure toggle(signal s : inout std_logic) is"
|
66
|
+
code << "begin"
|
67
|
+
code << " wait until rising_edge(clk);"
|
68
|
+
code << " s <=not(s);"
|
69
|
+
code << " wait until rising_edge(clk);"
|
70
|
+
code << " s <=not(s);"
|
71
|
+
code << "end procedure;"
|
72
|
+
code.newline
|
73
|
+
@entity.ports.each do |port|
|
74
|
+
port_name=port.name.str.ljust(@max_length_str)
|
75
|
+
port_type=port.type.str
|
76
|
+
code << "signal #{port_name} : #{port_type};" unless @excluded.include?(port)
|
77
|
+
end
|
78
|
+
code.indent=0
|
79
|
+
code << "begin"
|
80
|
+
code.indent=2
|
81
|
+
code << gen_clock_and_reset
|
82
|
+
code << instanciate_dut
|
83
|
+
code << gen_stim_process
|
84
|
+
code.indent=0
|
85
|
+
code << "end bhv;"
|
86
|
+
code.finalize
|
87
|
+
end
|
88
|
+
|
89
|
+
def gen_header
|
90
|
+
code=Code.new
|
91
|
+
code << line
|
92
|
+
code << "-- this file was generated automatically by Vertigo Ruby utility"
|
93
|
+
code << "-- date : (d/m/y h:m) #{Time.now.strftime("%d/%m/%Y %k:%M")}"
|
94
|
+
code << "-- author : Jean-Christophe Le Lann - 2014"
|
95
|
+
code << line
|
96
|
+
code.newline
|
97
|
+
code
|
98
|
+
end
|
99
|
+
|
100
|
+
def gen_clock_and_reset
|
101
|
+
code=Code.new
|
102
|
+
code << line
|
103
|
+
code << comment("clock and reset")
|
104
|
+
code << line
|
105
|
+
code << "#{@reset_name} <= '0','1' after 123 ns;"
|
106
|
+
code.newline
|
107
|
+
code << "#{@clk_name} <= not(#{@clk_name}) after HALF_PERIOD when running else #{@clk_name};"
|
108
|
+
code
|
109
|
+
end
|
110
|
+
|
111
|
+
def instanciate_dut
|
112
|
+
code=Code.new
|
113
|
+
code << line
|
114
|
+
code << comment("Design Under Test")
|
115
|
+
code << line
|
116
|
+
code << "dut : entity work.#{@entity_name}(#{@arch_name})"
|
117
|
+
code.indent=2
|
118
|
+
code << "port map ("
|
119
|
+
code.indent=4
|
120
|
+
|
121
|
+
@entity.ports.each_with_index do |port,idx|
|
122
|
+
port_name=port.name.str.ljust(@max_length_str)
|
123
|
+
port_type=port.type.str
|
124
|
+
if idx < @entity.ports.size-1
|
125
|
+
code << "#{port_name} => #{port_name},"
|
126
|
+
else
|
127
|
+
code << "#{port_name} => #{port_name}"
|
128
|
+
end
|
129
|
+
end
|
130
|
+
code.indent=2
|
131
|
+
code << ");"
|
132
|
+
code.indent=0
|
133
|
+
code
|
134
|
+
end
|
135
|
+
|
136
|
+
def gen_stim_process
|
137
|
+
code=Code.new
|
138
|
+
code << line
|
139
|
+
code << comment("sequential stimuli")
|
140
|
+
code << line
|
141
|
+
code << "stim : process"
|
142
|
+
code << "begin"
|
143
|
+
code.indent=2
|
144
|
+
code << "report \"running testbench for #{@entity_name}(#{@arch_name})\";"
|
145
|
+
code << "report \"waiting for asynchronous reset\";"
|
146
|
+
code << "wait until #{@reset_name}='1';"
|
147
|
+
code << "wait_cycles(10);"
|
148
|
+
code << "wait_cycles(10);"
|
149
|
+
code << "report \"end of simulation\";"
|
150
|
+
code << "running <= false;"
|
151
|
+
code << "wait;"
|
152
|
+
code.indent=0
|
153
|
+
code << "end process;"
|
154
|
+
code
|
24
155
|
end
|
25
156
|
|
26
157
|
private
|
@@ -30,27 +161,31 @@ module Vertigo
|
|
30
161
|
puts msg="ERROR : no entity found"
|
31
162
|
raise msg
|
32
163
|
end
|
33
|
-
puts "=> found entity '#{entity.name.str}'"
|
164
|
+
puts "=> found entity '#{entity.name.str}'" unless options[:mute]
|
34
165
|
@arch=ast.design_units.find{|du| du.is_a? Architecture}
|
35
166
|
if @arch.nil?
|
36
167
|
puts msg="ERROR : no architecture found"
|
37
168
|
raise msg
|
38
169
|
end
|
39
170
|
|
40
|
-
puts "=> found architecture '#{arch.name.str}'"
|
171
|
+
puts "=> found architecture '#{arch.name.str}'" unless options[:mute]
|
172
|
+
@entity_name=@entity.name.str
|
173
|
+
@arch_name=@arch.name.str
|
41
174
|
[@entity,@arch]
|
42
175
|
end
|
43
176
|
|
44
177
|
def detecting_clk_and_reset entity_arch
|
45
|
-
puts "=> detecting clock and reset"
|
178
|
+
puts "=> detecting clock and reset" unless options[:mute]
|
46
179
|
entity,arch=entity_arch
|
47
180
|
inputs=entity.ports.select{|port| port.is_a?(Input)}
|
48
181
|
@clk = inputs.sort_by{|input| levenshtein_distance(input.name.str,"clk")}.first
|
49
|
-
@rst = inputs.sort_by{|input| levenshtein_distance(input.name.str,"
|
50
|
-
puts "\t-most probable clk : #{@clk.name.str}"
|
51
|
-
puts "\t-most probable reset : #{@rst.name.str}"
|
182
|
+
@rst = inputs.sort_by{|input| levenshtein_distance(input.name.str,"reset_n")}.first
|
183
|
+
puts "\t-most probable clk : #{@clk.name.str}" unless options[:mute]
|
184
|
+
puts "\t-most probable reset : #{@rst.name.str}" unless options[:mute]
|
52
185
|
@max_length_str=entity.ports.map{|port| port.name.str.size}.max
|
53
186
|
@excluded=[@clk,@rst]
|
187
|
+
@reset_name=@rst.name.str
|
188
|
+
@clk_name=@clk.name.str
|
54
189
|
end
|
55
190
|
|
56
191
|
def levenshtein_distance(s, t)
|
data/lib/vertigo/version.rb
CHANGED
@@ -0,0 +1,34 @@
|
|
1
|
+
-- generated automatically by NewageHLS
|
2
|
+
library ieee;
|
3
|
+
use ieee.std_logic_1164.all;
|
4
|
+
use ieee.numeric_std.all;
|
5
|
+
|
6
|
+
library newage_lib;
|
7
|
+
use newage_lib.type_package.all;
|
8
|
+
|
9
|
+
|
10
|
+
entity PingPong_sys is
|
11
|
+
port(
|
12
|
+
reset_n : in std_logic;
|
13
|
+
clk : in std_logic;
|
14
|
+
sreset : in std_logic;
|
15
|
+
go : in std_logic;
|
16
|
+
done : out std_logic;
|
17
|
+
inputs : in inputs_t;
|
18
|
+
outputs : out outputs_t;
|
19
|
+
reqs : out reqs_t;
|
20
|
+
acks : in acks_t);
|
21
|
+
end entity PingPong_sys;
|
22
|
+
|
23
|
+
architecture RTL of PingPong_sys is
|
24
|
+
begin
|
25
|
+
|
26
|
+
inst_0 : entity Player1_lib.ping(RTL)
|
27
|
+
port map(
|
28
|
+
);
|
29
|
+
|
30
|
+
inst_1 : entity Player2_lib.pong(RTL)
|
31
|
+
port map(
|
32
|
+
);
|
33
|
+
|
34
|
+
end RTL;
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: vertigo_vhdl
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.8.
|
4
|
+
version: 0.8.7
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Jean-Christophe Le Lann
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date:
|
11
|
+
date: 2021-04-01 00:00:00.000000000 Z
|
12
12
|
dependencies: []
|
13
13
|
description: A Ruby handwritten VHDL parser and utilities
|
14
14
|
email: jean-christophe.le_lann@ensta-bretagne.fr
|
@@ -31,7 +31,6 @@ files:
|
|
31
31
|
- lib/vertigo/pretty_printer.rb
|
32
32
|
- lib/vertigo/runner.rb
|
33
33
|
- lib/vertigo/tb_generator.rb
|
34
|
-
- lib/vertigo/template.tb.vhd
|
35
34
|
- lib/vertigo/token.rb
|
36
35
|
- lib/vertigo/version.rb
|
37
36
|
- lib/vertigo/vertigo.rkg
|
@@ -40,6 +39,7 @@ files:
|
|
40
39
|
- tests/ghdl_tests/fsm_synth.vhd
|
41
40
|
- tests/ghdl_tests/test_fsm.vhd
|
42
41
|
- tests/parser_tests/else.vhd
|
42
|
+
- tests/parser_tests/pingpong.vhd
|
43
43
|
- tests/parser_tests/test_MUST_fail.vhd
|
44
44
|
- tests/parser_tests/test_accelerator.vhd
|
45
45
|
- tests/parser_tests/test_accelerator_pp.vhd
|
data/lib/vertigo/template.tb.vhd
DELETED
@@ -1,72 +0,0 @@
|
|
1
|
-
-----------------------------------------------------------------
|
2
|
-
-- This file was generated automatically by Vertigo Ruby utility
|
3
|
-
-- date : <%=Time.now.strftime("(d/m/y) %d/%m/%Y %H:%M")%>
|
4
|
-
-- Author : Jean-Christophe Le Lann - 2014
|
5
|
-
-----------------------------------------------------------------
|
6
|
-
library ieee;
|
7
|
-
use ieee.std_logic_1164.all;
|
8
|
-
use ieee.numeric_std.all;
|
9
|
-
<%@supplemental_libs_h.each do |lib,packages|%>
|
10
|
-
library <%=lib%>;
|
11
|
-
<%packages.each do |package|%>
|
12
|
-
use <%=lib%>.<%=package%>.all;
|
13
|
-
<%end%>
|
14
|
-
<%end%>
|
15
|
-
|
16
|
-
entity <%=@tb_name%> is
|
17
|
-
end entity;
|
18
|
-
|
19
|
-
architecture bhv of <%=@tb_name%> is
|
20
|
-
|
21
|
-
constant HALF_PERIOD : time := 5 ns;
|
22
|
-
|
23
|
-
signal <%=clk.name.str%> : std_logic := '0';
|
24
|
-
signal <%=rst.name.str%> : std_logic := '0';
|
25
|
-
|
26
|
-
signal running : boolean := true;
|
27
|
-
|
28
|
-
procedure wait_cycles(n : natural) is
|
29
|
-
begin
|
30
|
-
for i in 1 to n loop
|
31
|
-
wait until rising_edge(clk);
|
32
|
-
end loop;
|
33
|
-
end procedure;
|
34
|
-
|
35
|
-
<%=@entity.ports.collect do |port|
|
36
|
-
" signal #{port.name.str.ljust(@max_length_str)} : #{port.type.str}" if not @excluded.include?(port)
|
37
|
-
end.compact.join(";\n")%>;
|
38
|
-
|
39
|
-
begin
|
40
|
-
-------------------------------------------------------------------
|
41
|
-
-- clock and reset
|
42
|
-
-------------------------------------------------------------------
|
43
|
-
reset_n <= '0','1' after 666 ns;
|
44
|
-
|
45
|
-
clk <= not(clk) after HALF_PERIOD when running else clk;
|
46
|
-
|
47
|
-
--------------------------------------------------------------------
|
48
|
-
-- Design Under Test
|
49
|
-
--------------------------------------------------------------------
|
50
|
-
dut : entity work.<%=@entity.name.str%>(<%=@arch.name.str%>)
|
51
|
-
<%=@generics%>
|
52
|
-
port map ( <%map=@entity.ports.collect do |port| "\t #{port.name.str} => #{port.name.str}" end%>
|
53
|
-
<%=map.join(",\n")%>
|
54
|
-
);
|
55
|
-
|
56
|
-
--------------------------------------------------------------------
|
57
|
-
-- sequential stimuli
|
58
|
-
--------------------------------------------------------------------
|
59
|
-
stim : process
|
60
|
-
begin
|
61
|
-
report "running testbench for <%=@entity.name.str%>(<%=@arch.name.str%>)";
|
62
|
-
report "waiting for asynchronous reset";
|
63
|
-
wait until reset_n='1';
|
64
|
-
wait_cycles(100);
|
65
|
-
report "applying stimuli...";
|
66
|
-
wait_cycles(100);
|
67
|
-
report "end of simulation";
|
68
|
-
running <=false;
|
69
|
-
wait;
|
70
|
-
end process;
|
71
|
-
|
72
|
-
end bhv;
|