vertigo_vhdl 0.8.13 → 0.8.15

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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  ---
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  SHA256:
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- metadata.gz: 3f7eecaed2d4b5a72e742bb50665fe8dc039c540ba3ccf97a5c78938b3eadec4
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- data.tar.gz: 04eaa1b607442048ef566c5bd067bf9c93e37bca35f8c60ed44301a6454423f1
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+ metadata.gz: 635b13128c3f914c6626e38592085949ea68dce1b7b73476586f6876869217d7
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+ data.tar.gz: 9e615326ef6eaec062919f0f0ed910d317fa21cefea6a20512ddf335599ed7c5
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  SHA512:
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- metadata.gz: b4d1b525899302571608d769efd34992e00310f9a851b920e82a39441e86fcfffa602f65ced5747c95acd5c75b44f610e190fe650dd1feb85acfe738c83ef8d7
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- data.tar.gz: 95862bbfc72888c6f48433ac4c019fbbf8294543f2e3b5a2db3cffce76fe867172bc1fba446602900b8591906ad059b7051cac7cbeedf74881c9c13446b10d68
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+ metadata.gz: 1e1d0f67ff7ea8fd521db96b711d917362faade0487936f915614ad8490074caf76fff9021b34662267467d7642acdfd8c8f0a0d670570cfa3bb59b414b9d468
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+ data.tar.gz: 862a444335445f42fe6a1aeacf9b9a59f523ea3168d267a2791cd7c38ec3f5e4e785145db8eaf5dcadaa1a469079b8bdd7e646b7531290949521c2a8038cda5e
@@ -15,7 +15,7 @@ module Vertigo
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  end
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  def lex filename
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- unless File.exists?(filename)
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+ unless File.exist?(filename)
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  raise "ERROR : cannot find file '#{filename}'"
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  end
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  begin
@@ -94,8 +94,6 @@ module Vertigo
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  options[:mute]=true
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  end
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-
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-
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  parser.on("-v", "--version", "Show version number") do
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  puts VERSION
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  exit(true)
@@ -68,9 +68,9 @@ module Vertigo
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  code.newline
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  code << "procedure toggle(signal s : inout std_logic) is"
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  code << "begin"
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- code << " wait until rising_edge(clk);"
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+ code << " wait until rising_edge(#{@clk_name});"
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  code << " s <=not(s);"
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- code << " wait until rising_edge(clk);"
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+ code << " wait until rising_edge(#{@clk_name});"
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  code << " s <=not(s);"
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  code << "end procedure;"
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  code.newline
@@ -1,3 +1,3 @@
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  module Vertigo
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- VERSION="0.8.13"
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+ VERSION="0.8.15"
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  end
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: vertigo_vhdl
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  version: !ruby/object:Gem::Version
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- version: 0.8.13
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+ version: 0.8.15
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  platform: ruby
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  authors:
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  - Jean-Christophe Le Lann
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2023-10-18 00:00:00.000000000 Z
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+ date: 2024-11-05 00:00:00.000000000 Z
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  dependencies: []
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  description: A Ruby handwritten VHDL parser and utilities
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  email: jean-christophe.le_lann@ensta-bretagne.fr