vertigo_vhdl 0.8.13 → 0.8.14
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- checksums.yaml +4 -4
- data/lib/vertigo/tb_generator.rb +2 -2
- data/lib/vertigo/version.rb +1 -1
- metadata +2 -2
checksums.yaml
CHANGED
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@@ -1,7 +1,7 @@
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1
1
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---
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2
2
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SHA256:
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3
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-
metadata.gz:
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4
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-
data.tar.gz:
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3
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+
metadata.gz: c8378d338d4ebc178cf5fec08f6aa2e0601cd0119bd684d29acf1980115fbed2
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4
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+
data.tar.gz: 965c56bc3bca0c562b6f11e55f498a31c720e68e56fac9b40a6d09d0eb2f885e
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5
5
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SHA512:
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6
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-
metadata.gz:
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|
7
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-
data.tar.gz:
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6
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+
metadata.gz: ad5d0885aa192abba0fc562e62ff689efa2e7253950d113998165489bd5c06c6b85f4510852dedd01710e87afd4dc65b1d10ac8d03ef08d837e30d51c3358d95
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|
7
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+
data.tar.gz: 631cafa7550689910810e11677ab4138146e545dc64e2b7de0872f2b8f61abc05a74c700359f3c46b1e5c89c7b32114cf433f5274d0b5a9b4d4bd86a8bc68e2a
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data/lib/vertigo/tb_generator.rb
CHANGED
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@@ -68,9 +68,9 @@ module Vertigo
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68
68
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code.newline
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69
69
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code << "procedure toggle(signal s : inout std_logic) is"
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70
70
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code << "begin"
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71
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-
code << " wait until rising_edge(
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|
71
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+
code << " wait until rising_edge(#{@clk_name});"
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72
72
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code << " s <=not(s);"
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73
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-
code << " wait until rising_edge(
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|
73
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+
code << " wait until rising_edge(#{@clk_name});"
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74
74
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code << " s <=not(s);"
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75
75
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code << "end procedure;"
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76
76
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code.newline
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data/lib/vertigo/version.rb
CHANGED
metadata
CHANGED
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@@ -1,14 +1,14 @@
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1
1
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--- !ruby/object:Gem::Specification
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2
2
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name: vertigo_vhdl
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3
3
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version: !ruby/object:Gem::Version
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4
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-
version: 0.8.
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4
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+
version: 0.8.14
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5
5
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platform: ruby
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6
6
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authors:
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7
7
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- Jean-Christophe Le Lann
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8
8
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autorequire:
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|
9
9
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bindir: bin
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10
10
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cert_chain: []
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|
11
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-
date:
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|
11
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+
date: 2024-02-08 00:00:00.000000000 Z
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12
12
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dependencies: []
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13
13
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description: A Ruby handwritten VHDL parser and utilities
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14
14
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email: jean-christophe.le_lann@ensta-bretagne.fr
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