vertigo_vhdl 0.8.12 → 0.8.13

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: 9a02b22f74a9843113918dfcb26e7f97681c72244df7bdcaa4651549294dec16
+  metadata.gz: 3f7eecaed2d4b5a72e742bb50665fe8dc039c540ba3ccf97a5c78938b3eadec4
+  data.tar.gz: 04eaa1b607442048ef566c5bd067bf9c93e37bca35f8c60ed44301a6454423f1
 SHA512:
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+  metadata.gz: b4d1b525899302571608d769efd34992e00310f9a851b920e82a39441e86fcfffa602f65ced5747c95acd5c75b44f610e190fe650dd1feb85acfe738c83ef8d7
+  data.tar.gz: 95862bbfc72888c6f48433ac4c019fbbf8294543f2e3b5a2db3cffce76fe867172bc1fba446602900b8591906ad059b7051cac7cbeedf74881c9c13446b10d68

data/lib/vertigo/parser.rb

@@ -669,6 +669,9 @@ module Vertigo
       if showNext.is_a?(:lparen)
         ret.sensitivity=parse_sensitivity_list
       end
+      if showNext.is_a? :is
+        acceptIt
+      end
       ret.decls=parse_decls
       ret.decls.flatten!
       expect :begin

data/lib/vertigo/version.rb

@@ -1,3 +1,3 @@
 module Vertigo
-  VERSION="0.8.12"
+  VERSION="0.8.13"
 end

data/tests/parser_tests/test_LUT.vhd

@@ -0,0 +1,62 @@
+-- ghdl -a [nom].vhd
+-- vertigo --gen_tb [nom].vhd
+-- ghdl -a [nom_tb].vhd
+-- ghdl -e [nom_tb]
+-- ghdl -r [nom_tb]
+-- ghdl -r [nom_tb] --wave=[nom_wave].ghw
+-- gtkwave [nom].ghw
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity LUT is
+  port (
+    clk  : in std_logic;
+    rst  : in std_logic;
+    push : in std_logic;
+    a    : in std_logic;
+    b    : in std_logic;
+    bitstream : in std_logic;
+    f    : out std_logic
+
+  );
+end LUT;
+
+architecture arch of LUT is
+	signal Q : std_logic_vector (3 downto 0);
+	signal T : std_logic_vector (1 downto 0);
+begin
+
+process(clk, rst) is
+	begin
+
+		if rst = '0' then
+			Q(0) <= '0';
+			Q(1) <= '0';
+			Q(2) <= '0';
+			Q(3) <= '0';
+
+		elsif rising_edge(clk) then
+			if push = '1' then
+				Q(0) <= bitstream;
+				Q(1) <= Q(0);
+				Q(2) <= Q(1);
+				Q(3) <= Q(2);
+			end if;
+		end if;
+	end process;
+
+process (a, b) is
+	begin
+		t(0) <= a;
+		t(1) <= b;
+		case t is
+			when "00"   => f <= Q(0);
+			when "01"   => f <= Q(1);
+			when "10"   => f <= Q(2);
+			when "11"   => f <= Q(3);
+			when others => f <= Q(0);
+		end case;
+	end process;
+end arch;

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: vertigo_vhdl
 version: !ruby/object:Gem::Version
-  version: 0.8.12
+  version: 0.8.13
 platform: ruby
 authors:
 - Jean-Christophe Le Lann
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-02-15 00:00:00.000000000 Z
+date: 2023-10-18 00:00:00.000000000 Z
 dependencies: []
 description: A Ruby handwritten VHDL parser and utilities
 email: jean-christophe.le_lann@ensta-bretagne.fr
@@ -39,6 +39,7 @@ files:
 - tests/ghdl_tests/arbitre_tb.vhd
 - tests/ghdl_tests/fsm.vhd
 - tests/ghdl_tests/fsm_synth.vhd
+- tests/parser_tests/test_LUT.vhd
 - tests/parser_tests/test_MUST_fail.vhd
 - tests/parser_tests/test_accelerator.vhd
 - tests/parser_tests/test_adder_rca_vhdl93.vhd