vertigo_vhdl 0.8.11 → 0.8.12

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 5f66142ff1aa2f02093dbc99c8cd22a78a44ae177d0ecaf41e1cc3289b505e80
-  data.tar.gz: 406108f6e1fc88d54cd96b38708772e7051788b8c9ab9417a15bef96326004e1
+  metadata.gz: a3459a1e9abbe835d383e2137cfa7f34146d14d54813888019e75d72ac37a24d
+  data.tar.gz: 9a02b22f74a9843113918dfcb26e7f97681c72244df7bdcaa4651549294dec16
 SHA512:
-  metadata.gz: 9c3f59eea1d1a2ca3ec6c22361bcd5eb54512b95a9b76e60465d6aa2749072d730fc0d79d28cfe0b2d11048f49a29f655d55aabc34cf6f0c8fcbd0c82b3f440c
-  data.tar.gz: a12214d7979e71a31172ce35fa67ac7ca3bbf69c4a3e8730acdeae20c451cb9344b3a2c1d567389db41ffa699a896db6244f8ec3fdd4f9d15600d9caf7ef857e
+  metadata.gz: e676079468bfc02a31d541aef60289f2da02a7daf90c59019e240e3eb5b833ed1ff94f4391398bc61fecae80ff62a255c5db1a809b12f4dae37f3ae019a507aa
+  data.tar.gz: 2297f5a293fb186a4b4c7073b32d3a70af9df714835b8e58a1686c1757552629c0c6ec536ab0f18761d3d664b504b11952f325af89157392959f9ffd47978d48

data/lib/vertigo/parser.rb

@@ -1259,6 +1259,7 @@ module Vertigo
 
 
     def parse_term
+      #pp showNext
       if showNext.is_a? [:ident,:dot,:integer,:natural,:positive,:decimal_literal,:based_literal,:char_literal,:string_literal,:true,:false,:bit_string_literal,:lparen,:others,:abs,:not,:sub,:open]
         case showNext.kind
         when :ident

data/lib/vertigo/tb_generator.rb

@@ -74,7 +74,9 @@ module Vertigo
       code << "  s <=not(s);"
       code << "end procedure;"
       code.newline
-      @entity.ports.each do |port|
+      # bug discovered by a student : when he forgets "in" or "out" in entity port...
+      # fix : compact
+      @entity.ports.compact.each do |port|
         port_name=port.name.str.ljust(@max_length_str)
         port_type=port.type.str
         code << "signal #{port_name} : #{port_type};" unless @excluded.include?(port)
@@ -124,7 +126,7 @@ module Vertigo
       code << "port map ("
       code.indent=4
 
-      @entity.ports.each_with_index do |port,idx|
+      @entity.ports.compact.each_with_index do |port,idx|
         port_name=port.name.str.ljust(@max_length_str)
         port_type=port.type.str
         if idx < @entity.ports.size-1
@@ -189,7 +191,9 @@ module Vertigo
       puts "\t-most probable clk   : #{@clk.name.str}" unless options[:mute]
       puts "\t-most probable reset : #{@rst.name.str}" unless options[:mute]
 
-      @max_length_str=entity.ports.map{|port| port.name.str.size}.max
+      # bug discovered by a student : when he forgets "in" or "out" in port !
+      # fix : .compact
+      @max_length_str=entity.ports.compact.map{|port| port.name.str.size}.max
 
       print "\t-validate [Y/n] ? "
       answer=$stdin.gets.chomp

data/lib/vertigo/version.rb

@@ -1,3 +1,3 @@
 module Vertigo
-  VERSION="0.8.11"
+  VERSION="0.8.12"
 end

data/tests/ghdl_tests/arbitre.vhd

@@ -0,0 +1,79 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity arbitre is
+port(
+	clk : in std_logic;
+	reset_n : in std_logic;
+	r : std_logic_vector(1 downto 0);
+	outputs : out std_logic_vector(1 downto 0)
+	);
+end arbitre;
+
+architecture arch of arbitre is
+	type etat is (A, B, C, D);
+	signal state, next_state : etat;
+	begin
+		p0 : process(clk, reset_n)
+			begin
+				if reset_n = '0' then
+					state <= A;
+				elsif rising_edge(clk) then
+					state <= next_state;
+				end if;
+		end process;
+			
+		p1 : process(reset_n, r)
+			begin
+				next_state <= state;
+				case state is
+					when A =>
+						if r = "10" or r = "11" then
+							state <= C;
+						elsif r = "01" then
+							state <= D;
+						elsif r = "00" then
+							state <= state;
+						end if;
+					when B =>
+						if r = "01" or r = "11" then
+							state <= D;
+						elsif r = "10" then
+							state <= C;
+						elsif r = "00" then
+							state <= state;
+						end if;
+					when C =>
+						if r = "01" then
+							state <= D;
+						elsif r = "00" then
+							state <= B;
+						elsif r = "10" or r = "11" then
+							state <= state;
+						end if;
+					when D =>
+						if r = "10" then
+							state <= C;
+						elsif r = "00" then
+							state <= A;
+						elsif r = "01" or r = "11" then
+							state <= state;
+						end if;
+				end case;
+		end process;
+		
+		p3 : process(state)
+			begin
+				if state = A then
+					outputs <= "00";
+				elsif state = B then
+					outputs <= "00";
+				elsif state = C then
+					outputs <= "10";
+				elsif state = D then
+					outputs <= "01";
+				end if;
+		end process;
+end arch;
+					

data/tests/ghdl_tests/arbitre_tb.vhd

@@ -0,0 +1,67 @@
+--------------------------------------------------------------------------------
+-- this file was generated automatically by Vertigo Ruby utility
+-- date : (d/m/y h:m) 15/02/2023 14:26
+-- author : Jean-Christophe Le Lann - 2014
+--------------------------------------------------------------------------------
+ 
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+ 
+entity arbitre_tb is
+end entity;
+ 
+architecture bhv of arbitre_tb is
+  constant HALF_PERIOD : time :=5 ns;
+ 
+  signal clk : std_logic := '0';
+  signal reset_n : std_logic := '0';
+ 
+  signal running : boolean := true;
+ 
+  procedure wait_cycles(n : natural) is 
+  begin
+    for i in 0 to n-1 loop
+      wait until rising_edge(clk);
+    end loop;
+  end procedure;
+ 
+  procedure toggle(signal s : inout std_logic) is
+  begin
+    wait until rising_edge(clk);
+    s <=not(s);
+    wait until rising_edge(clk);
+    s <=not(s);
+  end procedure;
+ 
+  signal outputs : std_logic_vector(1 downto 0);
+begin
+  --------------------------------------------------------------------------------
+  -- clock and reset
+  --------------------------------------------------------------------------------
+  reset_n <= '0','1' after 123 ns;
+   
+  clk <= not(clk) after HALF_PERIOD when running else clk;
+  --------------------------------------------------------------------------------
+  -- Design Under Test
+  --------------------------------------------------------------------------------
+  dut : entity work.arbitre(arch)
+    port map (
+      clk     => clk    ,
+      reset_n => reset_n,
+      outputs => outputs);
+  --------------------------------------------------------------------------------
+  -- sequential stimuli
+  --------------------------------------------------------------------------------
+  stim : process
+  begin
+    report "running testbench for arbitre(arch)";
+    report "waiting for asynchronous reset";
+    wait until reset_n='1';
+    wait_cycles(10);
+    wait_cycles(200);
+    report "end of simulation";
+    running <= false;
+    wait;
+  end process;
+end bhv;

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: vertigo_vhdl
 version: !ruby/object:Gem::Version
-  version: 0.8.11
+  version: 0.8.12
 platform: ruby
 authors:
 - Jean-Christophe Le Lann
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2021-11-02 00:00:00.000000000 Z
+date: 2023-02-15 00:00:00.000000000 Z
 dependencies: []
 description: A Ruby handwritten VHDL parser and utilities
 email: jean-christophe.le_lann@ensta-bretagne.fr
@@ -35,6 +35,8 @@ files:
 - lib/vertigo/version.rb
 - lib/vertigo/vertigo.rkg
 - lib/vertigo/visitor_vertigo_rkgen.rb
+- tests/ghdl_tests/arbitre.vhd
+- tests/ghdl_tests/arbitre_tb.vhd
 - tests/ghdl_tests/fsm.vhd
 - tests/ghdl_tests/fsm_synth.vhd
 - tests/parser_tests/test_MUST_fail.vhd