verilog_gen 0.0.1
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- checksums.yaml +7 -0
- data/.gitignore +18 -0
- data/.rvmrc +1 -0
- data/Gemfile +11 -0
- data/LICENSE.txt +22 -0
- data/README.md +29 -0
- data/Rakefile +1 -0
- data/bin/vgen +2 -0
- data/features/hello.feature +8 -0
- data/features/support/aruba.rb +1 -0
- data/features/support/env.rb +5 -0
- data/lib/verilog_gen/version.rb +3 -0
- data/lib/verilog_gen.rb +5 -0
- data/verilog_gen.gemspec +23 -0
- metadata +91 -0
checksums.yaml
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---
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SHA1:
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metadata.gz: e6704b1a822e219b49e5f613a69d19a068810b62
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data.tar.gz: 717d1f7e1ed314da94394d46ae698253c6c955e3
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SHA512:
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metadata.gz: 081b28ce4d838b57a8cf8cce2d3bd13646a0a596f94b2612e6d616585ca9dcbd7fd8d11fbe54768b0d82c5ed116e5ba43b1f243e3de139178beeb6b68eea48e9
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data.tar.gz: 43a1dd83ad58d83fe6e65f476d29ac13721f1c5d918cbdf80e36e082c2e7011e65e2b1786050e0d0b5fb7173d8eed6733033e67d7b9af096b57dbb44450a6c4a
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data/.gitignore
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data/.rvmrc
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rvm --create use 2.0.0@verilog_gen
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data/Gemfile
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data/LICENSE.txt
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Copyright (c) 2014 sanjeev singh
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MIT License
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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data/README.md
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# VerilogGen
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TODO: Write a gem description
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## Installation
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Add this line to your application's Gemfile:
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gem 'verilog_gen'
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And then execute:
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$ bundle
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Or install it yourself as:
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$ gem install verilog_gen
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## Usage
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TODO: Write usage instructions here
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## Contributing
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1. Fork it ( http://github.com/<my-github-username>/verilog_gen/fork )
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2. Create your feature branch (`git checkout -b my-new-feature`)
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3. Commit your changes (`git commit -am 'Add some feature'`)
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4. Push to the branch (`git push origin my-new-feature`)
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5. Create new Pull Request
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data/Rakefile
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require "bundler/gem_tasks"
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data/bin/vgen
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require 'aruba/cucumber'
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data/lib/verilog_gen.rb
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data/verilog_gen.gemspec
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# coding: utf-8
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lib = File.expand_path('../lib', __FILE__)
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$LOAD_PATH.unshift(lib) unless $LOAD_PATH.include?(lib)
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require 'verilog_gen/version'
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Gem::Specification.new do |spec|
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spec.name = "verilog_gen"
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spec.version = VerilogGen::VERSION
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spec.authors = ["sanjeev singh"]
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spec.email = ["spsingh2@ncsu.edu"]
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spec.summary = %q{Generate verilog RTL hierarchy.}
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spec.description = %q{Writing portable RTL design in verilog is challenging due to limitations of verilog language. Hence would like to write the leaf modules of the design in verilog but use Ruby to stich different views of the design.}
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spec.homepage = ""
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spec.license = "MIT"
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spec.files = `git ls-files -z`.split("\x0")
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spec.executables = spec.files.grep(%r{^bin/}) { |f| File.basename(f) }
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spec.test_files = spec.files.grep(%r{^(test|spec|features)/})
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spec.require_paths = ["lib"]
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spec.add_development_dependency "bundler", "~> 1.5"
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spec.add_development_dependency "rake"
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end
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metadata
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--- !ruby/object:Gem::Specification
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name: verilog_gen
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version: !ruby/object:Gem::Version
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version: 0.0.1
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platform: ruby
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authors:
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- sanjeev singh
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2014-10-03 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: bundler
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - ~>
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- !ruby/object:Gem::Version
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version: '1.5'
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type: :development
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - ~>
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- !ruby/object:Gem::Version
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version: '1.5'
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- !ruby/object:Gem::Dependency
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name: rake
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - '>='
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- !ruby/object:Gem::Version
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version: '0'
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type: :development
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - '>='
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- !ruby/object:Gem::Version
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version: '0'
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description: Writing portable RTL design in verilog is challenging due to limitations
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of verilog language. Hence would like to write the leaf modules of the design in
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verilog but use Ruby to stich different views of the design.
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email:
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- spsingh2@ncsu.edu
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executables:
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- vgen
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extensions: []
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extra_rdoc_files: []
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files:
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- .gitignore
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- .rvmrc
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53
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- Gemfile
|
54
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- LICENSE.txt
|
55
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- README.md
|
56
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- Rakefile
|
57
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+
- bin/vgen
|
58
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+
- features/hello.feature
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59
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- features/support/aruba.rb
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60
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- features/support/env.rb
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61
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- lib/verilog_gen.rb
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- lib/verilog_gen/version.rb
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63
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- verilog_gen.gemspec
|
64
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homepage: ''
|
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licenses:
|
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- MIT
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metadata: {}
|
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post_install_message:
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rdoc_options: []
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require_paths:
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- lib
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required_ruby_version: !ruby/object:Gem::Requirement
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requirements:
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- - '>='
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- !ruby/object:Gem::Version
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version: '0'
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required_rubygems_version: !ruby/object:Gem::Requirement
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requirements:
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- - '>='
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- !ruby/object:Gem::Version
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version: '0'
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requirements: []
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rubyforge_project:
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rubygems_version: 2.1.11
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signing_key:
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specification_version: 4
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summary: Generate verilog RTL hierarchy.
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test_files:
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- features/hello.feature
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90
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- features/support/aruba.rb
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91
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- features/support/env.rb
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