udb 0.1.15 → 0.1.16

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 0c4e7059a447d2f815adfb15bfe6152a60e2a238167245bc3fbaf26de73859c3
-  data.tar.gz: fd573fc43f859b0fd40cb3a283015af2aa4a7f33fe1c2c2b1285f6e5fde2a3a9
+  metadata.gz: 642af8189712e586458dbc95aecdec921fff4d765b5914f00c59adf422ee60a0
+  data.tar.gz: 8e914af25855fd5335cee61d48b29b224886c39cb5b63b00530fc0fe0cc83747
 SHA512:
-  metadata.gz: cf76d15fcf97eba3aa58b29fbb4f6a45d486541f1bcba5ca35b3d7b15a67e957e9d60eaf9b7a1e2b7e53eeb4ddf0b6d9f0b1fbbdc6ba89befcfbbb5b1b8804be
-  data.tar.gz: a3051975397d7412e1cd39c2a4e352f2d42763c0d2663fb553198ca9c175725dbf47694f48a56c8615219b5d457a1aed20cb89b1094d75382279dfe23c619d63
+  metadata.gz: 23f4835af0d1fd845ef8c48ddd7dfce7354aa6656ad993ed189234fbe2f43eb01700ec24972336bcc3ddb6e0c41ee609eac4a8f88f6021e388a09e69e2a59834
+  data.tar.gz: 2eb190eecd92203f877366434e3400b58d50007da7dfbdf5745bed97443a4c39d6120624cac2eebcba697ad77ae81bc1eaaca91c60b71dd02daee44768a4e26f

data/.data/cfgs/example_rv64_with_overlay.yaml

@@ -22,6 +22,7 @@ implemented_extensions:
   - [I, "2.1.0"]
   - [H, "1.0.0"]
   - [M, "2.0.0"]
+  - [Zmmul, "1.0.0"]
   - [S, "1.12.0"]
   - [Sm, "1.12.0"]
   - [U, "1.0.0"]

data/.data/cfgs/mc100-32-full-example.yaml

@@ -11,6 +11,7 @@ implemented_extensions:
   - [C, "2.0"]
   - [Zca, "1.0"]
   - [M, "2.0"]
+  - [Zmmul, "1.0"]
   - [Zicsr, "2.0"]
   - [Zicntr, "2.0"]
   - [Smrnmi, "1.0"]

data/.data/cfgs/profile/RVA20S64.yaml

@@ -66,6 +66,8 @@ mandatory_extensions:
   version: "~> 2.0"
 - name: Zifencei
   version: "~> 2.0"
+- name: Zmmul
+  version: "~> 1.0.0"
 non_mandatory_extensions:
 - name: Ssu64xl
   version: "~> 1.0"

data/.data/cfgs/profile/RVA20U64.yaml

@@ -48,6 +48,8 @@ mandatory_extensions:
   version: "~> 2.0"
 - name: Zicsr
   version: "~> 2.0"
+- name: Zmmul
+  version: "~> 1.0.0"
 non_mandatory_extensions:
 - name: Zca
   version: "~> 1.0"

data/.data/cfgs/profile/RVA22S64.yaml

@@ -98,6 +98,8 @@ mandatory_extensions:
   version: "~> 2.0"
 - name: Zkt
   version: "~> 1.0"
+- name: Zmmul
+  version: "~> 1.0.0"
 non_mandatory_extensions:
 - name: Sha
   version: "~> 1.0"

data/.data/cfgs/profile/RVA22U64.yaml

@@ -74,6 +74,8 @@ mandatory_extensions:
   version: "~> 2.0"
 - name: Zkt
   version: "~> 1.0"
+- name: Zmmul
+  version: "~> 1.0.0"
 non_mandatory_extensions:
 - name: V
   version: "~> 1.0"

data/.data/cfgs/profile/RVA23S64.yaml

@@ -144,6 +144,8 @@ mandatory_extensions:
   version: "~> 1.0"
 - name: Zkt
   version: "~> 1.0"
+- name: Zmmul
+  version: "~> 1.0.0"
 - name: Zvbb
   version: "~> 1.0"
 - name: Zve32f

data/.data/cfgs/profile/RVA23U64.yaml

@@ -92,6 +92,8 @@ mandatory_extensions:
   version: "~> 1.0"
 - name: Zkt
   version: "~> 1.0"
+- name: Zmmul
+  version: "~> 1.0.0"
 - name: Zvbb
   version: "~> 1.0"
 - name: Zve32f

data/.data/cfgs/profile/RVB23S64.yaml

@@ -118,6 +118,8 @@ mandatory_extensions:
   version: "~> 1.0"
 - name: Zkt
   version: "~> 1.0"
+- name: Zmmul
+  version: "~> 1.0.0"
 non_mandatory_extensions:
 - name: Sdtrig
   version: "~> 1.0"

data/.data/cfgs/profile/RVB23U64.yaml

@@ -86,6 +86,8 @@ mandatory_extensions:
   version: "~> 1.0"
 - name: Zkt
   version: "~> 1.0"
+- name: Zmmul
+  version: "~> 1.0.0"
 non_mandatory_extensions:
 - name: Supm
   version: "~> 1.0"

data/.data/cfgs/qc_iu.yaml

@@ -12,6 +12,7 @@ implemented_extensions:
   - { name: Smdbltrp, version: "= 1.0" }
   - { name: I, version: "= 2.1" }
   - { name: M, version: "= 2.0" }
+  - { name: Zmmul, version: "= 1.0" }
   - { name: B, version: "= 1.0" }
   - { name: Zbs, version: "= 1.0" }
   - { name: Zbb, version: "= 1.0" }

data/.data/cfgs/rv32-riscv-tests.yaml

@@ -12,6 +12,7 @@ implemented_extensions:
   - [C, "2.0"]
   - [Zca, "1.0.0"]
   - [M, "2.0"]
+  - [Zmmul, "1.0"]
   - [Zicsr, "2.0"]
   - [Zicntr, "2.0"]
   - [Smrnmi, "1.0"]

data/.data/cfgs/rv32-vector.yaml

@@ -16,6 +16,7 @@ implemented_extensions:
   - [D, "2.2.0"]
   - [F, "2.2.0"]
   - [M, "2.0"]
+  - [Zmmul, "1.0"]
   - [Zicsr, "2.0"]
   - [Zicntr, "2.0"]
   - [Smrnmi, "1.0"]

data/.data/cfgs/rv64-riscv-tests.yaml

@@ -11,6 +11,7 @@ implemented_extensions:
   - [I, "2.1"]
   - [C, "2.0"]
   - [M, "2.0"]
+  - [Zmmul, "1.0"]
   - [Zicsr, "2.0"]
   - [Zicntr, "2.0"]
   - [Smrnmi, "1.0"]

data/.data/cfgs/rv64-vector.yaml

@@ -13,6 +13,7 @@ implemented_extensions:
   - [Zca, "1.0.0"]
   - [Zcd, "1.0.0"]
   - [M, "2.0"]
+  - [Zmmul, "1.0"]
   - [Zicsr, "2.0"]
   - [Zicntr, "2.0"]
   - [Smrnmi, "1.0"]

data/.data/spec/std/isa/csr/H/henvcfg.yaml

@@ -258,7 +258,7 @@ fields:
       if (csr_value.CBIE == 0 || csr_value.CBIE == 1 || csr_value.CBIE == 3) {
         return csr_value.CBIE;
       } else {
-        return CSR[menvcfg].CBIE;
+        return CSR[henvcfg].CBIE;
       }
     reset_value: UNDEFINED_LEGAL
   SSE:

data/.data/spec/std/isa/csr/H/htimedeltah.yaml

@@ -29,4 +29,4 @@ fields:
       CSR[htimedelta].DELTA = {csr_value.DELTA, CSR[htimedelta].DELTA[31:0]};
       return csr_value.DELTA;
 sw_read(): |
-  return CSR[htimedelta].DELTA[31:0];
+  return CSR[htimedelta].DELTA[63:32];

data/.data/spec/std/isa/csr/Smctr/vsctrctl.yaml

@@ -225,4 +225,4 @@ sw_read(): |
   if (MCTRCTL_CUSTOM_IMPLEMENTED) {
     mask = mask | (4'b1111 `<< 60);
   }
-  return ($bits(CSR[mctrctl]) & mask);
+  return ($bits(CSR[vsctrctl]) & mask);

data/.data/spec/std/isa/csr/hstateen0h.yaml

@@ -156,4 +156,4 @@ fields:
       `mstateen0.CTR=0`.
     type: RW
     reset_value: 0
-sw_read(): return $bits(CSR[hstateen0])[63:32];
+sw_read(): return CSR[hstateen0].sw_read()[63:32];

data/.data/spec/std/isa/csr/hstateen1h.yaml

@@ -44,4 +44,4 @@ fields:
       The SE0 bit in `hstateen1h` controls access to the `sstateen1` CSR.
     type: RW
     reset_value: UNDEFINED_LEGAL
-sw_read(): return $bits(CSR[hstateen1])[63:32];
+sw_read(): return CSR[hstateen1].sw_read()[63:32];

data/.data/spec/std/isa/csr/hstateen2h.yaml

@@ -44,4 +44,4 @@ fields:
       The SE0 bit in `hstateen2h` controls access to the `sstateen2` CSR.
     type: RW
     reset_value: UNDEFINED_LEGAL
-sw_read(): return $bits(CSR[hstateen2])[63:32];
+sw_read(): return CSR[hstateen2].sw_read()[63:32];

data/.data/spec/std/isa/csr/hstateen3h.yaml

@@ -44,4 +44,4 @@ fields:
       The SE0 bit in `hstateen3h` controls access to the `sstateen3` CSR.
     type: RW
     reset_value: UNDEFINED_LEGAL
-sw_read(): return $bits(CSR[hstateen3])[63:32];
+sw_read(): return CSR[hstateen3].sw_read()[63:32];

data/.data/spec/std/isa/csr/instreth.yaml

@@ -76,6 +76,4 @@ sw_read(): |
     }
   }
 
-  # since the counter may be shared among harts, reads must be handled
-  # as a builtin function
-  return read_mcycle();
+  return CSR[minstret].COUNT[63:32];

data/.data/spec/std/isa/csr/minstreth.yaml

@@ -34,6 +34,6 @@ definedBy:
   allOf:
     - xlen: 32
     - extension:
-        name: Zicntr
+        name: Sm
 sw_read(): |
   return CSR[minstret].COUNT[63:32];

data/.data/spec/std/isa/csr/mstatus.yaml

@@ -71,7 +71,7 @@ fields:
         - extension:
             name: Smdbltrp
     type: RW-H
-    reset_value: UNDEFINED_LEGAL
+    reset_value: 1
   MPELP:
     location: 41
     long_name: M-mode Previous Expected Landing Pad state

data/.data/spec/std/isa/csr/mstatush.yaml

@@ -26,7 +26,7 @@ fields:
     description: |
       see `mstatus.MDT`
     type: RW-H
-    reset_value: UNDEFINED_LEGAL
+    reset_value: 1
     alias: mstatus.MDT
     definedBy:
       extension:

data/.data/spec/std/isa/csr/senvcfg.yaml

@@ -12,7 +12,7 @@ long_name: Supervisor Environment Configuration
 description: |
   Contains fields that control certain characteristics of the U-mode execution environment.
 priv_mode: S
-length: 64
+length: SXLEN
 definedBy:
   extension:
     allOf:

data/.data/spec/std/isa/csr/sepc.yaml

@@ -10,7 +10,7 @@ long_name: Supervisor Exception Program Counter
 address: 0x141
 writable: true
 priv_mode: S
-length: 64
+length: SXLEN
 description: |
   Written with the PC of an instruction on an exception or interrupt taken in (H)S-mode.
 
@@ -20,7 +20,8 @@ definedBy:
     name: S
 fields:
   PC:
-    location: 63-0
+    location_rv32: 31-0
+    location_rv64: 63-0
     description: |
       When a trap is taken into S-mode, `sepc.PC` is written with the virtual address of the
       instruction that was interrupted or that encountered the exception.
@@ -38,7 +39,7 @@ fields:
       When `misa.C` is clear, bit 1 is masked to zero. Writes to bit 1 are still captured, and
       may be visible on the next read with `misa.C` is set.
 
-      Holds bits 63:<%= ext?(:C) ? 2 : 1 %> of the virtual address associated with an exception.
+      Holds bits [SXLEN-1:<%= ext?(:C) ? 2 : 1 %>] of the virtual address associated with an exception.
     type: RW-RH
     sw_write(csr_value): |
       return csr_value.PC & ~64'b1;

data/.data/spec/std/isa/csr/sip.yaml

@@ -15,7 +15,7 @@ description: |
 
   Hypervisor-related interrupts (VS-mode interrupts and Supervisor Guest interrupts) are not reflected
   in `sip` even though those interrupts can be taken in HS-mode. Instead, they are reported through `hip`.
-length: 64
+length: SXLEN
 definedBy:
   extension:
     name: S

data/.data/spec/std/isa/csr/sscratch.yaml

@@ -10,14 +10,15 @@ long_name: Supervisor Scratch Register
 address: 0x140
 writable: true
 priv_mode: S
-length: 64
+length: SXLEN
 description: Scratch register for software use. Bits are not interpreted by hardware.
 definedBy: # actually, defined by RV64, but must implement U-mode for this CSR to exist
   extension:
     name: S
 fields:
   SCRATCH:
-    location: 63-0
+    location_rv32: 31-0
+    location_rv64: 63-0
     description: Scratch value
     type: RW
     reset_value: UNDEFINED_LEGAL

data/.data/spec/std/isa/csr/stval.yaml

@@ -11,13 +11,14 @@ address: 0x143
 writable: true
 description: Holds trap-specific information
 priv_mode: S
-length: 64
+length: SXLEN
 definedBy:
   extension:
     name: S
 fields:
   VALUE:
-    location: 63-0
+    location_rv32: 31-0
+    location_rv64: 63-0
     description: |
       Written with trap-specific information when a trap is taken into S-mode.
 

data/.data/spec/std/isa/csr/stvec.yaml

@@ -10,19 +10,20 @@ long_name: Supervisor Trap Vector
 address: 0x105
 writable: true
 priv_mode: S
-length: 64
+length: SXLEN
 description: Controls where traps jump.
 definedBy:
   extension:
     name: S
 fields:
   BASE:
-    location: 63-2
+    location_rv32: 31-2
+    location_rv64: 63-2
     description: |
       <%- va_size = ext?(:Sv57) ? 57 : (ext?(:Sv48) ? 48 : 39) -%>
-      Bits 63:2 of the virtual address of the exception vector for any trap taken into S-mode.
+      Bits [SXLEN-1:2] of the virtual address of the exception vector for any trap taken into S-mode.
 
-      If the base address is written with a non-canonical address (_i.e._, bits 63:<%= va_size %> do not match bit <%= va_size-1 %>),
+      If the base address is written with a non-canonical address (_i.e._, bits [SXLEN-1:<%= va_size %>] do not match bit <%= va_size-1 %>),
       the write should be ignored.
 
     type: RW-R

data/.data/spec/std/isa/csr/time.yaml

@@ -79,7 +79,7 @@ sw_read(): |
     }
   } else if (mode() == PrivilegeMode::VU) {
     # access in VU mode
-    if (((CSR[hcounteren].TM & CSR[scounteren].TM) == 1'b0) && (CSR[mcounteren].IR == 1'b1)) {
+    if (((CSR[hcounteren].TM & CSR[scounteren].TM) == 1'b0) && (CSR[mcounteren].TM == 1'b1)) {
       raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
     } else if (CSR[mcounteren].TM == 1'b0) {
       raise(ExceptionCode::IllegalInstruction, mode(), $encoding);

data/.data/spec/std/isa/csr/timeh.yaml

@@ -80,7 +80,7 @@ sw_read(): |
     }
   } else if (mode() == PrivilegeMode::VU) {
     # access in VU mode
-    if (((CSR[hcounteren].TM & CSR[scounteren].TM) == 1'b0) && (CSR[mcounteren].IR == 1'b1)) {
+    if (((CSR[hcounteren].TM & CSR[scounteren].TM) == 1'b0) && (CSR[mcounteren].TM == 1'b1)) {
       raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
     } else if (CSR[mcounteren].TM == 1'b0) {
       raise(ExceptionCode::IllegalInstruction, mode(), $encoding);

data/.data/spec/std/isa/csr/vsepc.yaml

@@ -11,7 +11,7 @@ address: 0x241
 writable: true
 virtual_address: 0x141
 priv_mode: VS
-length: 64
+length: VSXLEN
 description: |
   Written with the PC of an instruction on an exception or interrupt taken in VS-mode.
 
@@ -21,7 +21,8 @@ definedBy:
     name: H
 fields:
   PC:
-    location: 63-0
+    location_rv32: 31-0
+    location_rv64: 63-0
     description: |
       When a trap is taken into VS-mode, `vsepc.PC` is written with the virtual address of the
       instruction that was interrupted or that encountered the exception.
@@ -39,14 +40,14 @@ fields:
       When `misa.C` is clear, bit 1 is masked to zero. Writes to bit 1 are still captured, and
       may be visible on the next read with `misa.C` is set.
 
-      Holds bits 63:<%= ext?(:C) ? 2 : 1 %> of the virtual address associated with an exception.
+      Holds bits [VSXLEN-1:<%= ext?(:C) ? 2 : 1 %>] of the virtual address associated with an exception.
     type: RW-RH
     sw_write(csr_value): |
       return csr_value.PC & ~64'b1;
     reset_value: UNDEFINED_LEGAL
 sw_read(): |
   if (implemented?(ExtensionName::C) && CSR[misa].C == 1'b1) {
-    return CSR[sepc].PC & ~64'b1;
+    return CSR[vsepc].PC & ~64'b1;
   } else {
-    return CSR[sepc].PC;
+    return CSR[vsepc].PC;
   }

data/.data/spec/std/isa/csr/vstvec.yaml

@@ -11,19 +11,20 @@ address: 0x205
 writable: true
 virtual_address: 0x105
 priv_mode: VS
-length: 64
+length: VSXLEN
 description: Controls where traps jump.
 definedBy:
   extension:
     name: H
 fields:
   BASE:
-    location: 63-2
+    location_rv32: 31-2
+    location_rv64: 63-2
     description: |
       <%- va_size = ext?(:Sv57) ? 57 : (ext?(:Sv48) ? 48 : 39) -%>
-      Bits 63:2 of the virtual address of the exception vector for any trap taken into VS-mode.
+      Bits [VSXLEN-1:2] of the virtual address of the exception vector for any trap taken into VS-mode.
 
-      If the base address is written with a non-canonical address (_i.e._, bits 63:<%= va_size %> do not match bit <%= va_size-1 %>),
+      If the base address is written with a non-canonical address (_i.e._, bits [VSXLEN-1:<%= va_size %>] do not match bit <%= va_size-1 %>),
       the write should be ignored.
 
     type: RW-R

data/.data/spec/std/isa/ext/M.yaml

@@ -12,6 +12,10 @@ versions:
   - version: "2.0.0"
     state: ratified
     ratification_date: 2019-12
+    requirements:
+      extension:
+        name: Zmmul
+        version: "~> 1.0.0"
 description: |
   This chapter describes the standard integer multiplication and division
   instruction extension, which is named `M` and contains instructions

data/.data/spec/std/isa/ext/Shgatpa.yaml

@@ -26,6 +26,7 @@ requirements:
     implemented?(ExtensionName::Sv39) -> SV39X4_TRANSLATION;
     implemented?(ExtensionName::Sv48) -> SV48X4_TRANSLATION;
     implemented?(ExtensionName::Sv57) -> SV57X4_TRANSLATION;
+    -> GSTAGE_MODE_BARE;
   reason: |
     Shgatpa mandates that or each supported virtual memory scheme SvNN supported in
     `satp`, the corresponding hgatp SvNNx4 mode must be supported.

data/.data/spec/std/isa/ext/Zibi.yaml

@@ -0,0 +1,29 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Zibi
+long_name: Branch with Immediate
+description: |
+  The Zibi extension adds conditional branch instructions that compare an
+  integer register with a small immediate constant.
+
+  Existing conditional branch instructions, such as `beq` and `bne`, compare two
+  integer registers. When a branch compares against a constant, software must
+  otherwise materialize that constant in an integer register before branching,
+  which can increase register pressure and potentially cause register spills and
+  reloads.
+
+  The `beqi` and `bnei` instructions use the B-type instruction format. The
+  instruction bits that would otherwise carry _rs2_ in a B-type branch carry a
+  5-bit _cimm_ field. All _cimm_ encodings are valid: the _cimm_ field is not
+  sign-extended; it decodes to an XLEN-bit comparison constant where `cimm=0`
+  encodes the value -1, and `cimm` values 1 through 31 encode the corresponding
+  positive integer values 1 through 31.
+type: unprivileged
+versions:
+  - version: "0.7.0"
+    state: frozen

data/.data/spec/std/isa/inst/B/roriw.yaml

@@ -41,5 +41,5 @@ operation(): |
 
   XReg xs1_word = X[xs1][31:0];
 
-  XReg unextended_result = (X[xs1] >> shamt) | (X[xs1] << (32 - shamt));
+  XReg unextended_result = (xs1_word >> shamt) | (xs1_word << (32 - shamt));
   X[xd] = {{32{unextended_result[31]}}, unextended_result};

data/.data/spec/std/isa/inst/B/rorw.yaml

@@ -42,5 +42,5 @@ operation(): |
   XReg xs1_word = X[xs1][31:0];
   XReg shamt = X[xs2][4:0];
 
-  XReg unextended_result = (X[xs1] >> shamt) | (X[xs1] << (32 - shamt));
+  XReg unextended_result = (xs1_word >> shamt) | (xs1_word << (32 - shamt));
   X[xd] = {{32{unextended_result[31]}}, unextended_result};

data/.data/spec/std/isa/inst/F/fmv.w.x.yaml

@@ -28,6 +28,9 @@ access:
   vs: always
   vu: always
 data_independent_timing: false
+pseudoinstructions:
+  - when: "true"
+    to: fmv.s.x fd, xs1
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/F/fmv.x.w.yaml

@@ -29,6 +29,9 @@ access:
   vs: always
   vu: always
 data_independent_timing: false
+pseudoinstructions:
+  - when: "true"
+    to: fmv.x.s xd, fs1
 operation(): |
   check_f_ok($encoding);
 

data/.data/spec/std/isa/inst/M/mul.yaml

@@ -22,9 +22,7 @@ description: |
 
 definedBy:
   extension:
-    anyOf:
-      - name: M
-      - name: Zmmul
+    name: Zmmul
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------000-----0110011

data/.data/spec/std/isa/inst/M/mulh.yaml

@@ -21,9 +21,7 @@ description: |
   Microarchitectures may look for that sequence and fuse the operations.
 definedBy:
   extension:
-    anyOf:
-      - name: M
-      - name: Zmmul
+    name: Zmmul
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------001-----0110011

data/.data/spec/std/isa/inst/M/mulhsu.yaml

@@ -21,9 +21,7 @@ description: |
   Microarchitectures may look for that sequence and fuse the operations.
 definedBy:
   extension:
-    anyOf:
-      - name: M
-      - name: Zmmul
+    name: Zmmul
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------010-----0110011

data/.data/spec/std/isa/inst/M/mulhu.yaml

@@ -21,9 +21,7 @@ description: |
   Microarchitectures may look for that sequence and fuse the operations.
 definedBy:
   extension:
-    anyOf:
-      - name: M
-      - name: Zmmul
+    name: Zmmul
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------011-----0110011

data/.data/spec/std/isa/inst/M/mulw.yaml

@@ -22,9 +22,7 @@ definedBy:
   allOf:
     - xlen: 64
     - extension:
-        anyOf:
-          - name: M
-          - name: Zmmul
+        name: Zmmul
 assembly: xd, xs1, xs2
 encoding:
   match: 0000001----------000-----0111011

data/.data/spec/std/isa/inst/Zbb/ctzw.yaml

@@ -36,4 +36,9 @@ operation(): |
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  X[xd] = lowest_set_bit(X[xs1][31:0]);
+  # lowest_set_bit() reports xlen() (64 here) for a zero input, but ctzw must report 32
+  if (X[xs1][31:0] == 0) {
+    X[xd] = 32;
+  } else {
+    X[xd] = lowest_set_bit(X[xs1][31:0]);
+  }

data/.data/spec/std/isa/inst/{Q → Zfa}/fltq.q.yaml

@@ -18,7 +18,7 @@ definedBy:
     allOf:
       - name: Q
       - name: Zfa
-assembly: fd, fs1, fs2
+assembly: xd, fs1, fs2
 encoding:
   match: 1010011----------101-----1010011
   variables:
@@ -26,7 +26,7 @@ encoding:
       location: 24-20
     - name: fs1
       location: 19-15
-    - name: fd
+    - name: xd
       location: 11-7
 access:
   s: always