udb 0.1.15 → 0.1.16

data/.data/spec/std/isa/inst/Zibi/beqi.yaml

@@ -0,0 +1,45 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: beqi
+long_name: Branch if equal immediate
+description: |
+  Branch to PC + offset if the value in register xs1 is equal to the XLEN-bit
+  comparison constant decoded from cimm.
+
+  The cimm field is not sign-extended: cimm == 0 encodes the value -1, and
+  cimm values 1 through 31 encode the corresponding positive integer values.
+
+  Raise a `MisalignedAddress` exception if the branch is taken and PC + offset is
+  misaligned.
+definedBy:
+  extension:
+    name: Zibi
+assembly: xs1, cimm, offset
+encoding:
+  match: "-----------------010-----1100011"
+  variables:
+    - name: offset
+      location: 31|7|30-25|11-8
+      left_shift: 1
+      sign_extend: true
+    - name: cimm
+      location: 24-20
+    - name: xs1
+      location: 19-15
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg lhs = X[xs1];
+  XReg rhs = (cimm == 0) ? {MXLEN{1'b1}} : cimm;
+
+  if (lhs == rhs) {
+    jump_halfword($pc + $signed(offset));
+  }

data/.data/spec/std/isa/inst/Zibi/bnei.yaml

@@ -0,0 +1,45 @@
+# Copyright (c) RISC-V International
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: "inst_schema.json#"
+kind: instruction
+name: bnei
+long_name: Branch if not equal immediate
+description: |
+  Branch to PC + offset if the value in register xs1 is not equal to the XLEN-bit
+  comparison constant decoded from cimm.
+
+  The cimm field is not sign-extended: cimm == 0 encodes the value -1, and
+  cimm values 1 through 31 encode the corresponding positive integer values.
+
+  Raise a `MisalignedAddress` exception if the branch is taken and PC + offset is
+  misaligned.
+definedBy:
+  extension:
+    name: Zibi
+assembly: xs1, cimm, offset
+encoding:
+  match: "-----------------011-----1100011"
+  variables:
+    - name: offset
+      location: 31|7|30-25|11-8
+      left_shift: 1
+      sign_extend: true
+    - name: cimm
+      location: 24-20
+    - name: xs1
+      location: 19-15
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+operation(): |
+  XReg lhs = X[xs1];
+  XReg rhs = (cimm == 0) ? {MXLEN{1'b1}} : cimm;
+
+  if (lhs != rhs) {
+    jump_halfword($pc + $signed(offset));
+  }

data/.data/spec/std/isa/inst/Zicbom/cbo.inval.yaml

@@ -52,7 +52,7 @@ description: |
   `cbo.inval` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`.
 
   <%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%>
-  Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.zero` has UNSPECIFIED behavior.
+  Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.inval` has UNSPECIFIED behavior.
   <%- end -%>
 
   Invalidate operations are treated as stores for page and access permissions. If permission checks fail,

data/.data/spec/std/isa/inst/Zicfiss/ssamoswap.d.yaml

@@ -12,7 +12,7 @@ description: |
 definedBy:
   extension:
     name: Zicfiss
-assembly: xd, xs2, xs1
+assembly: xd, xs2, (xs1)
 encoding:
   match: 01001------------011-----0101111
   variables:

data/.data/spec/std/isa/inst/Zicfiss/ssamoswap.w.yaml

@@ -12,7 +12,7 @@ description: |
 definedBy:
   extension:
     name: Zicfiss
-assembly: xd, xs2, xs1
+assembly: xd, xs2, (xs1)
 encoding:
   match: 01001------------010-----0101111
   variables:

data/.data/spec/std/isa/inst/Zicfiss/sspopchk.yaml

@@ -0,0 +1,63 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: sspopchk
+long_name: Shadow Stack Pop and Check
+description: |
+  SSPOPCHK pops a value from the shadow stack and checks it against link
+  register `xs1`. The encoding restricts `xs1` to `x1` or `x5`.
+
+  This instruction uses the `mop.r.28` codepoint provided by Zimop.
+definedBy:
+  extension:
+    name: Zicfiss
+assembly: xs1
+encoding:
+  match: "110011011100-----100000001110011"
+  variables:
+    - name: xs1
+      location: 19-15
+      not:
+        [
+          0,
+          2,
+          3,
+          4,
+          6,
+          7,
+          8,
+          9,
+          10,
+          11,
+          12,
+          13,
+          14,
+          15,
+          16,
+          17,
+          18,
+          19,
+          20,
+          21,
+          22,
+          23,
+          24,
+          25,
+          26,
+          27,
+          28,
+          29,
+          30,
+          31,
+        ]
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zicfiss/sspush.yaml

@@ -0,0 +1,63 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: sspush
+long_name: Shadow Stack Push
+description: |
+  SSPUSH pushes the value of link register `xs2` to the shadow stack.
+  The encoding restricts `xs2` to `x1` or `x5`.
+
+  This instruction uses the `mop.rr.7` codepoint provided by Zimop.
+definedBy:
+  extension:
+    name: Zicfiss
+assembly: xs2
+encoding:
+  match: "1100111-----00000100000001110011"
+  variables:
+    - name: xs2
+      location: 24-20
+      not:
+        [
+          0,
+          2,
+          3,
+          4,
+          6,
+          7,
+          8,
+          9,
+          10,
+          11,
+          12,
+          13,
+          14,
+          15,
+          16,
+          17,
+          18,
+          19,
+          20,
+          21,
+          22,
+          23,
+          24,
+          25,
+          26,
+          27,
+          28,
+          29,
+          30,
+          31,
+        ]
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

data/.data/spec/std/isa/inst/Zimop/mop.r.28.yaml

@@ -33,8 +33,7 @@ access:
   vu: always
 data_independent_timing: false
 hints:
-  - { $ref: inst/Zicfiss/sspopchk.x1.yaml# }
-  - { $ref: inst/Zicfiss/sspopchk.x5.yaml# }
+  - { $ref: inst/Zicfiss/sspopchk.yaml# }
   - { $ref: inst/Zicfiss/ssrdp.yaml# }
 operation(): |
   X[xd] = 0;

data/.data/spec/std/isa/inst/Zimop/mop.r.N.layout

@@ -50,8 +50,7 @@ access:
 data_independent_timing: false
 <% if n == 28 -%>
 hints:
-  - { $ref: inst/Zicfiss/sspopchk.x1.yaml# }
-  - { $ref: inst/Zicfiss/sspopchk.x5.yaml# }
+  - { $ref: inst/Zicfiss/sspopchk.yaml# }
   - { $ref: inst/Zicfiss/ssrdp.yaml# }
 <% end -%>
 operation(): |

data/.data/spec/std/isa/inst/Zimop/mop.rr.7.yaml

@@ -36,7 +36,6 @@ access:
   vu: always
 data_independent_timing: false
 hints:
-  - { $ref: inst/Zicfiss/sspush.x1.yaml# }
-  - { $ref: inst/Zicfiss/sspush.x5.yaml# }
+  - { $ref: inst/Zicfiss/sspush.yaml# }
 operation(): |
   X[xd] = 0;

data/.data/spec/std/isa/inst/Zimop/mop.rr.N.layout

@@ -51,8 +51,7 @@ access:
 data_independent_timing: false
 <% if n == 7 -%>
 hints:
-  - { $ref: inst/Zicfiss/sspush.x1.yaml# }
-  - { $ref: inst/Zicfiss/sspush.x5.yaml# }
+  - { $ref: inst/Zicfiss/sspush.yaml# }
 <% end -%>
 operation(): |
   X[xd] = 0;

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vandn.vv.yaml

@@ -11,7 +11,7 @@ description: |
   Performs a bitwise AND operation between vector register vs2 and the bitwise NOT of vector register vs1, storing results in vector register vd according to mask vm.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, vs1, vm
 encoding:
   match: 000001-----------000-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vandn.vx.yaml

@@ -11,7 +11,7 @@ description: |
   Performs a bitwise AND operation between vector register vs2 and the bitwise NOT of scalar register xs1, storing results in vector register vd according to mask vm.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, xs1, vm
 encoding:
   match: 000001-----------100-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vbrev8.v.yaml

@@ -11,7 +11,7 @@ description: |
   Reverses the byte order within each element of vector register vs2, storing results in vector register vd according to mask vm. Similar to vrev8.v but with different encoding.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, vm
 encoding:
   match: 010010------01000010-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vrev8.v.yaml

@@ -11,7 +11,7 @@ description: |
   Reverses the byte order within each element of vector register vs2, storing results in vector register vd according to mask vm. This is equivalent to a byte-level reversal of each element.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, vm
 encoding:
   match: 010010------01001010-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vrol.vv.yaml

@@ -11,7 +11,7 @@ description: |
   Rotates each element in vector register vs2 left by the amount specified in vector register vs1, storing results in vector register vd according to mask vm. The rotation amount is taken modulo the element width.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, vs1, vm
 encoding:
   match: 010101-----------000-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vrol.vx.yaml

@@ -11,7 +11,7 @@ description: |
   Rotates each element in vector register vs2 left by the amount specified in scalar register xs1, storing results in vector register vd according to mask vm. The rotation amount is taken modulo the element width.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, xs1, vm
 encoding:
   match: 010101-----------100-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vror.vi.yaml

@@ -11,7 +11,7 @@ description: |
   Rotates each element in vector register vs2 right by the immediate shift amount, storing results in vector register vd according to mask vm. The rotation amount is taken modulo the element width.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, imm, vm
 encoding:
   match: 01010------------011-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vror.vv.yaml

@@ -11,7 +11,7 @@ description: |
   Rotates each element in vector register vs2 right by the amount specified in vector register vs1, storing results in vector register vd according to mask vm. The rotation amount is taken modulo the element width.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, vs1, vm
 encoding:
   match: 010100-----------000-----1010111

data/.data/spec/std/isa/inst/{Zvbb → Zvkb}/vror.vx.yaml

@@ -11,7 +11,7 @@ description: |
   Rotates each element in vector register vs2 right by the amount specified in scalar register xs1, storing results in vector register vd according to mask vm. The rotation amount is taken modulo the element width.
 definedBy:
   extension:
-    name: Zvbb
+    name: Zvkb
 assembly: vd, vs2, xs1, vm
 encoding:
   match: 010100-----------100-----1010111

data/.data/spec/std/isa/isa/globals.isa

@@ -3144,7 +3144,7 @@ function mstatus_sd_reset_value
       fs_value = (!implemented?(ExtensionName::F)) ? 0 : MSTATUS_FS_LEGAL_VALUES[0];
     }
     if ((!implemented?(ExtensionName::V)) || ($array_size(MSTATUS_VS_LEGAL_VALUES) == 1)) {
-      fs_value = (!implemented?(ExtensionName::V)) ? 0 : MSTATUS_VS_LEGAL_VALUES[0];
+      vs_value = (!implemented?(ExtensionName::V)) ? 0 : MSTATUS_VS_LEGAL_VALUES[0];
     }
 
     return ((fs_value == 3) || (vs_value == 3)) ? 1 : 0;

data/.data/spec/std/isa/isa/util.idl

@@ -73,9 +73,9 @@ function highest_set_bit {
     or -1 if value is zero.
   }
   body {
-    for (Bits<8> i=xlen()-1; i >= 0; i--) {
-      if (value[i] == 1) {
-        return i;
+    for (Bits<8> i=xlen(); i > 0; i--) {
+      if (value[i-1] == 1) {
+        return i-1;
       }
     }
 

data/.data/spec/std/isa/param/COUNTINHIBIT_EN.yaml

@@ -25,6 +25,15 @@ schema:
     type: boolean
   maxItems: 32
   minItems: 32
+
+requirements:
+  idl(): |
+    for (U32 i = 3; i < 32; i++) {
+      (!HPM_COUNTER_EN[i]) -> !COUNTINHIBIT_EN[i];
+    }
+  reason: |
+    When mhpmcounter[i] is not implemented, it cannot be inhibited.
+
 definedBy:
   allOf:
     - extension:

data/.data/spec/std/isa/param/HCONTEXT_AVAILABLE.yaml

@@ -8,7 +8,7 @@ kind: parameter
 name: HCONTEXT_AVAILABLE
 description: |
   Specifies if HCONTEXT is available
-long_name: TODO
+long_name: HCONTEXT Availability
 schema:
   type: boolean
 definedBy:

data/.data/spec/std/isa/param/MUTABLE_MISA_H.yaml

@@ -11,7 +11,7 @@ description:
   `misa.H` bit.
 
   "
-long_name: TODO
+long_name: "`misa.H` mutability"
 schema:
   type: boolean
 requirements:

data/.data/spec/std/isa/param/MUTABLE_MISA_S.yaml

@@ -11,7 +11,7 @@ description:
   `misa.S` bit.
 
   "
-long_name: TODO
+long_name: "`misa.S` mutability"
 schema:
   type: boolean
 requirements:

data/lib/udb/config.rb

@@ -238,7 +238,7 @@ module Udb
     def initialize(data, info)
       super(data, info)
 
-      @param_values = @data.key?("params") ? @data["params"] : [].freeze
+      @param_values = @data.key?("params") ? @data["params"] : {}.freeze
 
       @mxlen = @data.dig("params", "MXLEN")
 

data/lib/udb/version.rb

@@ -5,5 +5,5 @@
 # frozen_string_literal: true
 
 module Udb
-  def self.version = "0.1.15"
+  def self.version = "0.1.16"
 end