udb 0.1.4 → 0.1.6

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 7f633f98551a4aa2c5d06e7d0be863a75ca5d4809c9ca5da6588969608395792
-  data.tar.gz: 9a0d1549e91a1267534f0a9579d94b1ee4e3de41eb3bafe23bd0c9be5b1961d8
+  metadata.gz: e3ee0e5cbe7e1f156b670b2851038ac508058f5ded02fcfa77b1d37dfd3b2801
+  data.tar.gz: d29e24404ee97a185b1d77a364e6d9f62d7d803e6f5cdb8f023554e61610f9e0
 SHA512:
-  metadata.gz: d3a982c3050f9de63c98daee99156d70d40bef14dc7f91ca2b4ecd8f8635aba9c1b138a4d876726400b4feebd77848fa456dd23834af6fb12b0333ecea368498
-  data.tar.gz: 308312a745f2187e722b796eeb7b2c465119bf1f982bb4361066bd624b95775bbbde6ec2604cfd08846a86d2a43646ae0836e561cd0730cdc97f1812bf0aedab
+  metadata.gz: da552e97506e8c03646f6d3c8d9da8dc6ee4d69f4d73d4766595d831ae92e7cfc12930bb71b42853582ad94f14e23c08c5b2912da1f522ed5d209d6f573f8717
+  data.tar.gz: 4de7021d90135149aa34fcf3dc9c1028b41a21eb7fcc7a7fbd0d5afb9bbc5b71398a37e57a969196ba3daafebfaa9465fc82b849fe0cf3d7b66e58f5fca099c4

data/.data/cfgs/mc100-32-full-example.yaml

@@ -161,38 +161,3 @@ params:
       false,
       false,
     ]
-  SCOUNTENABLE_EN:
-    [
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-      false,
-    ]

data/.data/cfgs/qc_iu.yaml

@@ -115,39 +115,6 @@ params:
     - false # HPM29
     - false # HPM30
     - false # HPM31
-  SCOUNTENABLE_EN:
-    - false # CY
-    - false # empty
-    - false # IR
-    - false # HPM3
-    - false # HPM4
-    - false # HPM5
-    - false # HPM6
-    - false # HPM7
-    - false # HPM8
-    - false # HPM9
-    - false # HPM10
-    - false # HPM11
-    - false # HPM12
-    - false # HPM13
-    - false # HPM14
-    - false # HPM15
-    - false # HPM16
-    - false # HPM17
-    - false # HPM18
-    - false # HPM19
-    - false # HPM20
-    - false # HPM21
-    - false # HPM22
-    - false # HPM23
-    - false # HPM24
-    - false # HPM25
-    - false # HPM26
-    - false # HPM27
-    - false # HPM28
-    - false # HPM29
-    - false # HPM30
-    - false # HPM31
   COUNTINHIBIT_EN:
     - true # CY
     - false # empty

data/.data/cfgs/rv32-riscv-tests.yaml

@@ -19,6 +19,8 @@ implemented_extensions:
   - [U, "1.0.0"]
   - [Zifencei, "2.0.0"]
   - [Sv32, "1.11.0"]
+  - [F, "2.2.0"]
+  - [Zcf, "1.0"]
 
 params:
   MXLEN: 32
@@ -191,7 +193,7 @@ params:
   TRAP_ON_ECALL_FROM_S: true
   TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY: false
   MSTATUS_VS_LEGAL_VALUES: [0]
-  MSTATUS_FS_LEGAL_VALUES: [0]
+  MSTATUS_FS_LEGAL_VALUES: [3, 2, 1, 0]
   MSTATUS_TVM_IMPLEMENTED: false
   NUM_PMP_ENTRIES: 16
   PMP_GRANULARITY: 12
@@ -240,3 +242,5 @@ params:
   # MSTATEEN_CSRIND_TYPE: rw
   # MSTATEEN_IMSIC_TYPE: rw
   # MSTATEEN_JVT_TYPE: rw
+  HW_MSTATUS_FS_DIRTY_UPDATE: precise
+  MUTABLE_MISA_F: false

data/.data/cfgs/rv64-riscv-tests.yaml

@@ -19,6 +19,7 @@ implemented_extensions:
   - [Zifencei, "2.0.0"]
   - [Sv39, "1.11.0"]
   - [Zca, "1.0.0"]
+  - [F, "2.2.0"]
 
 params:
   MXLEN: 64
@@ -191,7 +192,7 @@ params:
   TRAP_ON_ECALL_FROM_U: true
   TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY: false
   MSTATUS_VS_LEGAL_VALUES: [0]
-  MSTATUS_FS_LEGAL_VALUES: [0]
+  MSTATUS_FS_LEGAL_VALUES: [3, 2, 1, 0]
   MSTATUS_TVM_IMPLEMENTED: false
   NUM_PMP_ENTRIES: 16
   PMP_GRANULARITY: 12
@@ -199,6 +200,8 @@ params:
   U_MODE_ENDIANNESS: little
   UXLEN: [64]
   MSTATEEN_ENVCFG_TYPE: rw
+  HW_MSTATUS_FS_DIRTY_UPDATE: precise
+  MUTABLE_MISA_F: false
   HPM_COUNTER_EN:
     [
       false,

data/.data/spec/std/isa/inst/F/fadd.s.yaml

@@ -34,4 +34,19 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode mode = rm_to_mode(rm, $encoding);
-  f[fd] = f32_add(f[fs1], f[fs2], mode);
+  Bits<32> a = f[fs1];
+  Bits<32> b = f[fs2];
+
+  if (implemented?(ExtensionName::D)) {
+    # check for incorrectly NaN-boxed inputs
+    if (f[fs1][63:32] != 32'hffffffff) {
+      a = SP_CANONICAL_NAN;
+    }
+    if (f[fs2][63:32] != 32'hffffffff) {
+      b = SP_CANONICAL_NAN;
+    }
+  }
+
+  f[fd] = f32_add(a, b, mode);
+
+  mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fclass.s.yaml

@@ -53,6 +53,13 @@ operation(): |
 
   Bits<32> sp_value = f[fs1][31:0];
 
+  if (implemented?(ExtensionName::D)) {
+    # check for an incorrectly NaN-boxed value
+    if (f[fs1][63:32] != 32'hffffffff) {
+      sp_value = SP_CANONICAL_NAN;
+    }
+  }
+
   if (is_sp_neg_inf?(sp_value)) {
     X[xd] = 1 << 0;
   } else if (is_sp_neg_norm?(sp_value)) {

data/.data/spec/std/isa/inst/F/fcvt.l.s.yaml

@@ -32,3 +32,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
+  X[xd] = f32_to_i64(f[fs1], rounding_mode);

data/.data/spec/std/isa/inst/F/fcvt.lu.s.yaml

@@ -32,3 +32,6 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
+  X[xd] = f32_to_ui64(f[fs1], rounding_mode);

data/.data/spec/std/isa/inst/F/fcvt.s.l.yaml

@@ -32,3 +32,7 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
+  f[fd] = i64_to_f32(X[xs1], rounding_mode);
+  mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fcvt.s.lu.yaml

@@ -31,3 +31,7 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
+  f[fd] = ui64_to_f32(X[xs1], rounding_mode);
+  mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fcvt.w.s.yaml

@@ -60,4 +60,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  X[xd] = f32_to_i32(f[fs1], rounding_mode);
+  X[xd] = $signed(f32_to_i32(f[fs1], rounding_mode));

data/.data/spec/std/isa/inst/F/fcvt.wu.s.yaml

@@ -59,4 +59,4 @@ data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-  X[xd] = f32_to_ui32(f[fs1], rounding_mode);
+  X[xd] = $signed(f32_to_ui32(f[fs1], rounding_mode));

data/.data/spec/std/isa/inst/F/fdiv.s.yaml

@@ -32,3 +32,7 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode mode = rm_to_mode(rm, $encoding);
+  f[fd] = f32_div(f[fs1], f[fs2], mode);
+  mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/feq.s.yaml

@@ -35,7 +35,7 @@ operation(): |
   check_f_ok($encoding);
 
   Bits<32> sp_value_a = f[fs1][31:0];
-  Bits<32> sp_value_b = f[fs1][31:0];
+  Bits<32> sp_value_b = f[fs2][31:0];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {

data/.data/spec/std/isa/inst/F/fle.s.yaml

@@ -36,15 +36,22 @@ operation(): |
 
   Bits<32> sp_value_a = f[fs1][31:0];
   Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<1> sign_a = sp_value_a[31];
+  Bits<1> sign_b = sp_value_b[31];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
-    if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
-      set_fp_flag(FpFlag::NV);
-    }
+    set_fp_flag(FpFlag::NV);
     X[xd] = 0;
   } else {
-    X[xd] = (
-      (sp_value_a == sp_value_b)
-      || ((sp_value_a | sp_value_b)[30:0] == 0) # pos 0 is equal to neg zero
-    ) ? 1 : 0;
+    if (sign_a != sign_b) {
+      X[xd] = (
+        (sign_a == 1) ||  # b is pos and a neg
+        ((sp_value_a[30:0] | sp_value_b[30:0]) == 0) # both are zero (one pos, one neg)
+      ) ? 1 : 0;
+    } else {
+      X[xd] = (
+        (sp_value_a == sp_value_b) || # a and b are equal
+        (sign_a ^ ((sp_value_a < sp_value_b) ? 1 : 0)) == 1 # a < b
+      ) ? 1 : 0;
+    }
   }

data/.data/spec/std/isa/inst/F/fleq.s.yaml

@@ -30,3 +30,33 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+
+  Bits<32> sp_value_a = f[fs1][31:0];
+  Bits<32> sp_value_b = f[fs2][31:0];
+
+  if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
+    # Quiet comparison: only set NV for signaling NaN
+    if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
+      set_fp_flag(FpFlag::NV);
+    }
+    X[xd] = 0;
+  } else {
+    Boolean sign_a = sp_value_a[31] == 1;
+    Boolean sign_b = sp_value_b[31] == 1;
+
+    # Check equality first (including -0.0 == +0.0)
+    Boolean a_eq_b =
+      (sp_value_a == sp_value_b)
+      || ((sp_value_a | sp_value_b)[30:0] == 0);
+
+    # Check a < b
+    Boolean a_lt_b;
+    if (sign_a != sign_b) {
+      a_lt_b = sign_a && ((sp_value_a[30:0] | sp_value_b[30:0]) != 0);
+    } else {
+      a_lt_b = (sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b));
+    }
+
+    X[xd] = (a_lt_b || a_eq_b) ? 1 : 0;
+  }

data/.data/spec/std/isa/inst/F/flt.s.yaml

@@ -36,17 +36,22 @@ operation(): |
 
   Bits<32> sp_value_a = f[fs1][31:0];
   Bits<32> sp_value_b = f[fs2][31:0];
+  Bits<1> sign_a = sp_value_a[31];
+  Bits<1> sign_b = sp_value_b[31];
 
   if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
     set_fp_flag(FpFlag::NV);
     X[xd] = 0;
   } else {
-    Boolean sign_a = sp_value_a[31] == 1;
-    Boolean sign_b = sp_value_b[31] == 1;
-
-    Boolean a_lt_b =
-      (sign_a != sign_b)
-        ? (sign_a && ((sp_value_a[30:0] | sp_value_b[30:0]) != 0)) # opposite sign, a is negative. a is less than b as long as both are not zero
-        : ((sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b)));
-    X[xd] = a_lt_b ? 1 : 0;
+    if (sign_a != sign_b) {
+      X[xd] = (
+        (sign_a == 1) # a is neg and b is pos
+        && ((sp_value_a[30:0] | sp_value_b[30:0]) != 0) # a and b are not both zero
+       ) ? 1 : 0;
+    } else {
+      X[xd] = (
+        (sp_value_a != sp_value_b) # a and b are not equal
+        && ((sign_a ^ ((sp_value_a < sp_value_b) ? 1 : 0)) != 0)# a < b
+      ) ? 1 : 0;
+    }
   }

data/.data/spec/std/isa/inst/F/fltq.s.yaml

@@ -30,3 +30,24 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+
+  Bits<32> sp_value_a = f[fs1][31:0];
+  Bits<32> sp_value_b = f[fs2][31:0];
+
+  if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
+    # Quiet comparison: only set NV for signaling NaN
+    if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
+      set_fp_flag(FpFlag::NV);
+    }
+    X[xd] = 0;
+  } else {
+    Boolean sign_a = sp_value_a[31] == 1;
+    Boolean sign_b = sp_value_b[31] == 1;
+
+    Boolean a_lt_b =
+      (sign_a != sign_b)
+        ? (sign_a && ((sp_value_a[30:0] | sp_value_b[30:0]) != 0))
+        : ((sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b)));
+    X[xd] = a_lt_b ? 1 : 0;
+  }

data/.data/spec/std/isa/inst/F/fmadd.s.yaml

@@ -33,3 +33,7 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode mode = rm_to_mode(rm, $encoding);
+  f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], F32MulAddOp::Softfloat_mulAdd_addC, mode);
+  mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmax.s.yaml

@@ -39,3 +39,33 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+
+  Bits<32> sp_value_a = f[fs1][31:0];
+  Bits<32> sp_value_b = f[fs2][31:0];
+
+  if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
+    if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
+      set_fp_flag(FpFlag::NV);
+    }
+    # If both are NaN, return canonical NaN; otherwise return the non-NaN operand
+    if (is_sp_nan?(sp_value_a) && is_sp_nan?(sp_value_b)) {
+      f[fd] = SP_CANONICAL_NAN;
+    } else if (is_sp_nan?(sp_value_a)) {
+      f[fd] = sp_value_b;
+    } else {
+      f[fd] = sp_value_a;
+    }
+  } else {
+    Boolean sign_a = sp_value_a[31] == 1;
+    Boolean sign_b = sp_value_b[31] == 1;
+    Boolean a_lt_b;
+    if (sign_a != sign_b) {
+      # -0.0 is considered less than +0.0, so it's not a special case
+      a_lt_b = sign_a;
+    } else {
+      a_lt_b = (sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b));
+    }
+    f[fd] = a_lt_b ? sp_value_b : sp_value_a;
+  }
+  mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmin.s.yaml

@@ -39,3 +39,33 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+
+  Bits<32> sp_value_a = f[fs1][31:0];
+  Bits<32> sp_value_b = f[fs2][31:0];
+
+  if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
+    if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
+      set_fp_flag(FpFlag::NV);
+    }
+    # If both are NaN, return canonical NaN; otherwise return the non-NaN operand
+    if (is_sp_nan?(sp_value_a) && is_sp_nan?(sp_value_b)) {
+      f[fd] = SP_CANONICAL_NAN;
+    } else if (is_sp_nan?(sp_value_a)) {
+      f[fd] = sp_value_b;
+    } else {
+      f[fd] = sp_value_a;
+    }
+  } else {
+    Boolean sign_a = sp_value_a[31] == 1;
+    Boolean sign_b = sp_value_b[31] == 1;
+    Boolean a_lt_b;
+    if (sign_a != sign_b) {
+      # -0.0 is considered less than +0.0, so it's not a special case
+      a_lt_b = sign_a;
+    } else {
+      a_lt_b = (sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b));
+    }
+    f[fd] = a_lt_b ? sp_value_a : sp_value_b;
+  }
+  mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmsub.s.yaml

@@ -33,3 +33,7 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode mode = rm_to_mode(rm, $encoding);
+  f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], F32MulAddOp::Softfloat_mulAdd_subC, mode);
+  mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fmul.s.yaml

@@ -32,3 +32,7 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode mode = rm_to_mode(rm, $encoding);
+  f[fd] = f32_mul(f[fs1], f[fs2], mode);
+  mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fnmadd.s.yaml

@@ -34,3 +34,10 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode mode = rm_to_mode(rm, $encoding);
+  # fnmadd: -(fs1 * fs2) - fs3 = -(fs1 * fs2) + (-fs3)
+  # Negate fs3 by flipping its sign bit, then use subProd op
+  Bits<32> fs3_negated = f[fs3][31:0] ^ 32'h80000000;
+  f[fd] = f32_muladd(f[fs1], f[fs2], fs3_negated, F32MulAddOp::Softfloat_mulAdd_subProd, mode);
+  mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fnmsub.s.yaml

@@ -34,3 +34,7 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode mode = rm_to_mode(rm, $encoding);
+  f[fd] = f32_muladd(f[fs1], f[fs2], f[fs3], F32MulAddOp::Softfloat_mulAdd_subProd, mode);
+  mark_f_state_dirty();

data/.data/spec/std/isa/inst/F/fsqrt.s.yaml

@@ -29,3 +29,7 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
+  check_f_ok($encoding);
+  RoundingMode mode = rm_to_mode(rm, $encoding);
+  f[fd] = f32_sqrt(f[fs1], mode);
+  mark_f_state_dirty();