udb 0.1.2 → 0.1.4

data/.data/spec/std/isa/inst/V/vmsle.vi.yaml

@@ -31,47 +31,3 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-
-# SPDX-SnippetBegin
-# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
-# SPDX-License-Identifier: BSD-2-Clause
-sail(): |
-  {
-    let SEW      = get_sew();
-    let LMUL_pow = get_lmul_pow();
-    let num_elem = get_num_elem(LMUL_pow, SEW);
-
-    if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };
-
-    let 'n = num_elem;
-    let 'm = SEW;
-
-    let vm_val  : vector('n, dec, bool)     = read_vmask(num_elem, vm, 0b00000);
-    let imm_val : bits('m)                  = sign_extend(simm);
-    let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
-    let vd_val  : vector('n, dec, bool)     = read_vmask(num_elem, 0b0, vd);
-    result      : vector('n, dec, bool)     = undefined;
-    mask        : vector('n, dec, bool)     = undefined;
-
-    (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
-
-    foreach (i from 0 to (num_elem - 1)) {
-      if mask[i] then {
-        let res : bool = match funct6 {
-          VICMP_VMSEQ    => vs2_val[i] == imm_val,
-          VICMP_VMSNE    => vs2_val[i] != imm_val,
-          VICMP_VMSLEU   => unsigned(vs2_val[i]) <= unsigned(imm_val),
-          VICMP_VMSLE    => signed(vs2_val[i]) <= signed(imm_val),
-          VICMP_VMSGTU   => unsigned(vs2_val[i]) > unsigned(imm_val),
-          VICMP_VMSGT    => signed(vs2_val[i]) > signed(imm_val)
-        };
-        result[i] = res
-      }
-    };
-
-    write_vmask(num_elem, vd, result);
-    vstart = zeros();
-    RETIRE_SUCCESS
-  }
-
-# SPDX-SnippetEnd

data/.data/spec/std/isa/inst/V/vmsle.vv.yaml

@@ -31,47 +31,3 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-
-# SPDX-SnippetBegin
-# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
-# SPDX-License-Identifier: BSD-2-Clause
-sail(): |
-  {
-    let SEW      = get_sew();
-    let LMUL_pow = get_lmul_pow();
-    let num_elem = get_num_elem(LMUL_pow, SEW);
-
-    if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };
-
-    let 'n = num_elem;
-    let 'm = SEW;
-
-    let vm_val  : vector('n, dec, bool)     = read_vmask(num_elem, vm, 0b00000);
-    let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);
-    let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
-    let vd_val  : vector('n, dec, bool)     = read_vmask(num_elem, 0b0, vd);
-    result      : vector('n, dec, bool)     = undefined;
-    mask        : vector('n, dec, bool)     = undefined;
-
-    (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
-
-    foreach (i from 0 to (num_elem - 1)) {
-      if mask[i] then {
-        let res : bool = match funct6 {
-          VVCMP_VMSEQ    => vs2_val[i] == vs1_val[i],
-          VVCMP_VMSNE    => vs2_val[i] != vs1_val[i],
-          VVCMP_VMSLTU   => unsigned(vs2_val[i]) < unsigned(vs1_val[i]),
-          VVCMP_VMSLT    => signed(vs2_val[i]) < signed(vs1_val[i]),
-          VVCMP_VMSLEU   => unsigned(vs2_val[i]) <= unsigned(vs1_val[i]),
-          VVCMP_VMSLE    => signed(vs2_val[i]) <= signed(vs1_val[i])
-        };
-        result[i] = res
-      }
-    };
-
-    write_vmask(num_elem, vd, result);
-    vstart = zeros();
-    RETIRE_SUCCESS
-  }
-
-# SPDX-SnippetEnd

data/.data/spec/std/isa/inst/V/vmsle.vx.yaml

@@ -31,49 +31,3 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-
-# SPDX-SnippetBegin
-# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
-# SPDX-License-Identifier: BSD-2-Clause
-sail(): |
-  {
-    let SEW      = get_sew();
-    let LMUL_pow = get_lmul_pow();
-    let num_elem = get_num_elem(LMUL_pow, SEW);
-
-    if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };
-
-    let 'n = num_elem;
-    let 'm = SEW;
-
-    let vm_val  : vector('n, dec, bool)     = read_vmask(num_elem, vm, 0b00000);
-    let rs1_val : bits('m)                  = get_scalar(rs1, SEW);
-    let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
-    let vd_val  : vector('n, dec, bool)     = read_vmask(num_elem, 0b0, vd);
-    result      : vector('n, dec, bool)     = undefined;
-    mask        : vector('n, dec, bool)     = undefined;
-
-    (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
-
-    foreach (i from 0 to (num_elem - 1)) {
-      if mask[i] then {
-        let res : bool = match funct6 {
-          VXCMP_VMSEQ    => vs2_val[i] == rs1_val,
-          VXCMP_VMSNE    => vs2_val[i] != rs1_val,
-          VXCMP_VMSLTU   => unsigned(vs2_val[i]) < unsigned(rs1_val),
-          VXCMP_VMSLT    => signed(vs2_val[i]) < signed(rs1_val),
-          VXCMP_VMSLEU   => unsigned(vs2_val[i]) <= unsigned(rs1_val),
-          VXCMP_VMSLE    => signed(vs2_val[i]) <= signed(rs1_val),
-          VXCMP_VMSGTU   => unsigned(vs2_val[i]) > unsigned(rs1_val),
-          VXCMP_VMSGT    => signed(vs2_val[i]) > signed(rs1_val)
-        };
-        result[i] = res
-      }
-    };
-
-    write_vmask(num_elem, vd, result);
-    vstart = zeros();
-    RETIRE_SUCCESS
-  }
-
-# SPDX-SnippetEnd

data/.data/spec/std/isa/inst/V/vmsleu.vi.yaml

@@ -31,47 +31,3 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-
-# SPDX-SnippetBegin
-# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
-# SPDX-License-Identifier: BSD-2-Clause
-sail(): |
-  {
-    let SEW      = get_sew();
-    let LMUL_pow = get_lmul_pow();
-    let num_elem = get_num_elem(LMUL_pow, SEW);
-
-    if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };
-
-    let 'n = num_elem;
-    let 'm = SEW;
-
-    let vm_val  : vector('n, dec, bool)     = read_vmask(num_elem, vm, 0b00000);
-    let imm_val : bits('m)                  = sign_extend(simm);
-    let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
-    let vd_val  : vector('n, dec, bool)     = read_vmask(num_elem, 0b0, vd);
-    result      : vector('n, dec, bool)     = undefined;
-    mask        : vector('n, dec, bool)     = undefined;
-
-    (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
-
-    foreach (i from 0 to (num_elem - 1)) {
-      if mask[i] then {
-        let res : bool = match funct6 {
-          VICMP_VMSEQ    => vs2_val[i] == imm_val,
-          VICMP_VMSNE    => vs2_val[i] != imm_val,
-          VICMP_VMSLEU   => unsigned(vs2_val[i]) <= unsigned(imm_val),
-          VICMP_VMSLE    => signed(vs2_val[i]) <= signed(imm_val),
-          VICMP_VMSGTU   => unsigned(vs2_val[i]) > unsigned(imm_val),
-          VICMP_VMSGT    => signed(vs2_val[i]) > signed(imm_val)
-        };
-        result[i] = res
-      }
-    };
-
-    write_vmask(num_elem, vd, result);
-    vstart = zeros();
-    RETIRE_SUCCESS
-  }
-
-# SPDX-SnippetEnd

data/.data/spec/std/isa/inst/V/vmsleu.vv.yaml

@@ -31,47 +31,3 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-
-# SPDX-SnippetBegin
-# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
-# SPDX-License-Identifier: BSD-2-Clause
-sail(): |
-  {
-    let SEW      = get_sew();
-    let LMUL_pow = get_lmul_pow();
-    let num_elem = get_num_elem(LMUL_pow, SEW);
-
-    if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };
-
-    let 'n = num_elem;
-    let 'm = SEW;
-
-    let vm_val  : vector('n, dec, bool)     = read_vmask(num_elem, vm, 0b00000);
-    let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);
-    let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
-    let vd_val  : vector('n, dec, bool)     = read_vmask(num_elem, 0b0, vd);
-    result      : vector('n, dec, bool)     = undefined;
-    mask        : vector('n, dec, bool)     = undefined;
-
-    (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
-
-    foreach (i from 0 to (num_elem - 1)) {
-      if mask[i] then {
-        let res : bool = match funct6 {
-          VVCMP_VMSEQ    => vs2_val[i] == vs1_val[i],
-          VVCMP_VMSNE    => vs2_val[i] != vs1_val[i],
-          VVCMP_VMSLTU   => unsigned(vs2_val[i]) < unsigned(vs1_val[i]),
-          VVCMP_VMSLT    => signed(vs2_val[i]) < signed(vs1_val[i]),
-          VVCMP_VMSLEU   => unsigned(vs2_val[i]) <= unsigned(vs1_val[i]),
-          VVCMP_VMSLE    => signed(vs2_val[i]) <= signed(vs1_val[i])
-        };
-        result[i] = res
-      }
-    };
-
-    write_vmask(num_elem, vd, result);
-    vstart = zeros();
-    RETIRE_SUCCESS
-  }
-
-# SPDX-SnippetEnd

data/.data/spec/std/isa/inst/V/vmsleu.vx.yaml

@@ -31,49 +31,3 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-
-# SPDX-SnippetBegin
-# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
-# SPDX-License-Identifier: BSD-2-Clause
-sail(): |
-  {
-    let SEW      = get_sew();
-    let LMUL_pow = get_lmul_pow();
-    let num_elem = get_num_elem(LMUL_pow, SEW);
-
-    if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };
-
-    let 'n = num_elem;
-    let 'm = SEW;
-
-    let vm_val  : vector('n, dec, bool)     = read_vmask(num_elem, vm, 0b00000);
-    let rs1_val : bits('m)                  = get_scalar(rs1, SEW);
-    let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
-    let vd_val  : vector('n, dec, bool)     = read_vmask(num_elem, 0b0, vd);
-    result      : vector('n, dec, bool)     = undefined;
-    mask        : vector('n, dec, bool)     = undefined;
-
-    (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
-
-    foreach (i from 0 to (num_elem - 1)) {
-      if mask[i] then {
-        let res : bool = match funct6 {
-          VXCMP_VMSEQ    => vs2_val[i] == rs1_val,
-          VXCMP_VMSNE    => vs2_val[i] != rs1_val,
-          VXCMP_VMSLTU   => unsigned(vs2_val[i]) < unsigned(rs1_val),
-          VXCMP_VMSLT    => signed(vs2_val[i]) < signed(rs1_val),
-          VXCMP_VMSLEU   => unsigned(vs2_val[i]) <= unsigned(rs1_val),
-          VXCMP_VMSLE    => signed(vs2_val[i]) <= signed(rs1_val),
-          VXCMP_VMSGTU   => unsigned(vs2_val[i]) > unsigned(rs1_val),
-          VXCMP_VMSGT    => signed(vs2_val[i]) > signed(rs1_val)
-        };
-        result[i] = res
-      }
-    };
-
-    write_vmask(num_elem, vd, result);
-    vstart = zeros();
-    RETIRE_SUCCESS
-  }
-
-# SPDX-SnippetEnd

data/.data/spec/std/isa/inst/V/vmslt.vv.yaml

@@ -31,47 +31,3 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-
-# SPDX-SnippetBegin
-# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
-# SPDX-License-Identifier: BSD-2-Clause
-sail(): |
-  {
-    let SEW      = get_sew();
-    let LMUL_pow = get_lmul_pow();
-    let num_elem = get_num_elem(LMUL_pow, SEW);
-
-    if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };
-
-    let 'n = num_elem;
-    let 'm = SEW;
-
-    let vm_val  : vector('n, dec, bool)     = read_vmask(num_elem, vm, 0b00000);
-    let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);
-    let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
-    let vd_val  : vector('n, dec, bool)     = read_vmask(num_elem, 0b0, vd);
-    result      : vector('n, dec, bool)     = undefined;
-    mask        : vector('n, dec, bool)     = undefined;
-
-    (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
-
-    foreach (i from 0 to (num_elem - 1)) {
-      if mask[i] then {
-        let res : bool = match funct6 {
-          VVCMP_VMSEQ    => vs2_val[i] == vs1_val[i],
-          VVCMP_VMSNE    => vs2_val[i] != vs1_val[i],
-          VVCMP_VMSLTU   => unsigned(vs2_val[i]) < unsigned(vs1_val[i]),
-          VVCMP_VMSLT    => signed(vs2_val[i]) < signed(vs1_val[i]),
-          VVCMP_VMSLEU   => unsigned(vs2_val[i]) <= unsigned(vs1_val[i]),
-          VVCMP_VMSLE    => signed(vs2_val[i]) <= signed(vs1_val[i])
-        };
-        result[i] = res
-      }
-    };
-
-    write_vmask(num_elem, vd, result);
-    vstart = zeros();
-    RETIRE_SUCCESS
-  }
-
-# SPDX-SnippetEnd

data/.data/spec/std/isa/inst/V/vmslt.vx.yaml

@@ -31,49 +31,3 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-
-# SPDX-SnippetBegin
-# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
-# SPDX-License-Identifier: BSD-2-Clause
-sail(): |
-  {
-    let SEW      = get_sew();
-    let LMUL_pow = get_lmul_pow();
-    let num_elem = get_num_elem(LMUL_pow, SEW);
-
-    if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };
-
-    let 'n = num_elem;
-    let 'm = SEW;
-
-    let vm_val  : vector('n, dec, bool)     = read_vmask(num_elem, vm, 0b00000);
-    let rs1_val : bits('m)                  = get_scalar(rs1, SEW);
-    let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
-    let vd_val  : vector('n, dec, bool)     = read_vmask(num_elem, 0b0, vd);
-    result      : vector('n, dec, bool)     = undefined;
-    mask        : vector('n, dec, bool)     = undefined;
-
-    (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
-
-    foreach (i from 0 to (num_elem - 1)) {
-      if mask[i] then {
-        let res : bool = match funct6 {
-          VXCMP_VMSEQ    => vs2_val[i] == rs1_val,
-          VXCMP_VMSNE    => vs2_val[i] != rs1_val,
-          VXCMP_VMSLTU   => unsigned(vs2_val[i]) < unsigned(rs1_val),
-          VXCMP_VMSLT    => signed(vs2_val[i]) < signed(rs1_val),
-          VXCMP_VMSLEU   => unsigned(vs2_val[i]) <= unsigned(rs1_val),
-          VXCMP_VMSLE    => signed(vs2_val[i]) <= signed(rs1_val),
-          VXCMP_VMSGTU   => unsigned(vs2_val[i]) > unsigned(rs1_val),
-          VXCMP_VMSGT    => signed(vs2_val[i]) > signed(rs1_val)
-        };
-        result[i] = res
-      }
-    };
-
-    write_vmask(num_elem, vd, result);
-    vstart = zeros();
-    RETIRE_SUCCESS
-  }
-
-# SPDX-SnippetEnd

data/.data/spec/std/isa/inst/V/vmsltu.vv.yaml

@@ -31,47 +31,3 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-
-# SPDX-SnippetBegin
-# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
-# SPDX-License-Identifier: BSD-2-Clause
-sail(): |
-  {
-    let SEW      = get_sew();
-    let LMUL_pow = get_lmul_pow();
-    let num_elem = get_num_elem(LMUL_pow, SEW);
-
-    if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };
-
-    let 'n = num_elem;
-    let 'm = SEW;
-
-    let vm_val  : vector('n, dec, bool)     = read_vmask(num_elem, vm, 0b00000);
-    let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);
-    let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
-    let vd_val  : vector('n, dec, bool)     = read_vmask(num_elem, 0b0, vd);
-    result      : vector('n, dec, bool)     = undefined;
-    mask        : vector('n, dec, bool)     = undefined;
-
-    (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
-
-    foreach (i from 0 to (num_elem - 1)) {
-      if mask[i] then {
-        let res : bool = match funct6 {
-          VVCMP_VMSEQ    => vs2_val[i] == vs1_val[i],
-          VVCMP_VMSNE    => vs2_val[i] != vs1_val[i],
-          VVCMP_VMSLTU   => unsigned(vs2_val[i]) < unsigned(vs1_val[i]),
-          VVCMP_VMSLT    => signed(vs2_val[i]) < signed(vs1_val[i]),
-          VVCMP_VMSLEU   => unsigned(vs2_val[i]) <= unsigned(vs1_val[i]),
-          VVCMP_VMSLE    => signed(vs2_val[i]) <= signed(vs1_val[i])
-        };
-        result[i] = res
-      }
-    };
-
-    write_vmask(num_elem, vd, result);
-    vstart = zeros();
-    RETIRE_SUCCESS
-  }
-
-# SPDX-SnippetEnd

data/.data/spec/std/isa/inst/V/vmsltu.vx.yaml

@@ -31,49 +31,3 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-
-# SPDX-SnippetBegin
-# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
-# SPDX-License-Identifier: BSD-2-Clause
-sail(): |
-  {
-    let SEW      = get_sew();
-    let LMUL_pow = get_lmul_pow();
-    let num_elem = get_num_elem(LMUL_pow, SEW);
-
-    if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };
-
-    let 'n = num_elem;
-    let 'm = SEW;
-
-    let vm_val  : vector('n, dec, bool)     = read_vmask(num_elem, vm, 0b00000);
-    let rs1_val : bits('m)                  = get_scalar(rs1, SEW);
-    let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
-    let vd_val  : vector('n, dec, bool)     = read_vmask(num_elem, 0b0, vd);
-    result      : vector('n, dec, bool)     = undefined;
-    mask        : vector('n, dec, bool)     = undefined;
-
-    (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
-
-    foreach (i from 0 to (num_elem - 1)) {
-      if mask[i] then {
-        let res : bool = match funct6 {
-          VXCMP_VMSEQ    => vs2_val[i] == rs1_val,
-          VXCMP_VMSNE    => vs2_val[i] != rs1_val,
-          VXCMP_VMSLTU   => unsigned(vs2_val[i]) < unsigned(rs1_val),
-          VXCMP_VMSLT    => signed(vs2_val[i]) < signed(rs1_val),
-          VXCMP_VMSLEU   => unsigned(vs2_val[i]) <= unsigned(rs1_val),
-          VXCMP_VMSLE    => signed(vs2_val[i]) <= signed(rs1_val),
-          VXCMP_VMSGTU   => unsigned(vs2_val[i]) > unsigned(rs1_val),
-          VXCMP_VMSGT    => signed(vs2_val[i]) > signed(rs1_val)
-        };
-        result[i] = res
-      }
-    };
-
-    write_vmask(num_elem, vd, result);
-    vstart = zeros();
-    RETIRE_SUCCESS
-  }
-
-# SPDX-SnippetEnd

data/.data/spec/std/isa/inst/V/vmsne.vi.yaml

@@ -31,47 +31,3 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-
-# SPDX-SnippetBegin
-# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
-# SPDX-License-Identifier: BSD-2-Clause
-sail(): |
-  {
-    let SEW      = get_sew();
-    let LMUL_pow = get_lmul_pow();
-    let num_elem = get_num_elem(LMUL_pow, SEW);
-
-    if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };
-
-    let 'n = num_elem;
-    let 'm = SEW;
-
-    let vm_val  : vector('n, dec, bool)     = read_vmask(num_elem, vm, 0b00000);
-    let imm_val : bits('m)                  = sign_extend(simm);
-    let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
-    let vd_val  : vector('n, dec, bool)     = read_vmask(num_elem, 0b0, vd);
-    result      : vector('n, dec, bool)     = undefined;
-    mask        : vector('n, dec, bool)     = undefined;
-
-    (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
-
-    foreach (i from 0 to (num_elem - 1)) {
-      if mask[i] then {
-        let res : bool = match funct6 {
-          VICMP_VMSEQ    => vs2_val[i] == imm_val,
-          VICMP_VMSNE    => vs2_val[i] != imm_val,
-          VICMP_VMSLEU   => unsigned(vs2_val[i]) <= unsigned(imm_val),
-          VICMP_VMSLE    => signed(vs2_val[i]) <= signed(imm_val),
-          VICMP_VMSGTU   => unsigned(vs2_val[i]) > unsigned(imm_val),
-          VICMP_VMSGT    => signed(vs2_val[i]) > signed(imm_val)
-        };
-        result[i] = res
-      }
-    };
-
-    write_vmask(num_elem, vd, result);
-    vstart = zeros();
-    RETIRE_SUCCESS
-  }
-
-# SPDX-SnippetEnd

data/.data/spec/std/isa/inst/V/vmsne.vv.yaml

@@ -31,47 +31,3 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-
-# SPDX-SnippetBegin
-# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
-# SPDX-License-Identifier: BSD-2-Clause
-sail(): |
-  {
-    let SEW      = get_sew();
-    let LMUL_pow = get_lmul_pow();
-    let num_elem = get_num_elem(LMUL_pow, SEW);
-
-    if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };
-
-    let 'n = num_elem;
-    let 'm = SEW;
-
-    let vm_val  : vector('n, dec, bool)     = read_vmask(num_elem, vm, 0b00000);
-    let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);
-    let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
-    let vd_val  : vector('n, dec, bool)     = read_vmask(num_elem, 0b0, vd);
-    result      : vector('n, dec, bool)     = undefined;
-    mask        : vector('n, dec, bool)     = undefined;
-
-    (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
-
-    foreach (i from 0 to (num_elem - 1)) {
-      if mask[i] then {
-        let res : bool = match funct6 {
-          VVCMP_VMSEQ    => vs2_val[i] == vs1_val[i],
-          VVCMP_VMSNE    => vs2_val[i] != vs1_val[i],
-          VVCMP_VMSLTU   => unsigned(vs2_val[i]) < unsigned(vs1_val[i]),
-          VVCMP_VMSLT    => signed(vs2_val[i]) < signed(vs1_val[i]),
-          VVCMP_VMSLEU   => unsigned(vs2_val[i]) <= unsigned(vs1_val[i]),
-          VVCMP_VMSLE    => signed(vs2_val[i]) <= signed(vs1_val[i])
-        };
-        result[i] = res
-      }
-    };
-
-    write_vmask(num_elem, vd, result);
-    vstart = zeros();
-    RETIRE_SUCCESS
-  }
-
-# SPDX-SnippetEnd

data/.data/spec/std/isa/inst/V/vmsne.vx.yaml

@@ -31,49 +31,3 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-
-# SPDX-SnippetBegin
-# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
-# SPDX-License-Identifier: BSD-2-Clause
-sail(): |
-  {
-    let SEW      = get_sew();
-    let LMUL_pow = get_lmul_pow();
-    let num_elem = get_num_elem(LMUL_pow, SEW);
-
-    if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL };
-
-    let 'n = num_elem;
-    let 'm = SEW;
-
-    let vm_val  : vector('n, dec, bool)     = read_vmask(num_elem, vm, 0b00000);
-    let rs1_val : bits('m)                  = get_scalar(rs1, SEW);
-    let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
-    let vd_val  : vector('n, dec, bool)     = read_vmask(num_elem, 0b0, vd);
-    result      : vector('n, dec, bool)     = undefined;
-    mask        : vector('n, dec, bool)     = undefined;
-
-    (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val);
-
-    foreach (i from 0 to (num_elem - 1)) {
-      if mask[i] then {
-        let res : bool = match funct6 {
-          VXCMP_VMSEQ    => vs2_val[i] == rs1_val,
-          VXCMP_VMSNE    => vs2_val[i] != rs1_val,
-          VXCMP_VMSLTU   => unsigned(vs2_val[i]) < unsigned(rs1_val),
-          VXCMP_VMSLT    => signed(vs2_val[i]) < signed(rs1_val),
-          VXCMP_VMSLEU   => unsigned(vs2_val[i]) <= unsigned(rs1_val),
-          VXCMP_VMSLE    => signed(vs2_val[i]) <= signed(rs1_val),
-          VXCMP_VMSGTU   => unsigned(vs2_val[i]) > unsigned(rs1_val),
-          VXCMP_VMSGT    => signed(vs2_val[i]) > signed(rs1_val)
-        };
-        result[i] = res
-      }
-    };
-
-    write_vmask(num_elem, vd, result);
-    vstart = zeros();
-    RETIRE_SUCCESS
-  }
-
-# SPDX-SnippetEnd

data/.data/spec/std/isa/inst/V/vmsof.m.yaml

@@ -29,45 +29,3 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
-
-# SPDX-SnippetBegin
-# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
-# SPDX-License-Identifier: BSD-2-Clause
-sail(): |
-  {
-    let SEW      = get_sew();
-    let LMUL_pow = get_lmul_pow();
-    let num_elem = unsigned(vlenb) * 8;
-
-    if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2
-    then { handle_illegal(); return RETIRE_FAIL };
-
-    let 'n = num_elem;
-    let 'm = SEW;
-
-    let vm_val  : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);
-    let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2);
-    let vd_val  : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd);
-    result      : vector('n, dec, bool) = undefined;
-    mask        : vector('n, dec, bool) = undefined;
-
-    (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val);
-
-    found_elem : bool = false;
-    foreach (i from 0 to (num_elem - 1)) {
-      if mask[i] then {
-        if vs2_val[i] & not(found_elem) then {
-          result[i] = true;
-          found_elem = true
-        } else {
-          result[i] = false
-        }
-      }
-    };
-
-    write_vmask(num_elem, vd, result);
-    vstart = zeros();
-    RETIRE_SUCCESS
-  }
-
-# SPDX-SnippetEnd