ucisc 0.1.0

data/lib/micro_cisc/compile/label_generator.rb

@@ -0,0 +1,48 @@
+module MicroCisc
+  module Compile
+    class LabelGenerator
+      def initialize
+        @labels = []
+        @count = 0
+      end
+
+      def push_context
+        @count += 1
+        @labels << "{#{@count}"
+      end
+
+      def pop_context
+        @labels << last_open.sub('{', '}')
+      end
+
+      def end_label
+        last_open.sub('{', '}')
+      end
+
+      def start_label
+        last_open
+      end
+
+      def last_open
+        if @labels.empty?
+          raise ArgumentException, "No open label context"
+        end
+        # Go backwards until we find an open that we didn't see the close for first
+        i = @labels.size - 1
+        closed = nil
+        while(i >= 0)
+          if @labels[i].start_with?('}')
+            closed = @labels[i]
+          elsif !closed
+            return @labels[i]
+          elsif closed && @labels[i].end_with?(closed[1..-1])
+            closed = nil
+          else
+            raise 'Invalid state, contexts are out of order'
+          end
+          i -= 1
+        end
+      end
+    end
+  end
+end

data/lib/micro_cisc/compile/statement.rb

@@ -0,0 +1,113 @@
+module MicroCisc
+  module Compile
+    class Statement
+      SUGAR_REGEX = /(?<name>(\$|&)[^\s\[\]]+)\s+(?<op>as|=)\s+(?<param>.+)/
+      FUNCTION_REGEX = /(?<stack>[^\s\[\]]+)\s*(\[(?<words>[0-9]+)\]){0,1}\s+<=\s+(?<label>[a-zA-Z_][a-zA-Z0-9_\-@$!%]*)\s*\(\s*(?<args>[^)]*)/
+      IMM_REGEX = / (0x){0,1}(?<imm_val>[0-9A-Fa-f])\.imm/
+      attr_reader :original, :minimal
+
+      def initialize(label_generator, statement, sugar)
+        @label_generator = label_generator
+        @original = statement
+        @minimal = filter_comments(statement)
+        @sugar = sugar
+      end
+
+      def filter_comments(instruction)
+        # Remove all inline comments
+        instruction = instruction.to_s.strip.gsub(/\/[^\/]*\//, '')
+        # Remove all word comments
+        instruction = instruction.gsub(/'[^\s]*/, '')
+        # Remove all line comments
+        instruction = instruction.gsub(/#.*/, '')
+        # Single space
+        instruction.gsub(/\s+/, ' ')
+      end
+
+      def create_variable(name, arg)
+        if arg.end_with?("mem") || arg.end_with?("reg")
+          name = name[1..-1]
+          arg = arg[0..-4]
+
+          @sugar["$#{name}"] = "#{arg}mem"
+          @sugar["&#{name}"] = "#{arg}reg"
+        else
+          @sugar[name] = arg
+        end
+      end
+
+      def parse
+        if FUNCTION_REGEX =~ @minimal
+          parse_function_call
+        elsif SUGAR_REGEX =~ @minimal
+          match = SUGAR_REGEX.match(@minimal)
+          name = match['name']
+          if match['op'] == 'as'
+            create_variable(name, match['param'])
+            []
+          elsif match['op'] == '='
+            @minimal = match['param']
+            instruction = Instruction.new(@label_generator, minimal, original, @sugar)
+            dest = instruction.dest
+            if [1, 2, 3].include?(dest)
+              create_variable(name, "#{dest}.mem")
+            else
+              dest -= 4 if dest > 4
+              create_variable(name, "#{dest}.reg")
+            end
+            [instruction]
+          else
+            raise ArgumentError, "Invalid syntax declaration: #{@minimal}"
+          end
+        else
+          [Instruction.new(@label_generator, @minimal, original, @sugar)]
+        end
+      end
+
+      def parse_function_call
+        match = FUNCTION_REGEX.match(@minimal)
+        label = match['label']
+
+        stack = match['stack']
+        stack = @sugar[stack] if @sugar[stack]
+        raise ArgumentError, "Invalid stack param, mem register expected: #{stack}" unless stack =~ /^[1-3]\.mem$/
+        stackp = stack.sub('mem', 'reg')
+
+        return_words = match['words'].to_i
+        args = match['args'].split(',').map(&:strip)
+
+        instructions = []
+        if return_words > 0
+          instruction = "copy #{stackp} -#{return_words}.imm #{stackp}"
+          instructions << Instruction.new(@label_generator, instruction, "  #{instruction} # return vars - #{original}", @sugar)
+        end
+
+        instruction = "copy 0.reg #{args.size + 2}.imm #{stack} push"
+        instructions << Instruction.new(@label_generator, instruction, "  #{instruction} # return addr - #{original}", @sugar)
+
+        stack_delta = 1 + return_words
+        args = args.each do |arg|
+          arg = arg.split(' ').map { |a| @sugar[a] || a }.join(' ')
+          is_stack = arg.start_with?(stack)
+          if is_stack
+            offset = stack_delta
+            if arg_imm = IMM_REGEX.match(arg)
+              arg_imm = arg_imm['imm_val'].to_i(16)
+              arg = arg.sub(IMM_REGEX, '')
+            else
+              arg_imm = 0
+            end
+            offset_immediate = (offset + arg_imm) > 0 ? " #{(offset + arg_imm)}.imm" : ''
+            arg = "#{arg}#{offset_immediate}"
+          end
+          instruction = "copy #{arg} #{stack} push"
+          stack_delta += 1
+          instructions << Instruction.new(@label_generator, instruction, "  #{instruction} # push arg - #{original}", @sugar)
+        end
+        instruction = "copy 0.reg #{label}.disp 0.reg"
+        instructions << Instruction.new(@label_generator, instruction, "  #{instruction} # call - #{original}", @sugar)
+        instructions
+      end
+    end
+  end
+end

data/lib/micro_cisc/version.rb

@@ -0,0 +1,3 @@
+module MicroCisc
+  VERSION = "0.1.0"
+end

data/lib/micro_cisc/vm/device.rb

@@ -0,0 +1,140 @@
+module MicroCisc
+  module Vm
+    # This is a generic device base class providing memory and control access
+    #
+    # From the docs, the control word layout is as follows:
+    #
+    # * 0x0 - Device ID, read only. Unique system wide.
+    # * 0x1 - Bank address (MSB) | Device type (LSB)
+    # * 0x2 - Bus access device ID
+    # * 0x3 - Interrupt code (MSB) | Device status (LSB)
+    # * 0x4 - Local register with interrupt handler address (read/write)
+    # * 0x5 to 0xF - Device type specific
+    class Device
+      attr_reader :id
+
+      def initialize(id, type, local_blocks, rom_blocks = [])
+        @id = id
+        @external_read = 0x001F
+        @privileged_read = 0x001F
+        @privileged_write = 0x0010
+        @internal_write = 0x000C
+
+        @local_blocks = local_blocks
+        rom_blocks.each { |block| block.freeze }
+        ram_blocks = Array.new(local_blocks - rom_blocks.size).map do
+          Array.new(256).map { 0 }
+        end
+        @local_mem = rom_blocks + ram_blocks
+
+        @control = 0
+        @control_mem = Array.new(16).map { 0 }
+        @control_mem[0] = id
+        @control_mem[1] = type & 0xFF
+
+        @devices = [self]
+      end
+
+      def bank_index=(index)
+        @control_mem[1] = ((index & 0xFF) << 8) | (@control_mem[1] & 0xFF)
+      end
+
+      def devices=(devices)
+        @devices = [self] + devices
+        @devices.each_with_index { |device, index| device.bank_index = index }
+      end
+
+      def source_halted(source_device_id)
+        @control_mem[2] = 0 if source_device_id == @control_mem[2]
+      end
+
+      def write_control(source_device_id, address, value)
+        address = address & 0xF
+        return if address == 0
+        if source_device_id == @id
+          return if (1 << (address - 1)) & @internal_write == 0
+          @control_mem[address] = value
+        elsif source_device_id == @control_mem[2]
+          return if (1 << (address - 1)) & @privileged_write == 0
+          @control_mem[address] = value
+          handle_control_update(address, value)
+        end
+      end
+
+      def read_control(source_device_id, address)
+        return @control_mem[0] if address == 0
+        if source_device_id == @id || source_device_id == @control_mem[2]
+          return 0 if (1 << (address - 1)) & @privileged_read == 0
+          handle_control_read(address)
+          @control_mem[address]
+        else
+          return 0 if (1 << (address - 1)) & @external_read == 0
+          handle_control_read(address)
+          @control_mem[address]
+        end
+      end
+
+      def handle_control_read(address)
+        # Does nothing by default, override in subclass
+      end
+
+      def handle_control_update(address, value)
+        # Does nothing by default, override in subclass
+      end
+
+      def banked?(address)
+        banked = ((address & 0xF000) >> 12)
+        if banked == 0
+          banked = 1
+        else
+          banked = 1 << banked
+        end
+        (banked & @control) != 0
+      end
+
+      def write_mem(source_device_id, address, value)
+        banked = banked?(address)
+        device = (address >> 4)
+        if banked && source_device_id == @id && device < @devices.size
+          @devices[device].write_control(source_device_id, address & 0xF, value)
+        elsif banked && source_device_id == @id && device >= 256
+          device = (address >> 8)
+          if device < @devices.size
+            @devices[device].write_mem(source_device_id, address & 0xFF, value)
+          else
+            page = (address & 0xFF00) >> 8
+            @local_mem[page][address & 0xFF] = value
+          end
+        elsif !banked && source_device_id == @id
+          page = (address & 0xFF00) >> 8
+          @local_mem[page][address & 0xFF] = value
+        elsif source_device_id == @control_mem[2]
+          page = (@control_mem[3] & 0xFF00) >> 8
+          @local_mem[page][address & 0xFF] = value
+        end
+      end
+
+      def read_mem(source_device_id, address, force_local = false)
+        banked = banked?(address) && !force_local
+        device = (address >> 4)
+        if banked && source_device_id == @id && device < @devices.size
+          @devices[device].read_control(source_device_id, address & 0xF)
+        elsif banked && source_device_id == @id && device >= 256
+          device = (address >> 8)
+          if device < @devices.size
+            @devices[device].read_mem(source_device_id, address & 0xFF)
+          else
+            page = (address & 0xFF00) >> 8
+            @local_mem[page][address & 0xFF]
+          end
+        elsif !banked && source_device_id == @id
+          page = (address & 0xFF00) >> 8
+          @local_mem[page][address & 0xFF]
+        elsif source_device_id == @control_mem[2]
+          page = @control_mem[3] & 0xFF00
+          @local_mem[page][address * 0xFF]
+        end
+      end
+    end
+  end
+end

data/lib/micro_cisc/vm/empty_device.rb

@@ -0,0 +1,9 @@
+module MicroCisc
+  module Vm
+    class EmptyDevice < Device
+      def initialize
+        super(0, 0, 0)
+      end
+    end
+  end
+end

data/lib/micro_cisc/vm/processor.rb

@@ -0,0 +1,447 @@
+module MicroCisc
+  module Vm
+    # Many of the coding decisions made in here are for performance reasons:
+    #
+    # 1. Mostly one big class, avoiding object creation and referencing
+    # 2. More verbose programming style in some cases
+    # 3. Optimized/strange bitwise math for performance/avoiding ruby magic
+    # 4. Some strange branching structures to shortcut common paths
+    # 5. Few accessor methods, prefer instance vars
+    # 6. Little runtime error checking
+    #
+    # Performance isn't a deal breaker, but 1+ MIPS, roughly speaking, gives me a few
+    # times the MIPS of an original 6502 which puts me in the ball park of where I
+    # need to be to do some real programming. We just want something reasonable for
+    # debuging and doing some real coding, actual hardware will leave this in the
+    # dust most likely.
+    class Processor < Device
+      OP_MASK             = 0x8000
+      EFFECT_MASK         = 0x6000
+      DESTINATION_MASK    = 0x1C00
+      SOURCE_MASK         = 0x0380
+      ALU_OP_MASK         = 0x000F
+      IMMEDIATE_MASK      = 0x0030
+      INCREMENT_MASK      = 0x0040
+      IMMEDIATE_SIGN_MASK = 0x0020
+
+      OP_SHIFT            = 15
+      EFFECT_SHIFT        = 13
+      DESTINATION_SHIFT   = 10
+      SOURCE_SHIFT        = 7
+
+      NEGATIVE_MASK       = 0x0004
+      ZERO_MASK           = 0x0002
+      OVERFLOW_MASK       = 0x0001
+
+      SIGNED_MODE_FLAG    = 0x0100
+      HALT_MODE_FLAG      = 0x0200
+
+      SIGN_BIT            = 0x8000
+      PAGE_MASK           = 0xFFC0
+
+      MEM_ARGS            = [1, 2, 3]
+
+      attr_accessor :flags, :overflow, :debug
+      attr_reader :pc, :control, :count
+
+      def initialize(id, local_blocks, rom_blocks = [])
+        super(id, 1, local_blocks, rom_blocks)
+
+        @registers = [0, 0, 0, 0]
+        @pc = 0
+        @flags = 0
+        @overflow = 0
+        @debug = false
+        @run = false
+        @pc_modified = false
+        @count = 0
+      end
+
+      def handle_control_update(address, value)
+        if address == 0x7
+          self.pc = value
+        elsif address == 0x8
+          set_register(1, value)
+        elsif address == 0x9
+          set_register(2, value)
+        elsif address == 0xA
+          set_register(3, value)
+        elsif address == 0xB
+          @flags = value & 0xFFFF
+        elsif address == 0xC
+          self.control = value
+        end
+      end
+
+      def control=(value)
+        @control = value & 0xFFFF
+      end
+
+      def pc=(value)
+        @pc_modified = true
+        @pc = value & 0xFFFF
+      end
+
+      def register(id)
+        @registers[id]
+      end
+
+      def set_register(id, value)
+        @registers[id] = value
+      end
+
+      def extract_immediates(word, is_copy, inc_is_immediate, signed, half_width)
+        if is_copy
+          immediate_mask = IMMEDIATE_MASK | ALU_OP_MASK
+          immediate_shift = 0
+        else
+          immediate_mask = IMMEDIATE_MASK
+          immediate_shift = 4
+        end
+
+        sign_mask = IMMEDIATE_SIGN_MASK
+        if inc_is_immediate
+          sign_mask = INCREMENT_MASK
+          immediate_mask = immediate_mask | INCREMENT_MASK
+        end
+
+        if signed && ((word & sign_mask) != 0)
+          # Fancy bit inverse for high performance sign extend
+          [~(~(word & immediate_mask) & immediate_mask) >> immediate_shift]
+        elsif half_width
+          [
+            (word & immediate_mask) >> (immediate_shift + 3),
+            (word & (immediate_mask >> 3)) >> immediate_shift
+          ]
+        else
+          [(word & immediate_mask) >> immediate_shift]
+        end
+      end
+
+      # * 0 = zero?
+      # * 1 = not zero?
+      # * 2 = negative?
+      # * 3 = store
+      def store?(flags, effect)
+        return true if effect == 3 # handle the common case quickly
+
+        zero = flags & ZERO_MASK != 0
+        (effect == 0 && zero) ||
+          (effect == 1 && !zero) ||
+          (effect == 2 && (flags & NEGATIVE_MASK != 0))
+      end
+
+      def source_value(source, immediate)
+        case source
+        when 0
+          @pc + immediate
+        when 1,2,3
+          read_mem(@id, @registers[source] + immediate)
+        when 4
+          immediate
+        else
+          @registers[source - 4] + immediate
+        end
+      end
+
+      def destination_value(destination, immediate)
+        case destination
+        when 0
+          @pc
+        when 1,2,3
+          read_mem(@id, @registers[destination] + immediate)
+        when 4
+          @control
+        else
+          @registers[destination - 4]
+        end
+      end
+
+      def exec_instruction(word)
+        source = (word & SOURCE_MASK) >> SOURCE_SHIFT
+        destination = (word & DESTINATION_MASK) >> DESTINATION_SHIFT
+        effect = (word & EFFECT_MASK) >> EFFECT_SHIFT
+
+        signed = !MEM_ARGS.include?(source)
+        inc_is_immediate = signed && !MEM_ARGS.include?(destination)
+        is_copy = (word & OP_MASK) == 0
+        half_width = is_copy && MEM_ARGS.include?(source) && MEM_ARGS.include?(destination)
+        immediates = extract_immediates(word, is_copy, inc_is_immediate, signed, half_width)
+
+        alu = word & ALU_OP_MASK
+        result = compute_result(is_copy, source, destination, immediates, alu, true)
+
+        return false unless store?(@flags, effect)
+
+        push = !inc_is_immediate && (word & INCREMENT_MASK) > 0
+        store_result(result, source, destination, immediates, push, 0)
+
+        # Detect halt instruction
+        return 1 if immediates.first == 0 && source == 0 && destination == 0
+        0
+      end
+
+      def compute_result(is_copy, source, destination, immediates, alu, update_flags)
+        source_value = source_value(source, immediates.first)
+        if is_copy
+          source_value
+        else
+          dest_immediate = immediates.size > 1 ? immediates.last : 0
+          destination_value = destination_value(destination, dest_immediate)
+          compute(alu, source_value, destination_value, update_flags)
+        end
+      end
+
+      def store_result(value, source, destination, immediates, push, sign)
+        case destination
+        when 0
+          @pc = value
+          @pc_modified = true
+        when 1,2,3
+          if push
+            @registers[destination] = (@registers[destination] - 1) & 0xFFFF
+          end
+          imm = immediates.size > 1 ? immediates.last : 0
+          address = @registers[destination] + imm
+          write_mem(@id, address, value)
+        when 4
+          self.control = value
+        else
+          @registers[destination - 4] = value
+        end
+        if push && !MEM_ARGS.include?(destination) && MEM_ARGS.include?(source)
+          @registers[source] = (@registers[source] + 1) & 0xFFFF
+        end
+      end
+
+      def compute(alu_code, arg1, arg2, update_flags)
+        overflow = 0
+        overflow_reg = 0
+
+        case alu_code
+        when 0x00
+          # INV
+          value = (arg1 & 0xFFFF) ^ 0xFFFF
+        when 0x01
+          # AND
+          value = arg2 & arg1
+        when 0x02
+          # OR
+          value = arg2 | arg1
+        when 0x03
+          # XOR
+          value = arg2 ^ arg1
+        when 0x04
+          # Negate (2's compliment)
+          value = -1 * arg1
+        when 0x05
+          # Shift left, zero extend
+          value = arg2 << arg1
+          overflow_reg = (value & 0xFFFF0000) >> 16
+          value = value & 0xFFFF
+        when 0x06
+          # Shift right, repsect signed mode
+          overflow_mask = ~(-1 << arg1) & 0xFFFF
+          overflow_reg = arg2 & overflow_mask
+          overflow_reg >> (arg1 - 16) if arg1 > 16
+
+          if @control & SIGNED_MODE_FLAG == 0
+            value = (arg2 & 0xFFFF) >> arg1
+          else
+            value = arg2 >> arg1
+          end
+        when 0x07
+          # Swap MSB and LSB bytes
+          value = ((arg1 & 0xFF00) >> 8) | ((arg1 & 0x00FF) << 8)
+        when 0x08
+          # Zero LSB
+          value = arg1 & 0xFF00
+        when 0x09
+          # Zero MSB
+          value = arg1 & 0x00FF
+        when 0x0A,0x0B
+          arg1 = (arg1 ^ 0xFFFF) + 1 if alu_code == 0x0B
+          value = (arg1 & 0xFFFF) + (arg2 & 0xFFFF)
+          # Add, respect signed mode
+          if @control & SIGNED_MODE_FLAG == 0
+            if value > 0xFFFF
+              overflow = 1
+              overflow_reg = 1
+            end
+          else
+            if ((arg1 & SIGN_BIT) == (arg2 & SIGN_BIT)) &&
+                ((arg1 & SIGN_BIT) != (value & SIGN_BIT))
+              overflow = 1
+              overflow_reg = (value & 0xFFFF0000 >> 16) & 0xFFFF
+            end
+          end
+          value = value & 0xFFFF
+        when 0x0C
+          if @control & SIGNED_MODE_FLAG == 0
+            arg1 = ~(~arg1 & 0xFFFF) if arg1 & SIGN_BIT != 0
+            arg2 = ~(~arg2 & 0xFFFF) if arg2 & SIGN_BIT != 0
+          end
+          value = arg1 * arg2
+          overflow_reg = (value & 0xFFFF0000 >> 16) & 0xFFFF
+          if ((overflow_reg & SIGN_BIT) == (value & SIGN_BIT)) &&
+              overflow_reg == 0xFFFF
+            # There was no actual overflow, it's just the sign extension
+            overflow = 0 
+          else
+            overflow = 1
+          end
+          value = value & 0xFFFF
+        when 0x0D
+          if @control & SIGNED_MODE_FLAG == 0
+            arg1 = ~(~arg1 & 0xFFFF) if arg1 & SIGN_BIT != 0
+            arg2 = ~(~arg2 & 0xFFFF) if arg2 & SIGN_BIT != 0
+          end
+          value = arg2 / arg1
+          overflow_reg = arg2 % arg1
+          value = value & 0xFFFF
+        when 0x0E
+          value = arg1 & PAGE_MASK
+        when 0x0F
+          value = arg1 + @overflow
+        else
+          raise ArgumentError, "Unsupported ALU code #{alu_code.to_s(16).upcase}"
+        end
+
+        zero = value == 0 ? 1 : 0
+        negative = (value & 0x8000) == 0 ? 0 : 1
+
+        if update_flags
+          flags =
+            (overflow * OVERFLOW_MASK) |
+            (zero * ZERO_MASK) |
+            (negative * NEGATIVE_MASK)
+          @flags = flags
+          @overflow = overflow_reg
+        end
+        value & 0xFFFF
+      end
+
+      def start(debug = false)
+        @debug = debug
+        @run = true
+        run
+      end
+
+      def run
+        @t0 = Time.now
+        @count = 0
+        while(@run) do
+          word = read_mem(@id, @pc, true)
+          if @debug
+            # Pause before executing next command
+            do_command("#{'%04x' % [@pc]} #{ucisc(word)} ")
+          end
+          special = exec_instruction(word)
+          if special != 0
+            halt if special == 1
+            @debug = true if special == 2
+          end
+          if @pc_modified
+            @pc_modified = false
+          else
+            @pc += 1
+          end
+          @count += 1
+          # if count & 0xFF == 0
+          #   read_from_processor
+          # end
+        end
+      end
+
+      def do_command(prefix = '')
+        return unless @debug
+        $stdout.print "#{prefix}> "
+        command = $stdin.readline
+        exit(1) if /exit/.match(command)
+        @debug = true if /debug|n|next/.match(command)
+        @debug = false if /c|continue/.match(command)
+        MicroCisc.logger.info(stack_string) if /stack/.match(command)
+        byebug if /break/.match(command)
+      end
+
+      def format_data(data)
+        data.map { |w| '%04X' % w }.join(' ').gsub(/(([0-9A-Za-z]{4} ){16})/, "\\1\n")
+      end
+
+      def halt
+        delta = (Time.now - @t0)
+        MicroCisc.logger.info("HALT: #{@count} instructions in #{delta}s")
+        MicroCisc.logger.info("Stack: " + stack_string)
+
+        @run = false
+      end
+
+      def stack_string
+        address = @registers[1] & 0xFFFF
+        str = "#{'%04X' % address} => "
+        while(address > 0xFF00 && address < 0x10000 && address - @registers[1] < 10)
+          str += "0x#{'%04X' % read_mem(@id, address)} "
+          address += 1
+        end
+        str
+      end
+
+      def ucisc(word)
+        source = (word & SOURCE_MASK) >> SOURCE_SHIFT
+        destination = (word & DESTINATION_MASK) >> DESTINATION_SHIFT
+        effect = (word & EFFECT_MASK) >> EFFECT_SHIFT
+
+        src =
+          if source == 0
+            '0.reg'
+          elsif source < 4
+            "#{source}.mem"
+          elsif source == 4
+            '4.val'
+          else
+            "#{source - 4}.reg"
+          end
+
+        dest =
+          if destination == 0
+            '0.reg'
+          elsif destination < 4
+            "#{destination}.mem"
+          elsif destination == 4
+            '4.reg'
+          else
+            "#{destination - 4}.reg"
+          end
+
+        # Eh?
+        signed = !MEM_ARGS.include?(source)
+        inc_is_immediate = signed && !MEM_ARGS.include?(destination)
+        is_copy = (word & OP_MASK) == 0
+        half_width = is_copy && MEM_ARGS.include?(source) && MEM_ARGS.include?(destination)
+        immediates = extract_immediates(word, is_copy, inc_is_immediate, signed, half_width)
+
+        value = source_value(source, immediates.first)
+        store = store?(@flags, effect)
+
+        alu = word & ALU_OP_MASK
+        result = compute_result(is_copy, source, destination, immediates, alu, true)
+        alu = is_copy ? '' : "0x#{alu.to_s(16).upcase}.op "
+
+        imm0 = immediates.first < 0 ? "-#{(immediates.first * -1)}.imm" : "#{immediates.first}.imm"
+        imm1 =
+          if half_width
+            immediates.last < 0 ? "-#{(immediates.last * -1)}.imm " : "#{immediates.last}.imm "
+          else
+            ""
+          end
+        eff = "#{effect}.eff"
+        push = !inc_is_immediate && (word & INCREMENT_MASK) > 0
+        push = push ? 'push ' : ''
+        ins = is_copy ? 'copy' : 'compute'
+
+
+        "Stack: #{stack_string}\n#{ins} #{alu}#{src} #{imm0} #{dest} #{imm1}#{eff} #{push}# value: #{value} (0x#{'%04x' % value}), result: #{result} (0x#{'%04x' % result}), #{'not ' if !store}stored"
+      end
+    end
+  end
+end