tamashii-mfrc522 1.0.7

checksums.yaml

@@ -0,0 +1,7 @@
+---
+SHA1:
+  metadata.gz: 440eac7bf93b99e1fdcca04eadc90bb01f325b49
+  data.tar.gz: 25602072e19601347e17e7b58e30f7919ae35628
+SHA512:
+  metadata.gz: 3e476988e2fcd4bfa7c501ffa37132711b52c0af1a15cb39ca45257e181934e718dcccfe6ac892be8ed01ec8cfeee6495afab514c4181be6775da4c3f2cd3cb2
+  data.tar.gz: 88575cc6eb0330cba4bdfa7776e8bdde6da11693a03c9963c9bd838c900ca57924a5595169c08feaaf845cbecea48d4faa2514666f2ad6527f95dfacd09ca467

data/lib/core_ext.rb

@@ -0,0 +1,35 @@
+class Array
+  def append_uint(number, byte)
+    raise 'Only support unsigned integer' if number < 0
+    raise 'Insufficient bytes' if number.abs >= (1 << (byte * 8))
+
+    until byte == 0
+      self << (number & 0xFF)
+      number >>= 8
+      byte -= 1
+    end
+    self
+  end
+
+  def to_uint
+    int = 0
+    self.each_with_index do |byte, index|
+      int |= (byte << (index * 8))
+    end
+    int
+  end
+
+  def append_sint(number, byte)
+    raise 'Insufficient bytes' if number.abs >= (1 << (byte * 8))
+
+    sign = (number < 0) ? 1 : 0
+    number &= (1 << ((byte * 8) - 1)) - 1
+    self.append_uint(number, byte)
+    self << (self.pop | (sign << 7))
+  end
+
+  def to_sint
+    sign = (self.last & 0x80 != 0) ? (-1 ^ ((1 << ((self.size * 8) - 1)) - 1)) : 0
+    sign | self.to_uint
+  end
+end

data/lib/exceptions.rb

@@ -0,0 +1,14 @@
+class CommunicationError < StandardError; end
+class PICCTimeoutError < CommunicationError; end
+class PCDTimeoutError < CommunicationError; end
+class IncorrectCRCError < CommunicationError; end
+class CollisionError < CommunicationError; end
+
+class UnexpectedDataError < StandardError; end
+
+class MifareNakError < StandardError; end
+
+class DESFireError < StandardError; end
+class UnauthenticatedError < DESFireError; end
+class ReceiptStatusError < DESFireError; end
+class ReceiptIntegrityError < DESFireError; end

data/lib/iso144434.rb

@@ -0,0 +1,247 @@
+class ISO144434 < PICC
+  FSCI_to_FSC = [16, 24, 32, 40, 48, 64, 96, 128, 256]
+
+  CMD_RATS              = 0xE0
+  CMD_PPS               = 0xD0
+  CMD_DESELECT          = 0xC2
+  CMD_SUCCESS           = 0x00
+  CMD_ADDITIONAL_FRAME  = 0xAF
+
+  def initialize(pcd, uid, sak)
+    super
+
+    @cid = 0x00 # We don't support CID
+    @fsc = 16 # Assume PICC only supports 16 bytes frame
+    @fwt = 256 # 77.33ms(256 ticks) default frame waiting time
+
+    @support_cid = false
+    @support_nad = false
+    @block_number = 0
+    @selected = false
+  end
+
+  # ISO/IEC 14443-4 select
+  def select
+    # Send RATS (Request for Answer To Select)
+    buffer = [CMD_RATS, 0x50 | @cid]
+    received_data = @pcd.picc_transceive(buffer)
+
+    dr, ds = process_ats(received_data)
+
+    # Send PPS (Protocol and Parameter Selection Request)
+    buffer = [CMD_PPS | @cid, 0x11, (ds << 2) | dr]
+    received_data = @pcd.picc_transceive(buffer)
+    raise UnexpectedDataError, 'Incorrect response' if received_data[0] != (0xD0 | @cid)
+
+    # Set PCD baud rate
+    @pcd.transceiver_baud_rate(:tx, dr)
+    @pcd.transceiver_baud_rate(:rx, ds)
+
+    @block_number = 0
+    @max_frame_size = [64, @fsc].min
+    @max_inf_size = @max_frame_size - 3 # PCB + CRC16
+    @max_inf_size -= 1 if @support_cid
+    @max_inf_size -= 1 if @support_nad
+    @selected = true
+  end
+
+  # Send S(DESELECT)
+  def deselect
+    buffer = [CMD_DESELECT]
+    received_data = @pcd.picc_transceive(buffer)
+
+    if received_data[0] & 0xF7 == CMD_DESELECT
+      @selected = false
+      true
+    else
+      false
+    end
+  end
+
+  # Wrapper for handling ISO protocol
+  def transceive(send_data)
+    # Split data according to max buffer size
+    send_data = [send_data] unless send_data.is_a? Array
+    chained_data = send_data.each_slice(@max_inf_size).to_a
+
+    # Initialize I-block
+    pcb = 0x02
+
+    # Send chained data
+    until chained_data.empty?
+      pcb &= 0xEF # Reset chaining indicator
+      pcb |= 0x10 if chained_data.size > 1 # Set chaining
+      pcb |= @block_number # Set block number
+      data = chained_data.shift
+
+      buffer = [pcb] + data
+
+      finished = false
+      until finished
+        received_data = handle_wtx(buffer)
+
+        # Retreive response pcb from data
+        r_pcb = received_data[0]
+
+        # Received ACK
+        if r_pcb & 0xF6 == 0xA2
+          # If ACK matches current block number means success
+          # Otherwise transmit it again
+          if (pcb & 0x01) == (r_pcb & 0x01)
+            finished = true
+          end
+        else
+          finished = true
+        end
+      end
+
+      @block_number ^= 1 # toggle block number for next frame
+    end
+
+    received_chained_data = [received_data]
+
+    # Receive chained data
+    while r_pcb & 0x10 != 0
+      ack = 0xA2 | @block_number # Set block number
+      received_data = handle_wtx([ack]) # Send ACK to receive next frame
+
+      r_pcb = received_data[0]
+
+      received_chained_data << received_data
+
+      @block_number ^= 1 # toggle block number for next frame
+    end
+
+    # Collect INF from chain
+    inf = []
+    received_chained_data.each do |data|
+      inf_position = 1
+      inf_position += 1 if data[0] & 0x08 != 0 # CID present
+      inf_position += 1 if data[0] & 0x04 != 0 # NAD present
+
+      inf.concat(data[inf_position..-1])
+    end
+
+    inf
+  end
+
+  def resume_communication
+    deselect rescue nil
+    super
+  end
+
+  def halt
+    deselect rescue nil
+    super
+  end
+
+  private
+
+  def convert_iso_baud_rate_to_pcd_setting(value)
+    # ISO
+    # 0b000: 106kBd, 0b001: 212kBd, 0b010: 424kBd, 0b100: 848kBd
+    # MFRC522 register
+    # 0b000: 106kBd, 0b001: 212kBd, 0b010: 424kBd, 0b011: 848kBd
+    x = (value >> 2) & 0x01
+    y = (value >> 1) & 0x01
+    z = value & 0x01
+
+    ((x | y) << 1) + (x | (~y & z))
+  end
+
+  # Gether information from ATS (Answer to Select)
+  def process_ats(ats)
+    position = 1
+    t0 = ats[position] # Format byte
+
+    fsci = t0 & 0x0F # PICC buffer size integer
+    y1 = (t0 >> 4) & 0x07 # Optional frame(TA, TB, TC) indicator
+    @fsc = FSCI_to_FSC.fetch(fsci) # Convert buffer size integer to bytes
+    dr = 0 # default baud rate 106kBd
+    ds = 0
+
+    # Frame: TA
+    if y1 & 0x01 != 0
+      position += 1
+      ta = ats[position]
+
+      dr = ta & 0x07 # PCD to PICC baud rate
+      ds = (ta >> 4) & 0x07 # PICC to PCD baud rate
+
+      # Convert fastest baud rate to PCD setting
+      # dr = convert_iso_baud_rate_to_pcd_setting(dr)
+      # ds = convert_iso_baud_rate_to_pcd_setting(ds)
+
+      # FIXME: baud rate fixed to 106kBd
+      # until author can confirm negotiation works
+      dr = 0
+      ds = 0
+    end
+
+    # Frame: TB
+    if y1 & 0x02 != 0
+      position += 1
+      tb = ats[position]
+
+      fwi = (tb >> 4) & 0x0F # Frame wating integer
+      sgfi = tb & 0x0F # Start-up frame guard integer
+
+      # Convert integers to real time
+      @fwt = (1 << fwi)
+      sgft = (1 << sgfi)
+
+      # Set frame waiting time
+      @pcd.internal_timer(@fwt)
+    end
+
+    # Get info about CID or NAD
+    if y1 & 0x04 != 0
+      position += 1
+      tc = ats[position]
+
+      @support_cid = true if tc & 0x02 != 0
+      @support_nad = true if tc & 0x01 != 0
+    end
+
+    # Start-up guard time
+    sleep 0.000302 * sgft
+
+    return dr, ds
+  end
+
+  def handle_wtx(data)
+    24.times do
+      begin
+        received_data = @pcd.picc_transceive(data)
+      rescue CommunicationError => e
+        raise e unless e.is_a? PICCTimeoutError
+
+        # Try sending NAK when timeout
+        nak = 0xB2 | @block_number
+        data = [nak]
+        next
+      end
+      
+      pcb = received_data[0]
+
+      # WTX detected
+      if pcb & 0xF7 == 0xF2
+        inf_position = (pcb & 0x08 != 0) ? 2 : 1
+        wtxm = received_data[inf_position] & 0x3F
+
+        # Set temporary timer
+        @pcd.internal_timer(@fwt * wtxm)
+
+        # Set WTX response
+        data = [0xF2, wtxm]
+      else
+        # Set timer back to FWT
+        @pcd.internal_timer(@fwt)
+
+        return received_data
+      end
+    end
+
+    raise PICCTimeoutError
+  end
+end

data/lib/mfrc522.rb

@@ -0,0 +1,616 @@
+require 'pi_piper'
+
+require 'openssl'
+require 'securerandom'
+
+require 'core_ext'
+require 'exceptions'
+
+require 'picc'
+require 'iso144434'
+
+require 'mifare/key'
+require 'mifare/classic'
+require 'mifare/ultralight'
+require 'mifare/ultralight_c'
+require 'mifare/des_fire'
+
+include PiPiper
+
+class MFRC522
+
+  # PICC commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
+  PICC_REQA         = 0x26  # REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
+  PICC_WUPA         = 0x52  # Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
+  PICC_CT           = 0x88  # Cascade Tag. Not really a command, but used during anti collision.
+  PICC_SEL_CL1      = 0x93  # Anti collision/Select, Cascade Level 1
+  PICC_SEL_CL2      = 0x95  # Anti collision/Select, Cascade Level 2
+  PICC_SEL_CL3      = 0x97  # Anti collision/Select, Cascade Level 3
+  PICC_HLTA         = 0x50  # HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
+  # Mifare Acknowledge
+  PICC_MF_ACK       = 0x0A
+
+  # PCD commands
+  PCD_Idle          = 0x00  # no action, cancels current command execution
+  PCD_Mem           = 0x01  # stores 25 bytes into the internal buffer
+  PCD_GenRandomID   = 0x02  # generates a 10-byte random ID number
+  PCD_CalcCRC       = 0x03  # activates the CRC coprocessor or performs a self test
+  PCD_Transmit      = 0x04  # transmits data from the FIFO buffer
+  PCD_NoCmdChange   = 0x07  # no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
+  PCD_Receive       = 0x08  # activates the receiver circuits
+  PCD_Transceive    = 0x0C  # transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
+  PCD_MFAuthent     = 0x0E  # performs the MIFARE standard authentication as a reader
+  PCD_SoftReset     = 0x0F  # resets the MFRC522
+  
+  # PCD Command and Status Registers
+  CommandReg        = 0x01  # starts and stops command execution
+  ComIEnReg         = 0x02  # enable and disable interrupt request control bits
+  DivIEnReg         = 0x03  # enable and disable interrupt request control bits
+  ComIrqReg         = 0x04  # interrupt request bits
+  DivIrqReg         = 0x05  # interrupt request bits
+  ErrorReg          = 0x06  # error bits showing the error status of the last command executed 
+  Status1Reg        = 0x07  # communication status bits
+  Status2Reg        = 0x08  # receiver and transmitter status bits
+  FIFODataReg       = 0x09  # input and output of 64 byte FIFO buffer
+  FIFOLevelReg      = 0x0A  # number of bytes stored in the FIFO buffer
+  WaterLevelReg     = 0x0B  # level for FIFO underflow and overflow warning
+  ControlReg        = 0x0C  # miscellaneous control registers
+  BitFramingReg     = 0x0D  # adjustments for bit-oriented frames
+  CollReg           = 0x0E  # bit position of the first bit-collision detected on the RF interface
+    
+  # PCD Command Registers
+  ModeReg           = 0x11  # defines general modes for transmitting and receiving 
+  TxModeReg         = 0x12  # defines transmission data rate and framing
+  RxModeReg         = 0x13  # defines reception data rate and framing
+  TxControlReg      = 0x14  # controls the logical behavior of the antenna driver pins TX1 and TX2
+  TxASKReg          = 0x15  # controls the setting of the transmission modulation
+  TxSelReg          = 0x16  # selects the internal sources for the antenna driver
+  RxSelReg          = 0x17  # selects internal receiver settings
+  RxThresholdReg    = 0x18  # selects thresholds for the bit decoder
+  DemodReg          = 0x19  # defines demodulator settings
+  MfTxReg           = 0x1C  # controls some MIFARE communication transmit parameters
+  MfRxReg           = 0x1D  # controls some MIFARE communication receive parameters
+  SerialSpeedReg    = 0x1F  # selects the speed of the serial UART interface
+    
+  # PCD Configuration Registers
+  CRCResultRegH     = 0x21  # shows the MSB and LSB values of the CRC calculation
+  CRCResultRegL     = 0x22
+  ModWidthReg       = 0x24  # controls the ModWidth setting?
+  RFCfgReg          = 0x26  # configures the receiver gain
+  GsNReg            = 0x27  # selects the conductance of the antenna driver pins TX1 and TX2 for modulation 
+  CWGsPReg          = 0x28  # defines the conductance of the p-driver output during periods of no modulation
+  ModGsPReg         = 0x29  # defines the conductance of the p-driver output during periods of modulation
+  TModeReg          = 0x2A  # defines settings for the internal timer
+  TPrescalerReg     = 0x2B  # the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
+  TReloadRegH       = 0x2C  # defines the 16-bit timer reload value
+  TReloadRegL       = 0x2D
+  TCounterValueRegH = 0x2E  # shows the 16-bit timer value
+  TCounterValueRegL = 0x2F
+    
+  # PCD Test Registers
+  TestSel1Reg       = 0x31  # general test signal configuration
+  TestSel2Reg       = 0x32  # general test signal configuration
+  TestPinEnReg      = 0x33  # enables pin output driver on pins D1 to D7
+  TestPinValueReg   = 0x34  # defines the values for D1 to D7 when it is used as an I/O bus
+  TestBusReg        = 0x35  # shows the status of the internal test bus
+  AutoTestReg       = 0x36  # controls the digital self test
+  VersionReg        = 0x37  # shows the software version
+  AnalogTestReg     = 0x38  # controls the pins AUX1 and AUX2
+  TestDAC1Reg       = 0x39  # defines the test value for TestDAC1
+  TestDAC2Reg       = 0x3A  # defines the test value for TestDAC2
+  TestADCReg        = 0x3B  # shows the value of ADC I and Q channels
+
+  def initialize(nrstpd = 24, chip = 0, spd = 1000000, timer = 256)
+    chip_option = { 0 => PiPiper::Spi::CHIP_SELECT_0,
+                    1 => PiPiper::Spi::CHIP_SELECT_1,
+                    2 => PiPiper::Spi::CHIP_SELECT_BOTH,
+                    3 => PiPiper::Spi::CHIP_SELECT_NONE }
+    @spi_chip = chip_option[chip]
+    @spi_spd = spd
+    @timer = timer
+
+    # Power it up
+    @nrstpd = nrstpd
+    nrstpd_pin = PiPiper::Pin.new(pin: nrstpd, direction: :out)
+    nrstpd_pin.on
+    sleep 1.0 / 20.0 # Wait 50ms
+
+    soft_reset # Perform software reset
+
+    pcd_config_reset # Set default setting
+
+    antenna_on # Turn antenna on. They were disabled by the reset.
+  end
+
+  # Shutdown
+  def shutdown
+    antenna_off
+    # TODO: handle other platform?
+    if PiPiper::Platform.driver == PiPiper::Bcm2835
+      PiPiper::Platform.driver.unexport_pin(@nrstpd)
+    end
+  end
+
+  # PCD software reset
+  def soft_reset
+    write_spi(CommandReg, PCD_SoftReset)
+    sleep 1.0 / 20.0 # wait 50ms
+
+    write_spi(TModeReg, 0x87) # Start timer by setting TAuto=1, and higher part of TPrescalerReg
+    write_spi(TPrescalerReg, 0xFF) # Set lower part of TPrescalerReg, and results in 302us timer (f_timer = 13.56 MHz / (2*TPreScaler+1))
+    
+    write_spi(TxASKReg, 0x40) # Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
+    write_spi(ModeReg, 0x3D) # Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
+  end
+
+  # Reset PCD config to default
+  def pcd_config_reset
+    # Clear ValuesAfterColl bit
+    write_spi_clear_bitmask(CollReg, 0x80)
+
+    # Reset transceiver baud rate to 106 kBd
+    transceiver_baud_rate(:tx, 0)
+    transceiver_baud_rate(:rx, 0)
+
+    # Set PCD timer value for 302us default timer
+    internal_timer(@timer)
+  end
+
+  # Control transceive timeout value
+  def internal_timer(timer = nil)
+    if timer
+      write_spi(TReloadRegH, (timer >> 8) & 0xFF)
+      write_spi(TReloadRegL, (timer & 0xFF))
+    end
+    (read_spi(TReloadRegH) << 8) | read_spi(TReloadRegL)
+  end
+
+  # Control transceiver baud rate
+  # value = 0: 106kBd, 1: 212kBd, 2: 424kBd, 3: 848kBd
+  def transceiver_baud_rate(direction, value = nil)
+    reg = {tx: TxModeReg, rx: RxModeReg}
+
+    if value
+      value <<= 4
+      value |= 0x80 if value != 0
+      write_spi(reg.fetch(direction), value)
+    end
+
+    (read_spi(reg.fetch(direction)) >> 4) & 0x07
+  end
+
+  # Turn antenna on
+  def antenna_on
+    write_spi_set_bitmask(TxControlReg, 0x03)
+  end
+
+  # Turn antenna off
+  def antenna_off
+    write_spi_clear_bitmask(TxControlReg, 0x03)
+  end
+
+  # Modify and show antenna gain level
+  # level = 1: 18dB, 2: 23dB, 3: 33dB, 4: 38dB, 5: 43dB, 6: 48dB
+  def antenna_gain(level = nil)
+    unless level.nil?
+      level = 1 if level > 6 || level < 1
+      write_spi_set_bitmask(RFCfgReg, ((level + 1) << 4))
+    end
+    (read_spi(RFCfgReg) & 0x70) >> 4
+  end
+
+  # Wakes PICC from HALT or IDLE to ACTIVE state
+  # Accept PICC_REQA and PICC_WUPA command
+  def picc_request(picc_command)
+    pcd_config_reset
+
+    status, _received_data, valid_bits = communicate_with_picc(PCD_Transceive, picc_command, 0x07)
+
+    status == :status_ok && valid_bits == 0 # REQA or WUPA command return 16 bits(full byte)
+  end
+
+  # Instruct PICC in ACTIVE state go to HALT state
+  def picc_halt
+    buffer = append_crc([PICC_HLTA, 0])
+
+    status, _received_data, _valid_bits = communicate_with_picc(PCD_Transceive, buffer)
+
+    # PICC in HALT state will not respond
+    # If PICC sent reply, means it didn't acknowledge the command we sent
+    status == :status_picc_timeout
+  end
+
+  # Select PICC for further communication
+  #
+  # PICC must be in state ACTIVE
+  def picc_select
+    #  Description of buffer structure:
+    #
+    #  Byte 0: SEL   Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
+    #  Byte 1: NVB   Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits. 
+    #  Byte 2: UID-data or Cascade Tag
+    #  Byte 3: UID-data
+    #  Byte 4: UID-data
+    #  Byte 5: UID-data
+    #  Byte 6: Block Check Character - XOR of bytes 2-5
+    #  Byte 7: CRC_A
+    #  Byte 8: CRC_A
+    #  The BCC and CRC_A are only transmitted if we know all the UID bits of the current Cascade Level.
+    #
+    #  Description of bytes 2-5
+    #
+    #  UID size  Cascade level Byte2 Byte3 Byte4 Byte5
+    #  ========  ============= ===== ===== ===== =====
+    #   4 bytes        1       uid0  uid1  uid2  uid3
+    #   7 bytes        1       CT    uid0  uid1  uid2
+    #                  2       uid3  uid4  uid5  uid6
+    #  10 bytes        1       CT    uid0  uid1  uid2
+    #                  2       CT    uid3  uid4  uid5
+    #                  3       uid6  uid7  uid8  uid9
+    pcd_config_reset
+
+    cascade_levels = [PICC_SEL_CL1, PICC_SEL_CL2, PICC_SEL_CL3]
+    uid = []
+    sak = 0
+
+    cascade_levels.each do |cascade_level|
+      buffer = [cascade_level]
+      current_level_known_bits = 0
+      received_data = []
+      valid_bits = 0
+      timeout = true
+
+      # Maxmimum loop count is defined in ISO spec
+      32.times do
+        if current_level_known_bits >= 32 # Prepare to do a complete select if we knew everything
+          # Validate buffer content against non-numeric classes and incorrect size
+          buffer = buffer[0..5]
+          dirty_buffer = buffer.size != 6
+          dirty_buffer ||= buffer.any? do |byte|
+            if Gem::Version.new(RUBY_VERSION) >= Gem::Version.new('2.4.0')
+              !byte.is_a?(Numeric)
+            else
+              !byte.is_a?(Fixnum)
+            end
+          end
+
+          # Retry reading UID when buffer is dirty, but don't reset loop count to prevent infinite loop
+          if dirty_buffer
+            # Reinitialize all variables
+            buffer = [cascade_level]
+            current_level_known_bits = 0
+            received_data = []
+            valid_bits = 0
+
+            # Continue to next loop
+            next
+          end
+
+          tx_last_bits = 0
+          buffer[1] = 0x70 # NVB - We're sending full length byte[0..6]
+          buffer[6] = (buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5]) # Block Check Character
+
+          # Append CRC to buffer
+          buffer = append_crc(buffer)
+        else
+          tx_last_bits = current_level_known_bits % 8
+          uid_full_byte = current_level_known_bits / 8
+          all_full_byte = 2 + uid_full_byte # length of SEL + NVB + UID
+          buffer[1] = (all_full_byte << 4) + tx_last_bits # NVB
+
+          buffer_length = all_full_byte + (tx_last_bits > 0 ? 1 : 0)
+          buffer = buffer[0...buffer_length]
+        end
+
+        framing_bit = (tx_last_bits << 4) + tx_last_bits
+
+        # Select it
+        status, received_data, valid_bits = communicate_with_picc(PCD_Transceive, buffer, framing_bit)
+
+        if status != :status_ok && status != :status_collision
+          raise CommunicationError, status
+        end
+
+        if received_data.empty?
+          raise UnexpectedDataError, 'Received empty UID data'
+        end
+
+        # Append received UID into buffer if not doing full select
+        if current_level_known_bits < 32
+          # Check for last collision
+          if tx_last_bits != 0
+            buffer[-1] |= received_data.shift
+          end
+
+          buffer += received_data
+        end
+
+        # Handle collision
+        if status == :status_collision
+          collision = read_spi(CollReg)
+
+          # CollPosNotValid - We don't know where collision happened
+          raise CollisionError if (collision & 0x20) != 0
+          
+          collision_position = collision & 0x1F
+          collision_position = 32 if collision_position == 0 # Values 0-31, 0 means bit 32
+          raise CollisionError if collision_position <= current_level_known_bits
+
+          # Calculate positioin
+          current_level_known_bits = collision_position
+          uid_bit = (current_level_known_bits - 1) % 8
+
+          # Mark the collision bit
+          buffer[-1] |= (1 << uid_bit)
+        else
+          if current_level_known_bits >= 32
+            timeout = false
+            break
+          end
+          current_level_known_bits = 32 # We've already known all bits, loop again for a complete select
+        end 
+      end
+
+      # Handle timeout after 32 loops
+      if timeout
+        raise UnexpectedDataError, 'Keep receiving incomplete UID until timeout'
+      end
+
+      # We've finished current cascade level
+      # Check and collect all uid stored in buffer
+
+      # Append UID
+      uid << buffer[2] if buffer[2] != PICC_CT
+      uid << buffer[3] << buffer[4] << buffer[5]
+
+      # Check the result of full select
+      # Select Acknowledge is 1 byte + CRC16
+      raise UnexpectedDataError, 'Unknown SAK format' if received_data.size != 3 || valid_bits != 0 
+      raise IncorrectCRCError unless check_crc(received_data)
+
+      sak = received_data[0]
+      break if (sak & 0x04) == 0 # No more cascade level
+    end
+
+    return uid, sak
+  end
+
+  # Trying to restart picc
+  def reestablish_picc_communication(uid)
+    picc_halt
+    picc_request(PICC_WUPA)
+
+    begin
+      new_uid, _new_sak = picc_select
+      status = true
+    rescue CommunicationError
+      status = false
+    end
+
+    status && uid == new_uid
+  end
+
+  # Lookup PICC name using sak
+  def identify_model(sak)
+    # SAK coding separation reference:
+    # http://cache.nxp.com/documents/application_note/AN10833.pdf
+    # http://www.nxp.com/documents/application_note/130830.pdf
+    if sak & 0x04 != 0
+      return :picc_uid_not_complete
+    end
+
+    if sak & 0x02 != 0
+      return :picc_reserved_future_use
+    end
+
+    if sak & 0x08 != 0
+      if sak & 0x10 != 0
+        return :picc_mifare_4k
+      end
+
+      if sak & 0x01 != 0
+        return :picc_mifare_mini
+      end
+      
+      return :picc_mifare_1k
+    end
+
+    if sak & 0x10 != 0
+      if sak & 0x01 != 0
+        return :picc_mifare_plus_4k_sl2
+      end
+        
+      return :picc_mifare_plus_2k_sl2
+    end
+
+    if sak == 0x00
+      return :picc_mifare_ultralight
+    end
+
+    if sak & 0x20 != 0
+      return :picc_iso_14443_4
+    end
+
+    if sak & 0x40 != 0
+      return :picc_iso_18092
+    end
+
+    return :picc_unknown
+  end
+
+  # Start Crypto1 communication between reader and Mifare PICC
+  #
+  # PICC must be selected before calling for authentication
+  # Remember to deauthenticate after communication, or no new communication can be made
+  #
+  # Accept PICC_MF_AUTH_KEY_A or PICC_MF_AUTH_KEY_B command
+  # Checks datasheets for block address numbering of your PICC
+  #
+  def mifare_crypto1_authenticate(command, block_addr, sector_key, uid)
+    # Buffer[12]: {command, block_addr, sector_key[6], uid[4]}
+    buffer = [command, block_addr]
+    buffer.concat(sector_key[0..5])
+    buffer.concat(uid[0..3])
+
+    communicate_with_picc(PCD_MFAuthent, buffer)
+
+    # Check MFCrypto1On bit
+    (read_spi(Status2Reg) & 0x08) != 0
+  end
+
+  # Stop Crypto1 communication
+  def mifare_crypto1_deauthenticate
+    write_spi_clear_bitmask(Status2Reg, 0x08) # Clear MFCrypto1On bit
+  end
+
+  # Append CRC to buffer and check CRC or Mifare acknowledge
+  def picc_transceive(send_data, accept_timeout = false)
+    send_data = append_crc(send_data)
+
+    puts "Sending Data: #{send_data.map{|x|x.to_s(16).rjust(2,'0').upcase}}" if ENV['DEBUG']
+
+    # Transfer data
+    status, received_data, valid_bits = communicate_with_picc(PCD_Transceive, send_data)
+    return [] if status == :status_picc_timeout && accept_timeout
+    raise PICCTimeoutError if status == :status_picc_timeout
+    raise CommunicationError, status if status != :status_ok
+
+    puts "Received Data: #{received_data.map{|x|x.to_s(16).rjust(2,'0').upcase}}" if ENV['DEBUG']
+
+    # Data exists, check CRC and return
+    if received_data.size > 1
+      raise IncorrectCRCError unless check_crc(received_data)
+
+      return received_data[0..-3]
+    end
+
+    raise UnexpectedDataError, 'Incorrect Mifare ACK format' if received_data.size != 1 || valid_bits != 4 # ACK is 4 bits long
+    raise MifareNakError, received_data[0] if received_data[0] != PICC_MF_ACK
+
+    received_data
+  end
+
+  private
+
+  # Read from SPI communication
+  def read_spi(reg)
+    output = 0
+    PiPiper::Spi.begin do |spi|
+      spi.chip_select_active_low(true)
+      spi.bit_order Spi::MSBFIRST
+      spi.clock @spi_spd
+
+      spi.chip_select(@spi_chip) do
+        spi.write((reg << 1) & 0x7E | 0x80)
+        output = spi.read
+      end
+    end
+    output
+  end
+
+  # Write to SPI communication
+  def write_spi(reg, values)
+    PiPiper::Spi.begin do |spi|
+      spi.chip_select_active_low(true)
+      spi.bit_order Spi::MSBFIRST
+      spi.clock @spi_spd
+
+      spi.chip_select(@spi_chip) do
+        spi.write((reg << 1) & 0x7E, *values)
+      end
+    end
+  end
+
+  # Set bits by mask
+  def write_spi_set_bitmask(reg, mask)
+    value = read_spi(reg)
+    write_spi(reg, value | mask)
+  end
+
+  # Clear bits by mask
+  def write_spi_clear_bitmask(reg, mask)
+    value = read_spi(reg)
+    write_spi(reg, value & (~mask))
+  end
+
+  # PCD transceive helper
+  def communicate_with_picc(command, send_data, framing_bit = 0)
+    wait_irq = 0x00
+    wait_irq = 0x10 if command == PCD_MFAuthent
+    wait_irq = 0x30 if command == PCD_Transceive
+
+    write_spi(CommandReg, PCD_Idle)               # Stop any active command.
+    write_spi(ComIrqReg, 0x7F)                    # Clear all seven interrupt request bits
+    write_spi_set_bitmask(FIFOLevelReg, 0x80)     # FlushBuffer = 1, FIFO initialization
+    write_spi(FIFODataReg, send_data)             # Write sendData to the FIFO
+    write_spi(BitFramingReg, framing_bit)         # Bit adjustments
+    write_spi(CommandReg, command)                # Execute the command
+    if command == PCD_Transceive
+      write_spi_set_bitmask(BitFramingReg, 0x80)  # StartSend=1, transmission of data starts
+    end
+
+    # Wait for the command to complete
+    i = 2000
+    loop do
+      irq = read_spi(ComIrqReg)
+      break if (irq & wait_irq) != 0
+      return :status_picc_timeout if (irq & 0x01) != 0
+      return :status_pcd_timeout if i == 0
+      i -= 1
+    end
+
+    # Check for error
+    error = read_spi(ErrorReg)
+    return :status_error if (error & 0x13) != 0 # BufferOvfl ParityErr ProtocolErr
+
+    # Receiving data
+    received_data = []
+    data_length = read_spi(FIFOLevelReg)
+    while data_length > 0 do
+      data = read_spi(FIFODataReg)
+      received_data << data
+      data_length -=1
+    end
+    valid_bits = read_spi(ControlReg) & 0x07
+
+    status = :status_ok
+    status = :status_collision if (error & 0x08) != 0 # CollErr
+
+    return status, received_data, valid_bits
+  end
+
+  def calculate_crc(data)
+    write_spi(CommandReg, PCD_Idle)               # Stop any active command.
+    write_spi(DivIrqReg, 0x04)                    # Clear the CRCIRq interrupt request bit
+    write_spi_set_bitmask(FIFOLevelReg, 0x80)     # FlushBuffer = 1, FIFO initialization
+    write_spi(FIFODataReg, data)                  # Write data to the FIFO
+    write_spi(CommandReg, PCD_CalcCRC)            # Start the calculation
+
+    # Wait for the command to complete
+    i = 5000
+    loop do
+      irq = read_spi(DivIrqReg)
+      break if (irq & 0x04) != 0
+      raise PCDTimeoutError, 'Error calculating CRC' if i == 0
+      i -= 1
+    end
+
+    write_spi(CommandReg, PCD_Idle)               # Stop calculating CRC for new content in the FIFO.
+
+    [read_spi(CRCResultRegL), read_spi(CRCResultRegH)]
+  end
+
+  def append_crc(data)
+    data + calculate_crc(data)
+  end
+
+  def check_crc(data)
+    raise UnexpectedDataError, 'Data too short for CRC check' if data.size < 3
+
+    data = data.dup
+    crc = data.pop(2)
+
+    crc == calculate_crc(data)
+  end
+
+end