rvvm 1.2.0 → 1.2.2

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data/CHANGELOG.md

@@ -193,3 +193,19 @@
 2. RVvM config file versions and regeneration
 3. Exit on failing compilation/elaboration/simulation
 
+## [1.2.2] - 2024-09-19
+
+### Added:
+
+1. Script exit on failing compilation/elaboration/simulation/...
+2. Option to ignore shell command errors
+3. Docs
+
+### Fixed:
+
+1. Syntax errors in RBS files
+
+### TBI
+
+1. Custom waveform dump file name generated by simulation
+2. RVvM config file version and regeneration

data/README.md

@@ -16,24 +16,33 @@ If bundler is not being used to manage dependencies, install the gem by executin
 gem install rvvm
 ```
 
+## Requirements
+
+1. [Vivado Design Suite](https://www.xilinx.com/support/download.html)
+2. **Xilinx Vivado** binaries in your `PATH` and `XILINX_PATH` env variable pointing to your Vivado install dir or sourced `settings64` Vivado script
+
 ## Usage
 
-### Project management
+To get full `rvvm` usage docs use `-h` or `--help` option.
+
+### Project creation
 
 Create a new RVvM project using `-n` or `--new`.
 
 eg.:
-```
+```bash
 rvvm -n best_rtl_project
 ```
 
 Whitespaces in project name and or generated templates are not allowed.
 
-To manage an RVvM project use the `rvvm` script from inside an RVvM project root or its config directory.
+### Project management
+
+To manage an **RVvM** project use the `rvvm` script inside the root of an **RVvM** project or its config directory.
 
 #### Project structure
 
-```
+```bash
 RvvM_project
 ├── design              # SV design sources
 │   ├── itf
@@ -61,7 +70,152 @@ RvvM_project
         └── src
 ```
 
-To get full `rvvm` usage docs use `-h` or `--help` option.
+### Project configuration
+
+RVvM project configuration is stored in its config directory in the `<project root>/rvvm/rvvmconf.json` json file.
+
+You can configure the project by editing its config file. Individual settings of the configuration can be owerwritten @ runtime using specific arguments (see `-h`/`--help`).
+
+The `rvvmconf.json` configuration consists of:
+
+```json
+# example configuration:
+# .../best_rtl_project/rvvm/rvvmconf.json:
+
+{
+  "project": {
+    "name": "best_rtl_project",
+    "path": "/home/mrbya/mycodes/ruby/rvvm/best_rtl_project",
+    "rvvmDir": "rvvm",
+    "logDir": "logs",
+    "company": " "
+  },
+
+  "compilation": {
+    "list": "best_rtl_project_compile_list.f",
+    "logDir": "comp",
+    "log": "comp.log",
+    "args": "-L uvm"
+  },
+
+  "dpi": {
+    "dpilib": 0,
+    "list": "dpi_compile_list.f",
+    "args": " "
+  },
+
+  "elaboration": {
+    "tbTop": "best_rtl_project_tb_top",
+    "tb": "best_rtl_project_tb",
+    "timescale": "1ns/1ps",
+    "customdpilib": "",
+    "logDir": "elab",
+    "log": "elab.log",
+    "args": " "
+  },
+
+  "simulation": {
+    "logDir": "sim",
+    "log": "${testname}.log",
+    "verbosity": "LOW",
+    "defTest": " ",
+    "batch": 0,
+    "testlist": [" "],
+    "args": " "
+  }
+}
+
+```
+
+#### Project
+
+| Parameter | Default Value                      | Description                         |
+| :-------: | ---------------------------------- | ----------------------------------- |
+|  `name`   | Name of the project @ creation     | RVvM project name                   |
+|  `path`   | Path to the project @ its creation | Absolute path to the project        |
+| `rvvmDir` | `rvvm`                             | Project config and output directory |
+| `logDir`  | `log`                              | Log output directory root           |
+| `company` | empty                              | Company name                        |
+
+#### Compilation
+
+| Parameter | Default Value                   | Description                                            |
+| :-------: | ------------------------------- | ------------------------------------------------------ |
+|  `list`   | `<project name>_compile_list.f` | Path to project HDL source files compile list          |
+| `logDir`  | `comp`                          | Subdirectory for `xvlog` logs inside `project: logDir` |
+|   `log`   | `comp.log`                      | `xvlog` log file name                                  |
+|  `args`   | `-L uvm`                        | Additional `xvlog` arguments                           |
+
+#### DPI
+
+| Parameter | Default value        | Description                                                                                         |
+| :-------: | -------------------- | --------------------------------------------------------------------------------------------------- |
+| `dpilib`  | `0`                  | Switch activating DPI-C compilation when running `--all` and dpi library linkage during elaboration |
+|  `list`   | `dpi_compile_list.f` | Path to DPI-C source files compile list                                                             |
+|  `args`   | empty                | Additional `xsc` arguments                                                                          |
+
+#### Elaboration
+
+|   Parameter    | Default value          | Description                                                               |
+| :------------: | ---------------------- | ------------------------------------------------------------------------- |
+|    `tbTop`     | `<projec name>_tb_top` | Testbench top module name                                                 |
+|      `tb`      | `<project name>_tb`    | Elaborated testbench snapshot name                                        |
+|  `timescale`   | `1ns/1ps`              | Elaborated testbench timescale                                            |
+| `customdpilib` | empty                  | Path to a custom DPI-C library to link into a snapshot during elaboration |
+|    `logDir`    | `elab`                 | Subdirectory for `xelab` logs inside `project: logDir`                    |
+|      log       | `elab.log`             | `xelab` log file name                                                     |
+|     `args`     | empty                  | Additional `xelab` arguments                                              |
+
+#### Simulation
+
+|  Parameter  | Default value     | Description                                                                                                                   |
+| :---------: | ----------------- | ----------------------------------------------------------------------------------------------------------------------------- |
+|  `logDir`   | `sim`             | Subdirectory for `xsim` logs inside `project: logDir`                                                                         |
+|    `log`    | `${testname}.log` | `xsim` log file name                                                                                                          |
+| `verbosity` | `LOW`             | UVM reporting verbosity                                                                                                       |
+|  `defTest`  | empty             | Default UVM test to be run using `--run`                                                                                      |
+|   `batch`   | `0`               | Switch activating batch UVM test simulation: run multiple UVM tests provided in `simulation: testlist` or using `--testlist`. |
+| `testlist`  | empty array       | Provide an array of UVM test names to run during a batch simulation.                                                          |
+|   `args`    | empty             | Additional `xsim` arguments                                                                                                   |
+### Tmplate file generation
+
+RVvM can generate SystemVerilog module, interface, package and generic template files to ease your SV project development.
+
+To generate module templates use:
+
+- `-m --module <NAME>` - to generate a SV module template
+- `-i --itf <NAME>` - to generate a SV interface template
+- `-p --pkg <NAME>` - to generate a SV package template
+- `--svfile <NAME>` - to generate a generic SV file template
+
+Default paths for template file generations are:
+
+```bash
+RVvM project root
+└── design
+    ├── itf  # for SV interfaces
+    ├── pkg  # for SV packages
+    └── src  # for SV modules and generic SV files
+```
+
+You can modify generated template path using `--path <PATH>` (excluding template file name) or `--here`.
+
+### Using Xilinx Vivado tools
+
+To compile/elaborate/simulate,... yout RVvM project use the `rvvm` script from inside an RVvM project root or its config directory.
+
+- `-c --comp` - to compile HDL sources
+- `-d --dpi` - to compile C/C++ DPI-C library sources
+- `-e --elab` - to elaborate project testbench into a snapshot
+- `-r --run` - to run UVM test simulation (use `-b --batch` to run a batch of simulations)
+- `-a --all` - to run `--comp`, `--dpi` (when configured), `--elab`, `--run`
+- `--runsv` - to run pure SV/V simulation
+
+Use `-w --wave` to dump signal waveforms
+
+- `-u --gui` - to open dumped waveforms in Vivado GUI
+- `-g --gencov` - to generate UVM test functional coverage report
+- `--covreport` - to open coverage report dashboard
 
 ## Development
 

data/Rakefile

@@ -4,9 +4,3 @@ require "bundler/gem_tasks"
 require "minitest/test_task"
 
 Minitest::TestTask.create
-
-# require "rubocop/rake_task"
-#
-# RuboCop::RakeTask.new
-#
-# task default: %i[test rubocop]