rubyboy 0.1.0 → 0.2.0

data/lib/roms/cpu_instrs/readme.txt

@@ -0,0 +1,119 @@
+Game Boy CPU Instruction Behavior Test
+--------------------------------------
+This ROM tests the behavior of all CPU instructions except STOP and the
+11 illegal opcodes. The tests are fairly thorough, running instructions
+with boundary data and verifying both the result and that other
+registers are not modified. Instructions which perform the same
+operation on different registers are each tested just as thoroughly, in
+case an emulator implements each independently. Some sub-tests take half
+minute to complete.
+
+Failed instructions are listed as
+
+	[CB] opcode
+
+Some errors cannot of course be diagnosed properly, since the test
+framework itself relies on basic instruction behavior being correct.
+
+
+Internal operation
+------------------
+The main tests use a framework that runs each instruction in a loop,
+varying the register values on input and examining them on output.
+Rather than keep a table of correct values, it simply calculates a
+CRC-32 checksum of all the output, then compares this with the correct
+value. Instructions are divided into several groups, each with a
+different set of input values suited for their behavior; for example,
+the bit test instructions are fed $01, $02, $04 ... $40, $80, to ensure
+each bit is handled properly, while the arithmetic instructions are fed
+$01, $0F, $10, $7F, $FF, to exercise carry and half-carry. A few
+instructions require a custom test due to their uniqueness.
+
+
+Multi-ROM
+---------
+In the main directory is a single ROM which runs all the tests. It
+prints a test's number, runs the test, then "ok" if it passes, otherwise
+a failure code. Once all tests have completed it either reports that all
+tests passed, or prints the number of failed tests. Finally, it makes
+several beeps. If a test fails, it can be run on its own by finding the
+corresponding ROM in individual/.
+
+Ths compact format on screen is to avoid having the results scroll off
+the top, so the test can be started and allowed to run without having to
+constantly monitor the display. 
+
+Currently there is no well-defined way for an emulator test rig to
+programatically find the result of the test; contact me if you're trying
+to do completely automated testing of your emulator. One simple approach
+is to take a screenshot after all tests have run, or even just a
+checksum of one, and compare this with a previous run.
+
+
+Failure codes
+-------------
+Failed tests may print a failure code, and also short description of the
+problem. For more information about a failure code, look in the
+corresponding source file in source/; the point in the code where
+"set_test n" occurs is where that failure code will be generated.
+Failure code 1 is a general failure of the test; any further information
+will be printed.
+
+Note that once a sub-test fails, no further tests for that file are run.
+
+
+Console output
+--------------
+Information is printed on screen in a way that needs only minimum LCD
+support, and won't hang if LCD output isn't supported at all.
+Specifically, while polling LY to wait for vblank, it will time out if
+it takes too long, so LY always reading back as the same value won't
+hang the test. It's also OK if scrolling isn't supported; in this case,
+text will appear starting at the top of the screen.
+
+Everything printed on screen is also sent to the game link port by
+writing the character to SB, then writing $81 to SC. This is useful for
+tests which print lots of information that scrolls off screen.
+
+
+Source code
+-----------
+Source code is included for all tests, in source/. It can be used to
+build the individual test ROMs. Code for the multi test isn't included
+due to the complexity of putting everything together.
+
+Code is written for the wla-dx assembler. To assemble a particular test,
+execute
+
+	wla -o "source_filename.s" test.o
+	wlalink linkfile test.gb
+
+Test code uses a common shell framework contained in common/.
+
+
+Internal framework operation
+----------------------------
+Tests use a common framework for setting things up, reporting results,
+and ending. All files first include "shell.inc", which sets up the ROM
+header and shell code, and includes other commonly-used modules.
+
+One oddity is that test code is first copied to internal RAM at $D000,
+then executed there. This allows self-modification, and ensures the code
+is executed the same way it is on my devcart, which doesn't have a
+rewritable ROM as most do.
+
+Some macros are used to simplify common tasks:
+
+	Macro               Behavior
+	- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	wreg addr,data      Writes data to addr using LDH
+	lda  addr           Loads byte from addr into A using LDH
+	sta  addr           Stores A at addr using LDH
+	delay n             Delays n cycles, where NOP = 1 cycle
+	delay_msec n        Delays n milliseconds
+	set_test n,"Cause"  Sets failure code and optional string
+
+Routines and macros are documented where they are defined.
+
+-- 
+Shay Green <gblargg@gmail.com>

data/lib/roms/instr_timing/readme.txt

@@ -0,0 +1,139 @@
+Game Boy CPU Instruction Timing Test
+------------------------------------
+This ROM tests the timings of all CPU instructions except HALT, STOP,
+and the 11 illegal opcodes. For conditional instructions, it tests taken
+and not taken timings. This test requires proper timer operation (TAC,
+TIMA, TMA).
+
+Failed instructions are listed as
+
+	[CB] opcode:measured time-correct time
+
+Times are in terms of instruction cycles, where NOP takes one cycle.
+
+
+Verified cycle timing tables
+----------------------------
+The test internally uses a table of proper cycle times, which can be
+used in an emulator to ensure proper timing. The only changes below are
+removal of the .byte prefixes, and addition of commas at the ends, so
+that they can be used without changes in most programming languages. For
+added correctness assurance, the original tables can be found at the end
+of the source code.
+
+Normal instructions:
+
+	1,3,2,2,1,1,2,1,5,2,2,2,1,1,2,1,
+	0,3,2,2,1,1,2,1,3,2,2,2,1,1,2,1,
+	2,3,2,2,1,1,2,1,2,2,2,2,1,1,2,1,
+	2,3,2,2,3,3,3,1,2,2,2,2,1,1,2,1,
+	1,1,1,1,1,1,2,1,1,1,1,1,1,1,2,1,
+	1,1,1,1,1,1,2,1,1,1,1,1,1,1,2,1,
+	1,1,1,1,1,1,2,1,1,1,1,1,1,1,2,1,
+	2,2,2,2,2,2,0,2,1,1,1,1,1,1,2,1,
+	1,1,1,1,1,1,2,1,1,1,1,1,1,1,2,1,
+	1,1,1,1,1,1,2,1,1,1,1,1,1,1,2,1,
+	1,1,1,1,1,1,2,1,1,1,1,1,1,1,2,1,
+	1,1,1,1,1,1,2,1,1,1,1,1,1,1,2,1,
+	2,3,3,4,3,4,2,4,2,4,3,0,3,6,2,4,
+	2,3,3,0,3,4,2,4,2,4,3,0,3,0,2,4,
+	3,3,2,0,0,4,2,4,4,1,4,0,0,0,2,4,
+	3,3,2,1,0,4,2,4,3,2,4,1,0,0,2,4
+
+CB-prefixed instructions:
+
+	2,2,2,2,2,2,4,2,2,2,2,2,2,2,4,2,
+	2,2,2,2,2,2,4,2,2,2,2,2,2,2,4,2,
+	2,2,2,2,2,2,4,2,2,2,2,2,2,2,4,2,
+	2,2,2,2,2,2,4,2,2,2,2,2,2,2,4,2,
+	2,2,2,2,2,2,3,2,2,2,2,2,2,2,3,2,
+	2,2,2,2,2,2,3,2,2,2,2,2,2,2,3,2,
+	2,2,2,2,2,2,3,2,2,2,2,2,2,2,3,2,
+	2,2,2,2,2,2,3,2,2,2,2,2,2,2,3,2,
+	2,2,2,2,2,2,4,2,2,2,2,2,2,2,4,2,
+	2,2,2,2,2,2,4,2,2,2,2,2,2,2,4,2,
+	2,2,2,2,2,2,4,2,2,2,2,2,2,2,4,2,
+	2,2,2,2,2,2,4,2,2,2,2,2,2,2,4,2,
+	2,2,2,2,2,2,4,2,2,2,2,2,2,2,4,2,
+	2,2,2,2,2,2,4,2,2,2,2,2,2,2,4,2,
+	2,2,2,2,2,2,4,2,2,2,2,2,2,2,4,2,
+	2,2,2,2,2,2,4,2,2,2,2,2,2,2,4,2
+
+
+Internal operation
+------------------
+Before each instruction is executed, the test sets up registers and
+memory in such a way that the instruction will cleanly execute and then
+end up at a common destination, without trashing anything important. The
+timing itself is done by first synchronizing to the timer via a loop,
+executing the instruction, then using a similar loop to determine how
+many clocks elapsed.
+
+
+Failure codes
+-------------
+Failed tests may print a failure code, and also short description of the
+problem. For more information about a failure code, look in the
+corresponding source file in source/; the point in the code where
+"set_test n" occurs is where that failure code will be generated.
+Failure code 1 is a general failure of the test; any further information
+will be printed.
+
+Note that once a sub-test fails, no further tests for that file are run.
+
+
+Console output
+--------------
+Information is printed on screen in a way that needs only minimum LCD
+support, and won't hang if LCD output isn't supported at all.
+Specifically, while polling LY to wait for vblank, it will time out if
+it takes too long, so LY always reading back as the same value won't
+hang the test. It's also OK if scrolling isn't supported; in this case,
+text will appear starting at the top of the screen.
+
+Everything printed on screen is also sent to the game link port by
+writing the character to SB, then writing $81 to SC. This is useful for
+tests which print lots of information that scrolls off screen.
+
+
+Source code
+-----------
+Source code is included for all tests, in source/. It can be used to
+build the individual test ROMs. Code for the multi test isn't included
+due to the complexity of putting everything together.
+
+Code is written for the wla-dx assembler. To assemble a particular test,
+execute
+
+	wla -o "source_filename.s" test.o
+	wlalink linkfile test.gb
+
+Test code uses a common shell framework contained in common/.
+
+
+Internal framework operation
+----------------------------
+Tests use a common framework for setting things up, reporting results,
+and ending. All files first include "shell.inc", which sets up the ROM
+header and shell code, and includes other commonly-used modules.
+
+One oddity is that test code is first copied to internal RAM at $D000,
+then executed there. This allows self-modification, and ensures the code
+is executed the same way it is on my devcart, which doesn't have a
+rewritable ROM as most do.
+
+Some macros are used to simplify common tasks:
+
+	Macro               Behavior
+	- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+	wreg addr,data      Writes data to addr using LDH
+	lda  addr           Loads byte from addr into A using LDH
+	sta  addr           Stores A at addr using LDH
+	delay n             Delays n cycles, where NOP = 1 cycle
+	delay_msec n        Delays n milliseconds
+	set_test n,"Cause"  Sets failure code and optional string
+
+Routines and macros are documented where they are defined.
+
+-- 
+Shay Green <gblargg@gmail.com>

data/lib/rubyboy/bus.rb

@@ -1,62 +1,201 @@
 # frozen_string_literal: true
 
+require_relative 'cartridge/factory'
+require_relative 'interrupt'
+require_relative 'timer'
+
 module Rubyboy
   class Bus
-    attr_accessor :ppu, :rom
+    attr_accessor :ppu, :rom, :interrupt
 
-    def initialize(ppu, rom)
+    def initialize(ppu, rom, timer, interrupt)
       @ppu = ppu
       @rom = rom
+      @ram = Ram.new
+      @mbc = Cartridge::Factory.create(rom, @ram)
+
+      @interrupt = interrupt
+      @timer = timer
+
+      @oam = Array.new(0xa0, 0)
+
+      @tmp = {}
     end
 
     def read_byte(addr)
       case addr
       when 0x0000..0x7fff
-        @rom.data[addr]
+        @mbc.read_byte(addr)
       when 0x8000..0x9fff
         @ppu.vram[addr - 0x8000]
-      when 0xff26
-        # nr52
+      when 0xa000..0xdfff
+        @mbc.read_byte(addr)
+      when 0xe000..0xfdff
+        # echo ram
+      when 0xfe00..0xfe9f
+        @oam[addr - 0xfe00]
+      when 0xfea0..0xfeff
+        # unused
+        0xff
+      when 0xff00
+        # joypad
+        @tmp[addr] ||= 0
+      when 0xff01..0xff02
+        # serial
+        @tmp[addr] ||= 0
+      when 0xff04..0xff07
+        @timer.read_byte(addr)
+      when 0xff0f
+        @interrupt.if
+      when 0xff10..0xff26
+        # sound
+        @tmp[addr] ||= 0
+      when 0xff30..0xff3f
+        # wave pattern ram
+        @tmp[addr] ||= 0
       when 0xff40
         @ppu.lcdc
+      when 0xff41
+        # stat
+        @tmp[addr] ||= 0
       when 0xff42
         @ppu.scy
       when 0xff43
         @ppu.scx
       when 0xff44
         @ppu.ly
+      when 0xff45
+        @ppu.lyc
+      when 0xff46
+        # dma
+        @tmp[addr] ||= 0
       when 0xff47
         @ppu.bgp
+      when 0xff48
+        # obp0
+        @tmp[addr] ||= 0
+      when 0xff49
+        # obp1
+        @tmp[addr] ||= 0
+      when 0xff4a
+        # wy
+        @tmp[addr] ||= 0
+      when 0xff4b
+        # wx
+        @tmp[addr] ||= 0
+      when 0xff4f
+        # vbk
+        @tmp[addr] ||= 0
+      when 0xff50
+        # boot rom
+        @tmp[addr] ||= 0
+      when 0xff51..0xff55
+        # hdma
+        @tmp[addr] ||= 0
+      when 0xff68..0xff6b
+        # bgp
+        @tmp[addr] ||= 0
+      when 0xff70
+        # svbk
+        @tmp[addr] ||= 0
+      when 0xff80..0xfffe
+        @ram.hram[addr - 0xff80]
+      when 0xffff
+        @interrupt.ie
       else
-        raise "not implemented: write_byte #{addr}"
+        0xff
       end
     end
 
     def write_byte(addr, value)
       case addr
       when 0x0000..0x7fff
-        @rom.data[addr] = value
+        @mbc.write_byte(addr, value)
       when 0x8000..0x9fff
         @ppu.vram[addr - 0x8000] = value
-      when 0xff26
-        # nr52
+      when 0xa000..0xdfff
+        @mbc.write_byte(addr, value)
+      when 0xe000..0xfdff
+        # echo ram
+      when 0xfe00..0xfe9f
+        @oam[addr - 0xfe00] = value
+      when 0xfea0..0xfeff
+        # unused
+      when 0xff00
+        # joypad
+        @tmp[addr] = value
+      when 0xff01..0xff02
+        # serial
+        @tmp[addr] = value
+      when 0xff04..0xff07
+        @timer.write_byte(addr, value)
+      when 0xff0f
+        @interrupt.if = value
+      when 0xff10..0xff26
+        # sound
+        @tmp[addr] = value
+      when 0xff30..0xff3f
+        # wave pattern ram
+        @tmp[addr] = value
       when 0xff40
         @ppu.lcdc = value
+      when 0xff41
+        # stat
+        @tmp[addr] = value
       when 0xff42
         @ppu.scy = value
       when 0xff43
         @ppu.scx = value
       when 0xff44
         @ppu.ly = value
+      when 0xff45
+        @ppu.lyc = value
+      when 0xff46
+        # dma
+        @tmp[addr] = value
       when 0xff47
         @ppu.bgp = value
-      else
-        raise "not implemented: write_byte #{addr}"
+      when 0xff48
+        # obp0
+        @tmp[addr] = value
+      when 0xff49
+        # obp1
+        @tmp[addr] = value
+      when 0xff4a
+        # wy
+        @tmp[addr] = value
+      when 0xff4b
+        # wx
+        @tmp[addr] = value
+      when 0xff4f
+        # vbk
+        @tmp[addr] = value
+      when 0xff50
+        # boot rom
+        @tmp[addr] = value
+      when 0xff51..0xff55
+        # hdma
+        @tmp[addr] = value
+      when 0xff68..0xff6b
+        # bgp
+        @tmp[addr] = value
+      when 0xff70
+        # svbk
+        @tmp[addr] = value
+      when 0xff80..0xfffe
+        @ram.hram[addr - 0xff80] = value
+      when 0xffff
+        @interrupt.ie = value
       end
     end
 
     def read_word(addr)
       read_byte(addr) + (read_byte(addr + 1) << 8)
     end
+
+    def write_word(addr, value)
+      write_byte(addr, value & 0xff)
+      write_byte(addr + 1, value >> 8)
+    end
   end
 end

data/lib/rubyboy/cartridge/factory.rb

@@ -0,0 +1,21 @@
+# frozen_string_literal: true
+
+require_relative 'nombc'
+require_relative 'mbc1'
+
+module Rubyboy
+  module Cartridge
+    class Factory
+      def self.create(rom, ram)
+        case rom.cartridge_type
+        when 0x00
+          Nombc.new(rom)
+        when 0x01..0x03
+          Mbc1.new(rom, ram)
+        else
+          raise "Unsupported cartridge type: #{cartridge_type}"
+        end
+      end
+    end
+  end
+end

data/lib/rubyboy/cartridge/mbc1.rb

@@ -0,0 +1,71 @@
+# frozen_string_literal: true
+
+require_relative '../ram'
+
+module Rubyboy
+  module Cartridge
+    class Mbc1
+      def initialize(rom, ram)
+        @rom = rom
+        @ram = ram
+        @rom_bank = 1
+        @ram_bank = 0
+        @ram_enable = false
+        @ram_banking_mode = false
+      end
+
+      def read_byte(addr)
+        case addr
+        when 0x0000..0x3fff
+          @rom.data[addr]
+        when 0x4000..0x7fff
+          @rom.data[addr + (@rom_bank - 1) * 0x4000]
+        when 0xa000..0xbfff
+          if @ram_enable
+            if @ram_banking_mode
+              @ram.eram[addr - 0xa000 + @ram_bank * 0x800]
+            else
+              @ram.eram[addr - 0xa000]
+            end
+          else
+            0xff
+          end
+        when 0xc000..0xcfff
+          @ram.wram1[addr - 0xc000]
+        when 0xd000..0xdfff
+          @ram.wram2[addr - 0xd000]
+        else
+          raise "not implemented: read_byte #{addr}"
+        end
+      end
+
+      def write_byte(addr, value)
+        case addr
+        when 0x0000..0x1fff
+          @ram_enable = value & 0x0f == 0x0a
+          @rom.data[addr] = value
+        when 0x2000..0x3fff
+          @rom_bank = value & 0x1f
+          @rom_bank = 1 if @rom_bank.zero?
+          @rom.data[addr] = value
+        when 0x4000..0x5fff
+          @ram_bank = value & 0x03
+        when 0x6000..0x7fff
+          @ram_banking_mode = value & 0x01 == 0x01
+        when 0xa000..0xbfff
+          if @ram_enable
+            if @ram_banking_mode
+              @ram.eram[addr - 0xa000 + @ram_bank * 0x800] = value
+            else
+              @ram.eram[addr - 0xa000] = value
+            end
+          end
+        when 0xc000..0xcfff
+          @ram.wram1[addr - 0xc000] = value
+        when 0xd000..0xdfff
+          @ram.wram2[addr - 0xd000] = value
+        end
+      end
+    end
+  end
+end

data/lib/rubyboy/cartridge/nombc.rb

@@ -0,0 +1,19 @@
+# frozen_string_literal: true
+
+module Rubyboy
+  module Cartridge
+    class Nombc
+      def initialize(rom)
+        @rom = rom
+      end
+
+      def read_byte(addr)
+        @rom.data[addr]
+      end
+
+      def write_byte(_addr, _value)
+        # do nothing
+      end
+    end
+  end
+end