ruby-vpi 9.0.0 → 10.0.0

data/HISTORY

@@ -12,13 +12,55 @@ We _strictly_ follow the RubyGems project's "rational versioning policy":http://
 fn1. C. Gross, "Explaining Open Source Version Numbers", [Online document], 2005 Nov 28, [cited 2006 Aug 27], Available HTTP: "http://ablog.apress.com/?p=738":http://ablog.apress.com/?p=738
 
 
+h1. Version 10.0.0 (2006-11-05)
+
+h2. Summary
+
+This release adds the ability to access a handle's children and reduces the amount of code produced by the automated test generator.
+
+h2. Acknowledgment
+
+Thanks to Matt Fischler for finding the problem of misdirected compilation errors in Verilog benches.
+
+h2. Notice
+
+* The way in which Ruby-VPI and generated tests interact has changed: the design is now a VPI handle object and the @design.rb@ and @proto.rb@ files define "singleton methods":http://wiki.rubygarden.org/Ruby/page/show/SingletonTutorial for that object.
+** I suggest that you regenerate your existing tests (just run *generate_test.rb* again) whilst employing the service of a text merging tool (see the user manual).
+
+* You can now access a handle's children by simply calling methods on it. In the event that a child handle has the same name as a VPI property, the child is given priority. However, you can always access VPI properties explicitly via the @get_value@ and @put_value@ methods.
+
+* *generate_test.rb* no longer accepts the @-s@ and @-u@ options. Use their longer counterparts @--rspec@ and @--xunit@ instead.
+
+
+h2. Detail
+
+h3. Automated test generator
+
+* Generated Verilog benches no longer divert compilation errors from Verilog design files. That is, if the Verilog simulator finds compilation errors in a Verilog design file, it will report that the Verilog design file is at fault (instead of reporting that the generated Verilog bench is at fault).
+
+* The user is now notified when a backup of an existing file is made.
+
+* Generated tests have been greatly simplified to reduce the amount of work for the user.
+** The design is now just a handle to the module in the Verilog bench.
+** @include Vpi@ and @@design@ are no longer generated.
+** The tutorial and examples have been updated accordingly.
+
+h3. User manual
+
+* Revised the stylesheet to make disjoint sections readily distinguishable from eachother, through generous spacing and minor coloring.
+
+* Added tips about @ruby-vpi/runner_proxy@, @rake -T@, and using *kdiff3* with *generate_test.rb*.
+
+* Moved installation information into a new "setup" chapter.
+
+
 h1. Version 9.0.0 (2006-10-28)
 
 h2. Summary
 
 This release improves the automated test generator and adds new content to the user manual.
 
-h2. Acknowledgments
+h2. Acknowledgment
 
 Thanks to Matt Fischler for helping test and debug the installation of Ruby-VPI on Windows.
 
@@ -26,7 +68,7 @@ h2. Notice
 
 * The command-line options for @generate_test.rb@ have changed. Run the command @generate_test.rb --help@ for details.
 
-h2. Details
+h2. Detail
 
 * Test runners now attempt to resolve paths in @SIMULATOR_SOURCES@ by searching for them within the directories specified in @SIMULATOR_INCLUDES@.
 
@@ -54,7 +96,7 @@ h2. Summary
 
 This release simplifies configuration of generated tests.
 
-h2. Acknowledgments
+h2. Acknowledgment
 
 Thanks to "students in CMPE-126":http://www.soe.ucsc.edu/classes/cmpe126/Fall06/ for their constructive criticism.
 
@@ -62,7 +104,7 @@ h2. Notice
 
 * Generated runners now have a @SIMULATOR_INCLUDES@ array, whose entries specify places where Verilog source files, needed by the Verilog design, reside.
 
-h2. Details
+h2. Detail
 
 * Generated Verilog benches now inherit all @`include@ and @`define@ directives from the Verilog design in a simpler manner.
 * A generated test no longer requires its Verilog design to reside in the same directory.
@@ -79,7 +121,7 @@ h2. Notice
 
 * The *vpi_util* library has been renamed to *vpi*. This change should not affect your code unless you explicitly imported this library via @require 'ruby-vpi/vpi_util'@. In which case, you should update your code to use @require 'ruby-vpi/vpi'@ accordingly.
 
-h2. Details
+h2. Detail
 
 * An integer library has been added to simplify common tasks related to hardware and the binary number system. You can import this library for use via @require 'ruby-vpi/integer'@.
 
@@ -97,7 +139,7 @@ h2. Notice
 * The @PROTO@ environment variable has been renamed to @PROTOTYPE@.
 ** In addition to using @unset@, you can now disable simulation of the prototype by assigning an empty value to this variable.
 
-h2. Details
+h2. Detail
 
 * We now use "Darcs":http://darcs.net for revision control, instead of Subversion. The source repository can now be accessed at "http://ruby-vpi.rubyforge.org/src/ruby-vpi":http://ruby-vpi.rubyforge.org/src/ruby-vpi.
 
@@ -120,10 +162,10 @@ This release fixes a bug in generated Verilog benches, includes parsed constants
 h2. Notice
 
 * Handles now have two new methods:
-** @handle.x?@ -- checks if the logic value is "don't care"
-** @handle.z?@ -- checks if the logic value is high impedance
+** @handle.x?@ checks if the logic value is "don't care"
+** @handle.z?@ checks if the logic value is high impedance
 
-h2. Details
+h2. Detail
 
 * Module instantiation code in generated Verilog benches has been fixed. Whitespace between the module type and instance variable was missing.
 
@@ -139,11 +181,11 @@ h2. Summary
 
 This release adds initial[1] support for code coverage analysis via the "rcov library":http://eigenclass.org/hiki.rb?rcov.
 
-h2. Acknowledgments
+h2. Acknowledgment
 
 Thanks to Mauricio Fernandez for helping me use rcov without its runner.
 
-h2. Details
+h2. Detail
 
 * Added initial[1] support for code coverage analysis, which can be enabled by setting the @COVERAGE@ environment variable to a non-empty value before running a test.
 ** For example, you can run a test with the GPL Cver simulator while enabling the generation of code coverage reports as follows: @export COVERAGE=1; rake cver@
@@ -159,7 +201,7 @@ h2. Summary
 
 This release simplifies running of multiple tests, restores compatibility with Synopsys VCS, and better integrates with RubyGems.
 
-h2. Details
+h2. Detail
 
 * Added @lib/ruby-vpi/runner_proxy@ library which, when embedded into a Rakefile, runs all generated tests in the working directory with any specified arguments. For example, have a look at the @samp/counter/Rakefile@ file.
 
@@ -178,12 +220,10 @@ h2. Summary
 
 This release distributes Ruby-VPI as a gem, improves portability of generated tests, and fixes a bug.
 
-h2. Details
+h2. Notice
 
 * @put_value()@ now accomodates register value overflows when verifying the value it has written.
 
-* Ruby-VPI is now distributed only as a "source gem":http://www.rubygems.org. You can decompress the gem without installing it onto your system by running the command @gem install -i output_directory ruby-vpi-7.0.0.gem@. In addition, you can still obtain the source code directly from the Subversion repository.
-
 * The test generator's templates and the examples have been updated as follows:
 ** Test runners no longer have to specify the path to Ruby-VPI installation directory. Instead, they simply @require 'ruby-vpi/runner'@. Thus, you can run your tests on any machine with Ruby-VPI without having to know where it is installed.
 ** Ruby benches now invoke @RubyVPI.init_bench@ instead of @require 'bench'; setup_bench@ to become initialized.
@@ -192,6 +232,10 @@ h2. Details
 
 * The @src/@ directory has been renamed to @ext/@ to follow RubyGems convention.
 
+h2. Detail
+
+* Ruby-VPI is now distributed only as a "source gem":http://www.rubygems.org. You can decompress the gem without installing it onto your system by running the command @gem install -i output_directory ruby-vpi-7.0.0.gem@. In addition, you can still obtain the source code directly from the Subversion repository.
+
 * The tools in @bin/@ become available in your system's @bin/@ directory when the gem is installed.
 ** Usage and help information has been added to the @header_to_ruby.rb@ tool.
 
@@ -208,13 +252,16 @@ h2. Summary
 
 This release adds support for the GPL Cver simulator, provides both binary and source packages, and explicitly defines the version numbering system.
 
-h2. Details
-
-* The GPL Cver simulator is now supported.
+h2. Notice
 
 * Ruby-VPI now only needs to be built once.
 ** You can run tests with different Verilog simulators without having to re-compile Ruby-VPI.
-** Release packages are now available in both source and binary form.
+
+h2. Detail
+
+* The GPL Cver simulator is now supported.
+
+* Release packages are now available in both source and binary form.
 
 * The RSpec based specifications for the counter example now use the @should_equal@ instead of the @should_be@ assertion, because the latter ensures strict equivalence. For instance, it will fail when a Fixnum is compared to a Bignum.
 
@@ -241,7 +288,13 @@ h2. Summary
 
 This release beautifies generated tests, adds checks to find signal width bugs, and includes a new tool.
 
-h2. Details
+h2. Notice
+
+* @put_value()@ now returns the value it puts. Therefore, it is easier to chain together a series of assignments: @foo.intVal = bar.intVal = baz.intVal = 10@
+
+* @put_value()@ now verifies that the value it puts was written correctly. This helps to find bugs regarding invalid assumptions about the number of bits supported by a signal.
+
+h2. Detail
 
 * The test generator now uses ERB templates which ensures nice indentation of generated output.
 
@@ -249,10 +302,6 @@ h2. Details
 
 * A tool which converts Verilog headers into Ruby has been added.
 
-* @put_value()@ now returns the value it puts. Therefore, it is easier to chain together a series of assignments: @foo.intVal = bar.intVal = baz.intVal = 10@
-
-* @put_value()@ now verifies that the value it puts was written correctly. This helps to find bugs regarding invalid assumptions about the number of bits supported by a signal.
-
 * The source code is now indented with two spaces instead of one tab character.
 
 
@@ -262,7 +311,7 @@ h2. Summary
 
 This release simplifies generated tests and fixes a bug.
 
-h2. Details
+h2. Detail
 
 * The test generator now produces simpler Ruby benches and specifications.
 ** A template used by generated specifications has been added.
@@ -277,12 +326,7 @@ h2. Summary
 
 This release adds support and documentation for rapid prototyping of Verilog designs in Ruby.
 
-h2. Details
-
-* Support for prototyping designs in Ruby, before they are implemented in Verilog, has been added.
-** The _same_ specification can be used to verify both prototype _and_ design! :-)
-** The tutorial in the user manual has been updated to discuss prototyping.
-*** Prototypes have been added to the counter example.
+h2. Notice
 
 * The directory structure has been reorganized as follows:
 ** @ext@ → @src@
@@ -291,6 +335,13 @@ h2. Details
 
 * All template files have been moved into the @tpl@ directory.
 
+h2. Detail
+
+* Support for prototyping designs in Ruby, before they are implemented in Verilog, has been added.
+** The _same_ specification can be used to verify both prototype _and_ design! :-)
+** The tutorial in the user manual has been updated to discuss prototyping.
+*** Prototypes have been added to the counter example.
+
 * The user manual has been revised for consistency.
 
 
@@ -300,11 +351,11 @@ h2. Summary
 
 This release fixes unreadable syntax coloring in the user manual.
 
-h2. Acknowledgments
+h2. Acknowledgment
 
 * Thanks to Todd Nagengast and Matt Fischler for notifying me about unreadable text in the user manual.
 
-h2. Details
+h2. Detail
 
 * Source code comments in the user manual are now readable.
 
@@ -317,11 +368,11 @@ h2. Summary
 
 This release adds a tutorial to the user manual, and improves the tools and examples.
 
-h2. Acknowledgments
+h2. Acknowledgment
 
 * Thanks to Phil Tomson for correcting the URL of the RHDL website, in the user manual.
 
-h2. Details
+h2. Detail
 
 h3. User manual
 
@@ -352,20 +403,22 @@ h2. Summary
 
 This release enhances the VPI utility layer and adds new content to the user manual.
 
-h2. Acknowledgments
+h2. Acknowledgment
 
 * Thanks to Jan Decaluwe for correcting the description of MyHDL in the user manual.
 
-h2. Details
+h2. Notice
 
 * SWIG is no longer required for users because its output is included in the release package.
 
+* The @handle.value@ and @handle.value=@ methods have been removed.
+
+h2. Detail
+
 * The VPI utility layer provides access to VPI properties of handles in a "simpler, more powerful way":http://ruby-vpi.rubyforge.org/doc/background.organization.html#organization.vpi.
 
 ** All VPI properties, except delay values, are now accessible from a handle.
 
-** The @handle.value@ and @handle.value=@ methods have been removed.
-
 * The user manual has been revised and new content in the organization and usage sections has been added.
 
 * This release was tested and developed using:
@@ -379,18 +432,20 @@ h2. Summary
 
 This release adds a comprehensive user manual, upgrades from make to "Rake":http://rake.rubyforge.org, and improves the test generation tool.
 
-h2. Acknowledgments
+h2. Acknowledgment
 
 * Thanks to Jose Renau for solving the problem of strange delays that occurred whenever a design was reset.
 
-h2. Details
-
-* A comprehensive user manual, written in DocBook-XML, has been added.
+h2. Notice
 
 * Rake has replaced the role of *make*. All makefiles have been converted accordingly.
 
 * The test generation tool now generates multiple files (runner, bench, design, spec) and makes backups of existing files. See its help information for details.
 
+h2. Detail
+
+* A comprehensive user manual, written in DocBook-XML, has been added.
+
 * Support for RSpec 0.5.4 has been added.
 ** The counter example now makes use of RSpec.
 
@@ -405,11 +460,11 @@ h2. Summary
 
 This release adds a tool which generates test benches, and adds support for "Behavior Driven Development":http://behaviour-driven.org via the "RSpec":http://rspec.rubyforge.org library.
 
-h2. Acknowledgments
+h2. Acknowledgment
 
 * Thanks to Scott L Holmes for helping me "use the RSpec library without its runner":http://article.gmane.org/gmane.comp.lang.ruby.general/150087 program.
 
-h2. Details
+h2. Detail
 
 * A tool, which generates most of a Ruby-VPI test bench from a Verilog 2001 module declaration, has been added.
 
@@ -428,7 +483,11 @@ h2. Summary
 
 This release adds simple ways of reading and writing values to VPI handles, adds documentation for the VPI utility layer, and fixes the pipelined ALU example.
 
-h2. Details
+h2. Notice
+
+* The *msim* Makefile target for Mentor Modelsim has been renamed back to *vsim*.
+
+h2. Detail
 
 * Simple, consistent ways of reading and writing values to handles have been added to the VPI utility layer. These ways are described in the @SWIG::TYPE_p_unsigned_int@ class' documentation.
 
@@ -451,11 +510,15 @@ h2. Summary
 
 This release adds support for the _entire_ "IEEE Std. 1364-2005":http://ieeexplore.ieee.org/xpl/standardstoc.jsp?isnumber=33945 VPI interface, and updates the examples into unit tests.
 
-h2. Acknowledgments
+h2. Acknowledgment
 
 * Thanks to the "SWIG developers":http://www.swig.org/guilty.html for making this project _much_ easier! ;-)
 
-h2. Details
+h2. Notice
+
+* The *vsim* Makefile target for Mentor Modelsim has been renamed to *msim*.
+
+h2. Detail
 
 * The Ruby interface to VPI is now generated by "SWIG":http://www.swig.org.
 ** The main @VPI@ module has been renamed to @Vpi@.
@@ -469,7 +532,6 @@ h2. Details
 * The examples now make use of the *test/unit* unit testing framework.
 
 * The makefiles for the examples have been simplified through the use of a common template.
-** The *vsim* target for Mentor Modelsim has been renamed to *msim*.
 
 * This release was tested and developed using:
 ** Ruby 1.8.4 and Icarus Verilog 0.8 on i686 GNU/Linux
@@ -482,19 +544,21 @@ h2. Summary
 
 This release fixes major bugs, adds support for Mentor Modelsim, and removes the @$ruby_task@ callback.
 
-h2. Acknowledgments
+h2. Acknowledgment
 
 * Thanks to Nobu Nakada for explaining the "cross-thread violation on rb_gc()":http://article.gmane.org/gmane.comp.lang.ruby.general/146653 error.
 
-h2. Details
+h2. Notice
+
+* Removed @$ruby_task@ callback and ability to dynamically register system tasks from Ruby because inter-process communication is complicated at present.
+
+h2. Detail
 
 * The *cross-thread violation on rb_gc()* error has been fixed.
 ** The *stack level too deep (SystemStackError)* error has been fixed.
 ** The *test/unit* library can be used in Ruby test bench.
 ** Mentor Modelsim Verilog simulator works with Ruby-VPI.
 
-* Removed @$ruby_task@ callback and ability to dynamically register system tasks from Ruby because inter-process communication is complicated at present.
-
 * Added piplelined ALU example.
 
 * This release was tested and developed using:
@@ -512,13 +576,13 @@ This release adds enough Verilog VPI functionality to make Ruby-VPI usable for s
 * read and change VPI handle values
 * stop, finish, restart the simulation
 
-h2. Acknowledgments
+h2. Acknowledgment
 
 * Thanks to Jose Renau for helping me debug how Synopsys VCS works with Verilog VPI. The problem was that VCS required calltf signatures to be @void (*)(void)@, whereas the Verilog standard defines a calltf signature as @PLI_INT32 (*)(PLI_BYTE8*)@.
 
 * Thanks to Ross Bamford, Eric Hodel, and Yukihiro Matsumoto for "helping me discover":http://blade.nagaokaut.ac.jp/cgi-bin/scat.rb/ruby/ruby-talk/180662 why the @SystemStackError@ was happening.
 
-h2. Details
+h2. Detail
 
 * Implemented some Verilog VPI functionality:
 ** @VPI::handle_by_name(string, VPI::Handle)@ → @VPI::Handle@
@@ -551,7 +615,7 @@ h2. Summary
 
 This is Kazuhiro HIWADA's initial testing release of Ruby-VPI. See its "original announcement":http://www.ruby-talk.org/cgi-bin/scat.rb/ruby/ruby-list/18193 and "source code":http://easter.kuee.kyoto-u.ac.jp/~hiwada/ruby/memo/src/ruby-vpi-test.tgz.
 
-h2. Details
+h2. Detail
 
 * Added ability to relay control from Verilog test bench to Ruby (using @$ruby_callback@) and vice versa (using @PLI::relay_Verilog@).
 

data/MEMO

@@ -5,6 +5,8 @@ h1. Notes
 
 h1. Pending tasks
 
+* interactive console IRB wrapper for spec (just like Breakpoints in Rails)
+
 * add support for reading & writing vpi_delay values
 
 * define handled methods in Vpi::method_missing for faster response
@@ -13,6 +15,10 @@ h1. Pending tasks
 * GHDL simulator supports VPI
 ** need way to invoke VPI tasks from VHDL, like @$ruby_init();@
 
+* need to dump signal values when expectation fails in rSpec
+** maybe a waveform dump will also help
+** this will help in debugging the problem
+
 
 h1. Finished tasks
 
@@ -33,6 +39,8 @@ h1. Finished tasks
 
 * integrate RCov for code-coverage statistics
 
+* method_missing for Design class
+
 
 h1. Obsolete tasks
 

data/README

@@ -6,7 +6,7 @@ h2. Features
 
 * Prototype and verify designs _quickly_ using "BDD(behavior-driven development)":http://behaviour-driven.org/, "TDD(test-driven development)":http://www.agiledata.org/essays/tdd.html, and more.
 * Reuse the _same_ specification to verify both prototype and design.
-* Specifications are executable _and_ human-readable. (See this <a href="./doc/usage.tutorial.html#fig..counter_rspecTest_spec.rb">example specification</a> and its <a href="./doc/usage.tutorial.html#fig..test-proto.rspec">boss-friendly output</a>.)
+* Specifications are executable _and_ human-readable. (See this <a href="./doc/usage.tutorial.html#fig..counter_rspec_spec.rb">example specification</a> and its <a href="./doc/usage.tutorial.html#fig..test-proto.rspec">boss-friendly output</a>.)
 
 * Utilize Ruby's power and elegance. ("Why choose Ruby?":http://www.ruby-doc.org/whyruby)
 ** Built-in support for unlimited length integers, regular expressions, networking, multi-threading, system calls, _ad infinium_!

data/Rakefile

@@ -116,8 +116,8 @@ end
 
 ## documentation
 
-desc 'Generate documentation.'
-task 'doc' => 'ref' do |t|
+desc 'Generate user documentation.'
+task 'doc' do |t|
   cd t.name do
     sh 'rake'
   end

data/bin/generate_test.rb

@@ -4,14 +4,13 @@
 # * The first input signal in a module's declaration is assumed to be the clocking signal.
 #
 # = Progress indicators
-# As this tool performs its duties, it notifies you of important information using the following indicators.
-#
-# create:: Output file does not exist. It will be created.
-# skip:: Output file exists and is up to date.
-# update:: Output file exists and is out of date. A backup copy will be made (with a ".old" suffix) before this output file is updated. Use a text merging tool or manually transfer any necessary information from the backup copy to the updated output file.
+# create:: File will be created because it does not exist.
+# skip:: File will be skipped because it is already up to date.
+# update:: File will be updated because it is out of date. A backup copy will be made before the file is updated. Use a text merging tool (see MERGER) or manually transfer any necessary information from the backup copy to the updated file.
+# backup:: A backup copy of a file is being made.
 #
 # = Environment variables
-# MERGER:: A command for invoking a text merging tool with two arguments: old file, new file. The tool should save its output to the new file.
+# MERGER:: A command that invokes a text merging tool with two arguments: old file, new file. The tool's output should be written to the new file.
 
 
 =begin
@@ -53,11 +52,12 @@ def write_file aPath, aContent
     if oldDigest == newDigest
       notify :skip, aPath
     else
-      notify :update, aPath
-
       old, new = "#{aPath}.old", aPath
 
+      notify :backup, old
       FileUtils.cp aPath, old, :preserve => true
+
+      notify :update, aPath
       File.open(new, 'w') {|f| f << aContent}
 
       if m = ENV['MERGER']
@@ -92,7 +92,7 @@ class OutputInfo
 
   SPEC_FORMATS = [:rSpec, :xUnit, :generic]
 
-  attr_reader :verilogBenchName, :verilogBenchPath, :rubyBenchName, :rubyBenchPath, :designName, :designClassName, :designPath, :specName, :specClassName, :specFormat, :specPath, :rubyVpiPath, :runnerName, :runnerPath, :protoName, :protoPath, :protoClassName
+  attr_reader :verilogBenchName, :verilogBenchPath, :rubyBenchName, :rubyBenchPath, :designName, :designClassName, :designPath, :specName, :specClassName, :specFormat, :specPath, :rubyVpiPath, :runnerName, :runnerPath, :protoName, :protoPath
 
   attr_reader :testName, :suffix, :benchSuffix, :designSuffix, :specSuffix, :runnerSuffix, :protoSuffix
 
@@ -126,7 +126,6 @@ class OutputInfo
     @specPath = @specName + RUBY_EXT
 
     @designClassName = aModuleName.to_ruby_const_name
-    @protoClassName = @designClassName + 'Prototype'
     @specClassName = @specName.to_ruby_const_name
 
     @runnerName = aModuleName + @runnerSuffix
@@ -163,11 +162,11 @@ if File.basename($0) == File.basename(__FILE__)
       exit
     end
 
-    opts.on '-u', '--xunit', 'use xUnit specification format' do |val|
+    opts.on '--xunit', 'use xUnit specification format' do |val|
       optSpecFmt = :xUnit if val
     end
 
-    opts.on '-s', '--rspec', 'use rSpec specification format' do |val|
+    opts.on '--rspec', 'use rSpec specification format' do |val|
       optSpecFmt = :rSpec if val
     end
 

data/bin/generate_test_tpl/bench.rb

@@ -1,4 +1,4 @@
-## This is the Ruby side of the bench.
+# This file is the Ruby side of the bench.
 
 require 'ruby-vpi'
 <%
@@ -14,7 +14,7 @@ require 'ruby-vpi/rspec'
   end
 %>
 
-RubyVpi.init_bench '<%= aModuleInfo.name + aOutputInfo.suffix %>', :<%= aOutputInfo.protoClassName %>
+RubyVpi.init_bench '<%= aModuleInfo.name + aOutputInfo.suffix %>', :<%= aOutputInfo.designClassName %>
 
 # service the $ruby_relay callback
 <%

data/bin/generate_test_tpl/bench.v

@@ -8,10 +8,7 @@
 
   clockSignal = aModuleInfo.ports.first.name
 %>
-/* This is the Verilog side of the bench. */
-
-`include "<%= aModuleInfo.name %>.v"
-
+/* This file is the Verilog side of the bench. */
 module <%= aOutputInfo.verilogBenchName %>;
 
   // instantiate the design under test

data/bin/generate_test_tpl/design.rb

@@ -1,26 +1,12 @@
-# An interface to the design under test.
-class <%= aOutputInfo.designClassName %>
-  include Vpi
-
-<% (aParseInfo.constants + aModuleInfo.parameters).each do |var| %>
-  <%= var.name.to_ruby_const_name %> = <%= var.value.verilog_to_ruby %>
+# This is a Ruby interface to the design under test.
+<% aParseInfo.constants.each do |var| %>
+<%= var.name.to_ruby_const_name %> = <%= var.value.verilog_to_ruby %>
 <% end %>
 
-  attr_reader <%=
-    aModuleInfo.ports.map do |port|
-      ":#{port.name}"
-    end.join(', ')
-  %>
-
-  def initialize
-<% aModuleInfo.ports.each do |port| %>
-    @<%= port.name %> = vpi_handle_by_name("<%= aOutputInfo.verilogBenchName %>.<%= port.name %>", nil)
-<% end %>
-  end
-
+class << <%= aOutputInfo.designClassName %>
   def reset!
-<% aModuleInfo.ports.select { |p| p.input? }[1..-1].each do |port| %>
-    @<%= port.name %>.hexStrVal = 'x'
+<% aModuleInfo.ports.select { |p| p.input? }[1..-1].each do |port| # using [1..] because the first signal is the clock %>
+    <%= port.name %>.hexStrVal = 'x'
 <% end %>
   end
 end

data/bin/generate_test_tpl/proto.rb

@@ -1,9 +1,11 @@
-# A prototype of the design under test.
-class <%= aOutputInfo.protoClassName %> < <%= aOutputInfo.designClassName %>
+# This is a prototype of the design under test.
+class << <%= aOutputInfo.designClassName %>
+  # When prototyping is enabled, this method is invoked
+  # instead of Vpi::relay_verilog to simulate the design.
   def simulate!
     # discard old outputs
 <% aModuleInfo.ports.reject { |p| p.input? }.each do |port| %>
-      @<%= port.name %>.hexStrVal = 'x'
+      <%= port.name %>.hexStrVal = 'x'
 <% end %>
 
     # process new inputs

data/bin/generate_test_tpl/runner.rake

@@ -1,7 +1,8 @@
-## This file builds and runs the test.
+# This file runs the test.
 
 # These are source files that are to be compiled.
 SIMULATOR_SOURCES = [
+  '<%= aModuleInfo.name %>.v',
   '<%= aOutputInfo.verilogBenchPath %>',
 ]
 

data/bin/generate_test_tpl/spec.rb

@@ -1,14 +1,12 @@
-## This specification verifies the design under test.
+# This file is a behavioral specification for the design under test.
 
 <%
   case aOutputInfo.specFormat
     when :xUnit
 %>
 class <%= aOutputInfo.specClassName %> < Test::Unit::TestCase
-  include Vpi
-
   def setup
-    @design = <%= aOutputInfo.designClassName %>.new
+    <%= aOutputInfo.designClassName %>.reset!
   end
 <% aModuleInfo.ports.each do |port| %>
 
@@ -19,26 +17,21 @@ end
 <%
    when :rSpec
 %>
-include Vpi
-
 context "A new <%= aOutputInfo.designClassName %>" do
   setup do
-    @design = <%= aOutputInfo.designClassName %>.new
-    @design.reset!
+    <%= aOutputInfo.designClassName %>.reset!
   end
 
   specify "should ..." do
-    # @design.should ...
+    # <%= aOutputInfo.designClassName %>.should ...
   end
 end
 <%
   else
 %>
 class <%= aOutputInfo.specClassName %>
-  include Vpi
-
   def initialize
-    @design = <%= aOutputInfo.designClassName %>.new
+    <%= aOutputInfo.designClassName %>.reset!
   end
 end
 <%