ruby-vpi 9.0.0 → 10.0.0

data/memo.html

@@ -104,6 +104,11 @@ Ask for help, give feedback, or discuss.</p>
 	<h1>Pending tasks</h1>
 
 
+	<ul>
+	<li>interactive console <span class="caps">IRB</span> wrapper for spec (just like Breakpoints in Rails)</li>
+	</ul>
+
+
 	<ul>
 	<li>add support for reading &#38; writing vpi_delay values</li>
 	</ul>
@@ -125,6 +130,15 @@ Ask for help, give feedback, or discuss.</p>
 	</ul>
 
 
+	<ul>
+	<li>need to dump signal values when expectation fails in rSpec
+	<ul>
+	<li>maybe a waveform dump will also help</li>
+		<li>this will help in debugging the problem</li>
+	</ul></li>
+	</ul>
+
+
 	<h1>Finished tasks</h1>
 
 
@@ -170,6 +184,11 @@ Ask for help, give feedback, or discuss.</p>
 	</ul>
 
 
+	<ul>
+	<li>method_missing for Design class</li>
+	</ul>
+
+
 	<h1>Obsolete tasks</h1>
 
 

data/memo.part.html

@@ -9,6 +9,11 @@
 	<h1>Pending tasks</h1>
 
 
+	<ul>
+	<li>interactive console <span class="caps">IRB</span> wrapper for spec (just like Breakpoints in Rails)</li>
+	</ul>
+
+
 	<ul>
 	<li>add support for reading &#38; writing vpi_delay values</li>
 	</ul>
@@ -30,6 +35,15 @@
 	</ul>
 
 
+	<ul>
+	<li>need to dump signal values when expectation fails in rSpec
+	<ul>
+	<li>maybe a waveform dump will also help</li>
+		<li>this will help in debugging the problem</li>
+	</ul></li>
+	</ul>
+
+
 	<h1>Finished tasks</h1>
 
 
@@ -75,6 +89,11 @@
 	</ul>
 
 
+	<ul>
+	<li>method_missing for Design class</li>
+	</ul>
+
+
 	<h1>Obsolete tasks</h1>
 
 

data/readme.html

@@ -105,7 +105,7 @@ Ask for help, give feedback, or discuss.</p>
 	<ul>
 	<li>Prototype and verify designs <em>quickly</em> using <a href="http://behaviour-driven.org/" title="behavior-driven development"><span class="caps">BDD</span></a>, <a href="http://www.agiledata.org/essays/tdd.html" title="test-driven development"><span class="caps">TDD</span></a>, and more.</li>
 		<li>Reuse the <em>same</em> specification to verify both prototype and design.</li>
-		<li>Specifications are executable <em>and</em> human-readable. (See this <a href="./doc/usage.tutorial.html#fig..counter_rspecTest_spec.rb">example specification</a> and its <a href="./doc/usage.tutorial.html#fig..test-proto.rspec">boss-friendly output</a>.)</li>
+		<li>Specifications are executable <em>and</em> human-readable. (See this <a href="./doc/usage.tutorial.html#fig..counter_rspec_spec.rb">example specification</a> and its <a href="./doc/usage.tutorial.html#fig..test-proto.rspec">boss-friendly output</a>.)</li>
 	</ul>
 
 

data/readme.part.html

@@ -10,7 +10,7 @@
 	<ul>
 	<li>Prototype and verify designs <em>quickly</em> using <a href="http://behaviour-driven.org/" title="behavior-driven development"><span class="caps">BDD</span></a>, <a href="http://www.agiledata.org/essays/tdd.html" title="test-driven development"><span class="caps">TDD</span></a>, and more.</li>
 		<li>Reuse the <em>same</em> specification to verify both prototype and design.</li>
-		<li>Specifications are executable <em>and</em> human-readable. (See this <a href="./doc/usage.tutorial.html#fig..counter_rspecTest_spec.rb">example specification</a> and its <a href="./doc/usage.tutorial.html#fig..test-proto.rspec">boss-friendly output</a>.)</li>
+		<li>Specifications are executable <em>and</em> human-readable. (See this <a href="./doc/usage.tutorial.html#fig..counter_rspec_spec.rb">example specification</a> and its <a href="./doc/usage.tutorial.html#fig..test-proto.rspec">boss-friendly output</a>.)</li>
 	</ul>
 
 

data/samp/counter/counter_rspec_bench.rb

@@ -1,9 +1,9 @@
-## This is the Ruby side of the bench.
+# This file is the Ruby side of the bench.
 
 require 'ruby-vpi'
 require 'ruby-vpi/rspec'
 
-RubyVpi.init_bench 'counter_rspec', :CounterPrototype
+RubyVpi.init_bench 'counter_rspec', :Counter
 
 # service the $ruby_relay callback
   # The rSpec library will take control henceforth.

data/samp/counter/counter_rspec_bench.v

@@ -1,7 +1,4 @@
-/* This is the Verilog side of the bench. */
-
-`include "counter.v"
-
+/* This file is the Verilog side of the bench. */
 module counter_rspec_bench;
 
   // instantiate the design under test

data/samp/counter/counter_rspec_design.rb

@@ -1,22 +1,8 @@
-# An interface to the design under test.
-class Counter
-  include Vpi
-
-  Size = 5
-
-  attr_reader :clock, :reset, :count
-
-  def initialize
-    @clock = vpi_handle_by_name("counter_rspec_bench.clock", nil)
-    @reset = vpi_handle_by_name("counter_rspec_bench.reset", nil)
-    @count = vpi_handle_by_name("counter_rspec_bench.count", nil)
-  end
-
+# This is a Ruby interface to the design under test.
+class << Counter
   def reset!
-    @reset.hexStrVal = 'x'
-
-    @reset.intVal = 1
+    reset.intVal = 1
     relay_verilog
-    @reset.intVal = 0
+    reset.intVal = 0
   end
 end

data/samp/counter/counter_rspec_proto.rb

@@ -1,10 +1,12 @@
-# A prototype of the design under test.
-class CounterPrototype < Counter
+# This is a prototype of the design under test.
+class << Counter
+  # When prototyping is enabled, this method is invoked
+  # instead of Vpi::relay_verilog to simulate the design.
   def simulate!
-    if @reset.intVal == 1
-      @count.intVal = 0
+    if reset.intVal == 1
+      count.intVal = 0
     else
-      @count.intVal += 1
+      count.intVal += 1
     end
   end
 end

data/samp/counter/counter_rspec_runner.rake

@@ -1,7 +1,8 @@
-## This file builds and runs the test.
+# This file runs the test.
 
 # These are source files that are to be compiled.
 SIMULATOR_SOURCES = [
+  'counter.v',
   'counter_rspec_bench.v',
 ]
 

data/samp/counter/counter_rspec_spec.rb

@@ -1,26 +1,23 @@
-## This specification verifies the design under test.
+# This file is a behavioral specification for the design under test.
 
 # lowest upper bound of counter's value
-LIMIT = 2 ** Counter::Size
+LIMIT = 2 ** Counter.Size.intVal
 
 # maximum allowed value for a counter
 MAX = LIMIT - 1
 
-include Vpi
-
 context "A resetted counter's value" do
   setup do
-    @design = Counter.new
-    @design.reset!
+    Counter.reset!
   end
 
   specify "should be zero" do
-    @design.count.intVal.should_equal 0
+    Counter.count.intVal.should_equal 0
   end
 
   specify "should increment by one count upon each rising clock edge" do
     LIMIT.times do |i|
-      @design.count.intVal.should_equal i
+      Counter.count.intVal.should_equal i
 
       # advance the clock
         relay_verilog
@@ -30,18 +27,17 @@ end
 
 context "A counter with the maximum value" do
   setup do
-    @design = Counter.new
-    @design.reset!
+    Counter.reset!
 
     # increment the counter to maximum value
       MAX.times do relay_verilog end
-      @design.count.intVal.should_equal MAX
+      Counter.count.intVal.should_equal MAX
   end
 
   specify "should overflow upon increment" do
     # increment the counter
       relay_verilog
 
-    @design.count.intVal.should_equal 0
+    Counter.count.intVal.should_equal 0
   end
 end

data/samp/counter/counter_xunit_bench.rb

@@ -1,9 +1,9 @@
-## This is the Ruby side of the bench.
+# This file is the Ruby side of the bench.
 
 require 'ruby-vpi'
 require 'test/unit'
 
-RubyVpi.init_bench 'counter_xunit', :CounterPrototype
+RubyVpi.init_bench 'counter_xunit', :Counter
 
 # service the $ruby_relay callback
   # The xUnit library will take control henceforth.

data/samp/counter/counter_xunit_bench.v

@@ -1,7 +1,4 @@
-/* This is the Verilog side of the bench. */
-
-`include "counter.v"
-
+/* This file is the Verilog side of the bench. */
 module counter_xunit_bench;
 
   // instantiate the design under test

data/samp/counter/counter_xunit_design.rb

@@ -1,22 +1,8 @@
-# An interface to the design under test.
-class Counter
-  include Vpi
-
-  Size = 5
-
-  attr_reader :clock, :reset, :count
-
-  def initialize
-    @clock = vpi_handle_by_name("counter_xunit_bench.clock", nil)
-    @reset = vpi_handle_by_name("counter_xunit_bench.reset", nil)
-    @count = vpi_handle_by_name("counter_xunit_bench.count", nil)
-  end
-
+# This is a Ruby interface to the design under test.
+class << Counter
   def reset!
-    @reset.hexStrVal = 'x'
-
-    @reset.intVal = 1
+    reset.intVal = 1
     relay_verilog
-    @reset.intVal = 0
+    reset.intVal = 0
   end
 end

data/samp/counter/counter_xunit_proto.rb

@@ -1,10 +1,12 @@
-# A prototype of the design under test.
-class CounterPrototype < Counter
+# This is a prototype of the design under test.
+class << Counter
+  # When prototyping is enabled, this method is invoked
+  # instead of Vpi::relay_verilog to simulate the design.
   def simulate!
-    if @reset.intVal == 1
-      @count.intVal = 0
+    if reset.intVal == 1
+      count.intVal = 0
     else
-      @count.intVal += 1
+      count.intVal += 1
     end
   end
 end

data/samp/counter/counter_xunit_runner.rake

@@ -1,7 +1,8 @@
-## This file builds and runs the test.
+# This file runs the test.
 
 # These are source files that are to be compiled.
 SIMULATOR_SOURCES = [
+  'counter.v',
   'counter_xunit_bench.v',
 ]
 

data/samp/counter/counter_xunit_spec.rb

@@ -1,26 +1,23 @@
-## This specification verifies the design under test.
+# This file is a behavioral specification for the design under test.
 
 # lowest upper bound of counter's value
-LIMIT = 2 ** Counter::Size
+LIMIT = 2 ** Counter.Size.intVal
 
 # maximum allowed value for a counter
 MAX = LIMIT - 1
 
 class ResettedCounterValue < Test::Unit::TestCase
-  include Vpi
-
   def setup
-    @design = Counter.new
-    @design.reset!
+    Counter.reset!
   end
 
   def test_zero
-    assert_equal 0, @design.count.intVal
+    assert_equal 0, Counter.count.intVal
   end
 
   def test_increment
     LIMIT.times do |i|
-      assert_equal i, @design.count.intVal
+      assert_equal i, Counter.count.intVal
 
       # advance the clock
         relay_verilog
@@ -29,21 +26,18 @@ class ResettedCounterValue < Test::Unit::TestCase
 end
 
 class MaximumCounterValue < Test::Unit::TestCase
-  include Vpi
-
   def setup
-    @design = Counter.new
-    @design.reset!
+    Counter.reset!
 
     # increment the counter to maximum value
       MAX.times do relay_verilog end
-      assert_equal MAX, @design.count.intVal
+      assert_equal MAX, Counter.count.intVal
   end
 
   def test_overflow
     # increment the counter
       relay_verilog
 
-    assert_equal 0, @design.count.intVal
+    assert_equal 0, Counter.count.intVal
   end
 end

data/samp/pipelined_alu/hw5_unit_test_bench.rb

@@ -1,9 +1,9 @@
-## This is the Ruby side of the bench.
+# This file is the Ruby side of the bench.
 
 require 'ruby-vpi'
 require 'test/unit'
 
-RubyVpi.init_bench 'hw5_unit_test', :Hw5_unitPrototype
+RubyVpi.init_bench 'hw5_unit_test', :Hw5_unit
 
 # service the $ruby_relay callback
-  # The UnitTest library will take control henceforth.
+  # The xUnit library will take control henceforth.

data/samp/pipelined_alu/hw5_unit_test_bench.v

@@ -1,7 +1,4 @@
-/* This is the Verilog side of the bench. */
-
-`include "hw5_unit.v"
-
+/* This file is the Verilog side of the bench. */
 module hw5_unit_test_bench;
 
   // instantiate the design under test

data/samp/pipelined_alu/hw5_unit_test_design.rb

@@ -1,88 +1,72 @@
-# An interface to the design under test.
-class Hw5_unit
-  include Vpi
-
-  WIDTH = 32
-  DATABITS = 7
-  OP_NOP = 0
-  OP_ADD = 1
-  OP_SUB = 2
-  OP_MULT = 3
-
-  # Supported types of ALU operations.
-  OPERATIONS = constants.grep(/^OP_/).map {|s| const_get s}
-
-  # Number of cycles needed to reset this design.
-  RESET_DELAY = 5
-
-  attr_reader :clk, :reset, :in_databits, :a, :b, :in_op, :res, :out_databits, :out_op
-
-  def initialize
-    @clk = vpi_handle_by_name("hw5_unit_test_bench.clk", nil)
-    @reset = vpi_handle_by_name("hw5_unit_test_bench.reset", nil)
-    @in_databits = vpi_handle_by_name("hw5_unit_test_bench.in_databits", nil)
-    @a = vpi_handle_by_name("hw5_unit_test_bench.a", nil)
-    @b = vpi_handle_by_name("hw5_unit_test_bench.b", nil)
-    @in_op = vpi_handle_by_name("hw5_unit_test_bench.in_op", nil)
-    @res = vpi_handle_by_name("hw5_unit_test_bench.res", nil)
-    @out_databits = vpi_handle_by_name("hw5_unit_test_bench.out_databits", nil)
-    @out_op = vpi_handle_by_name("hw5_unit_test_bench.out_op", nil)
-  end
+# This is a Ruby interface to the design under test.
+
+WIDTH = 32
+DATABITS = 7
+OP_NOP = 0
+OP_ADD = 1
+OP_SUB = 2
+OP_MULT = 3
+OPERATIONS = (OP_NOP..OP_MULT).to_a
+
+# Number of cycles needed to reset this design.
+RESET_DELAY = 5
 
+class << Hw5_unit
   def reset!
-    @reset.hexStrVal = 'x'
-    @in_databits.hexStrVal = 'x'
-    @a.hexStrVal = 'x'
-    @b.hexStrVal = 'x'
-    @in_op.hexStrVal = 'x'
+    reset.hexStrVal = 'x'
+    in_databits.hexStrVal = 'x'
+    a.hexStrVal = 'x'
+    b.hexStrVal = 'x'
+    in_op.hexStrVal = 'x'
 
 
-    @reset.intVal = 1
+    reset.intVal = 1
 
     RESET_DELAY.times do
       relay_verilog
     end
 
-    @reset.intVal = 0
+    reset.intVal = 0
   end
+end
 
-  # Represents an ALU operation.
-  class Operation
-    attr_accessor :type, :tag, :arg1, :arg2, :stage, :result
 
-    def initialize(type, tag, arg1 = 0, arg2 = 0)
-      raise ArgumentError unless OPERATIONS.include? type
+# Represents an ALU operation.
+class Operation
+  attr_accessor :type, :tag, :arg1, :arg2, :stage, :result
 
-      @type = type
-      @tag = tag
-      @arg1 = arg1
-      @arg2 = arg2
+  def initialize(type, tag, arg1 = 0, arg2 = 0)
+    raise ArgumentError unless OPERATIONS.include? type
 
-      @stage = 0
-    end
+    @type = type
+    @tag = tag
+    @arg1 = arg1
+    @arg2 = arg2
 
-    # Computes the result of this operation.
-    def compute
-      case @type
-        when OP_ADD
-          @arg1 + @arg2
+    @stage = 0
+  end
 
-        when OP_SUB
-          @arg1 - @arg2
+  # Computes the result of this operation.
+  def compute
+    case @type
+      when OP_ADD
+        @arg1 + @arg2
 
-        when OP_MULT
-          @arg1 * @arg2
+      when OP_SUB
+        @arg1 - @arg2
 
-        when OP_NOP
-          nil
+      when OP_MULT
+        @arg1 * @arg2
 
-        else
-          raise
-      end
-    end
+      when OP_NOP
+        nil
 
-    def compute!
-      @result = compute
+      else
+        raise
     end
   end
+
+  def compute!
+    @result = compute
+  end
 end

data/samp/pipelined_alu/hw5_unit_test_proto.rb

@@ -1,10 +1,14 @@
-# A prototype of the design under test.
-class Hw5_unitPrototype < Hw5_unit
+# This is a prototype of the design under test.
+class << Hw5_unit
+  # When prototyping is enabled, this method is invoked
+  # instead of Vpi::relay_verilog to simulate the design.
   def simulate!
+    raise NotImplementedError, "Prototype is not yet implemented."
+
     # discard old outputs
-      @res.hexStrVal = 'x'
-      @out_databits.hexStrVal = 'x'
-      @out_op.hexStrVal = 'x'
+      res.hexStrVal = 'x'
+      out_databits.hexStrVal = 'x'
+      out_op.hexStrVal = 'x'
 
     # process new inputs
 

data/samp/pipelined_alu/hw5_unit_test_runner.rake

@@ -1,7 +1,8 @@
-## This file builds and runs the test.
+# This file runs the test.
 
 # These are source files that are to be compiled.
 SIMULATOR_SOURCES = [
+  'hw5_unit.v',
   'hw5_unit_test_bench.v',
 ]
 

data/samp/pipelined_alu/hw5_unit_test_spec.rb

@@ -1,4 +1,3 @@
-## This specification verifies the design under test.
 =begin
   Copyright 2006 Suraj N. Kurapati
 
@@ -19,25 +18,23 @@
   Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 =end
 
+# This file is a behavioral specification for the design under test.
+
 require 'InputGenerator'
 
 class Hw5_unit_test_spec < Test::Unit::TestCase
-  include Vpi
-
   # Number of input sequences to test.
   NUM_TESTS = 4000
 
   # Bitmask capable of capturing ALU result.
-  ALU_RESULT_MASK = (2 ** Hw5_unit::WIDTH) - 1
+  ALU_RESULT_MASK = (2 ** WIDTH) - 1
 
   # Upper limit of values allowed for an operation's tag.
-  OPERATION_TAG_LIMIT = 2 ** Hw5_unit::DATABITS
+  OPERATION_TAG_LIMIT = 2 ** DATABITS
 
   def setup
-    @design = Hw5_unit.new
-    @design.reset!
-
-    @inputGen = InputGenerator.new(Hw5_unit::WIDTH)
+    Hw5_unit.reset!
+    @inputGen = InputGenerator.new(WIDTH)
   end
 
   def test_pipeline
@@ -47,17 +44,17 @@ class Hw5_unit_test_spec < Test::Unit::TestCase
     until numVerified == NUM_TESTS
       # issue a new operation
         if numIssued < NUM_TESTS
-          op = Hw5_unit::Operation.new(
-            Hw5_unit::OPERATIONS[rand(Hw5_unit::OPERATIONS.size)],
+          op = Operation.new(
+            OPERATIONS[rand(OPERATIONS.size)],
             numIssued % OPERATION_TAG_LIMIT,
             @inputGen.gen,
             @inputGen.gen
           )
 
-          @design.a.intVal = op.arg1
-          @design.b.intVal = op.arg2
-          @design.in_op.intVal = op.type
-          @design.in_databits.intVal = op.tag
+          Hw5_unit.a.intVal = op.arg1
+          Hw5_unit.b.intVal = op.arg2
+          Hw5_unit.in_op.intVal = op.type
+          Hw5_unit.in_databits.intVal = op.tag
 
           issuedOps << op
           numIssued += 1
@@ -66,18 +63,18 @@ class Hw5_unit_test_spec < Test::Unit::TestCase
       relay_verilog
 
       # verify result of finished operation
-        unless @design.out_databits.x?
-          finishedOp = Hw5_unit::Operation.new(
-            @design.out_op.intVal,
-            @design.out_databits.intVal
+        unless Hw5_unit.out_databits.x?
+          finishedOp = Operation.new(
+            Hw5_unit.out_op.intVal,
+            Hw5_unit.out_databits.intVal
           )
-          finishedOp.result = @design.res.intVal & ALU_RESULT_MASK
+          finishedOp.result = Hw5_unit.res.intVal & ALU_RESULT_MASK
 
           expectedOp = issuedOps.shift
           assert_equal expectedOp.type, finishedOp.type, "incorrect operation"
           assert_equal expectedOp.tag, finishedOp.tag, "incorrect tag"
 
-          unless finishedOp.type == Hw5_unit::OP_NOP
+          unless finishedOp.type == OP_NOP
             assert_equal expectedOp.compute & ALU_RESULT_MASK, finishedOp.result, "incorrect result"
           end