ruby-vpi 7.2.0 → 7.3.0

data/ref/ruby/fr_method_index.html

@@ -20,75 +20,83 @@
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   <h1 class="section-bar">Methods</h1>
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+    <a href="classes/SWIG/TYPE_p_unsigned_int.html#M000072">each (SWIG::TYPE_p_unsigned_int)</a><br />
+    <a href="classes/SWIG/TYPE_p_unsigned_int.html#M000068">get_value (SWIG::TYPE_p_unsigned_int)</a><br />
+    <a href="classes/SWIG/TYPE_p_unsigned_int.html#M000067">get_value_wrapper (SWIG::TYPE_p_unsigned_int)</a><br />
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+    <a href="classes/XX/Markup/InstanceMethods.html#M000036">method_missing (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/ERB.html#M000018">new (ERB)</a><br />
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+    <a href="classes/XX/Document.html#M000056">new (XX::Document)</a><br />
+    <a href="classes/VerilogParser.html#M000003">new (VerilogParser)</a><br />
+    <a href="classes/OutputInfo.html#M000014">new (OutputInfo)</a><br />
+    <a href="classes/VerilogParser/Module/Port.html#M000005">new (VerilogParser::Module::Port)</a><br />
+    <a href="classes/VerilogParser/Module.html#M000004">new (VerilogParser::Module)</a><br />
+    <a href="classes/Template.html#M000015">new (Template)</a><br />
     <a href="files/lib/ruby-vpi/runner_rb.html#M000002">object_file_path (lib/ruby-vpi/runner.rb)</a><br />
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-    <a href="classes/XX/Document.html#M000055">to_str (XX::Document)</a><br />
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-    <a href="classes/Table.html#M000006">to_xml (Table)</a><br />
-    <a href="classes/XX/Document.html#M000051">top (XX::Document)</a><br />
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+    <a href="classes/VerilogParser/Module/Port.html#M000007">output? (VerilogParser::Module::Port)</a><br />
+    <a href="classes/XX/Document.html#M000059">pop (XX::Document)</a><br />
+    <a href="classes/XX/Document.html#M000062">pretty (XX::Document)</a><br />
+    <a href="classes/XX/Document.html#M000058">push (XX::Document)</a><br />
+    <a href="classes/SWIG/TYPE_p_unsigned_int.html#M000069">put_value (SWIG::TYPE_p_unsigned_int)</a><br />
+    <a href="classes/VerilogParser/Module/Port.html#M000008">reg? (VerilogParser::Module::Port)</a><br />
+    <a href="classes/FileUtils.html#M000073">sh (FileUtils)</a><br />
+    <a href="classes/Table.html#M000012">to_html4 (Table)</a><br />
+    <a href="classes/String.html#M000017">to_ruby_const_name (String)</a><br />
+    <a href="classes/XX/Document.html#M000061">to_str (XX::Document)</a><br />
+    <a href="classes/Table.html#M000011">to_xhtml (Table)</a><br />
+    <a href="classes/Table.html#M000013">to_xml (Table)</a><br />
+    <a href="classes/XX/Document.html#M000057">top (XX::Document)</a><br />
+    <a href="classes/XX/Document.html#M000060">tracking_additions (XX::Document)</a><br />
+    <a href="classes/RDoc.html#M000077">usage_from_file (RDoc)</a><br />
+    <a href="classes/String.html#M000016">verilog_to_ruby (String)</a><br />
+    <a href="classes/RubyVPI.html#M000076">with_coverage_analysis (RubyVPI)</a><br />
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-    <a href="classes/XX/Markup/InstanceMethods.html#M000033">xx_with_doc_in_effect (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/SWIG/TYPE_p_unsigned_int.html#M000065">x? (SWIG::TYPE_p_unsigned_int)</a><br />
+    <a href="classes/XX/XHTML.html#M000024">xhtml_ (XX::XHTML)</a><br />
+    <a href="classes/XX/XHTML/Transitional.html#M000025">xhtml_ (XX::XHTML::Transitional)</a><br />
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+    <a href="classes/XX/XML.html#M000019">xml_ (XX::XML)</a><br />
+    <a href="classes/XX/XMLish.html#M000023">xmlish_ (XX::XMLish)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000052">xx_ancestors (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/ClassMethods.html#M000032">xx_ancestors (XX::Markup::ClassMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000043">xx_any_ (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000044">xx_cdata_ (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000047">xx_class (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000053">xx_config (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/ClassMethods.html#M000033">xx_config (XX::Markup::ClassMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000054">xx_config_for (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/ClassMethods.html#M000034">xx_config_for (XX::Markup::ClassMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000055">xx_configure (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/ClassMethods.html#M000035">xx_configure (XX::Markup::ClassMethods)</a><br />
+    <a href="classes/XX/Markup/ClassMethods.html#M000030">xx_define_tag_method (XX::Markup::ClassMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000050">xx_define_tag_method (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/ClassMethods.html#M000029">xx_define_tmp_method (XX::Markup::ClassMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000049">xx_define_tmp_method (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000040">xx_doc (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000042">xx_markup_ (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000045">xx_parse_attributes (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000046">xx_parse_yaml_attributes (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/ClassMethods.html#M000031">xx_remove_tag_method (XX::Markup::ClassMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000051">xx_remove_tag_method (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000037">xx_tag_ (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/ClassMethods.html#M000028">xx_tag_method_name (XX::Markup::ClassMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000048">xx_tag_method_name (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000041">xx_text_ (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000038">xx_which (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/XX/Markup/InstanceMethods.html#M000039">xx_with_doc_in_effect (XX::Markup::InstanceMethods)</a><br />
+    <a href="classes/SWIG/TYPE_p_unsigned_int.html#M000066">z? (SWIG::TYPE_p_unsigned_int)</a><br />
   </div>
 </div>
 </body>

data/samp/counter/counter_rspecTest_bench.v

@@ -4,12 +4,11 @@ module counter_rspecTest_bench;
 
   // instantiate the design under test
     parameter Size = 5;
+    reg  clock;
+    reg  reset;
+    wire [Size - 1 : 0] count;
 
-    reg clock;
-    reg reset;
-    wire  [Size - 1 : 0] count;
-
-    counter#(.Size(Size))counter_rspecTest_bench_rspecTest_design(.clock(clock), .reset(reset), .count(count));
+    counter #(.Size(Size))counter_rspecTest_bench_design(.clock(clock), .reset(reset), .count(count));
 
   // connect to the Ruby side of this bench
     initial begin

data/samp/counter/counter_unitTest_bench.v

@@ -1,15 +1,16 @@
 /* This is the Verilog side of the bench. */
 
+
+
 module counter_unitTest_bench;
 
   // instantiate the design under test
     parameter Size = 5;
+    reg  clock;
+    reg  reset;
+    wire [Size - 1 : 0] count;
 
-    reg clock;
-    reg reset;
-    wire  [Size - 1 : 0] count;
-
-    counter#(.Size(Size))counter_unitTest_bench_unitTest_design(.clock(clock), .reset(reset), .count(count));
+    counter #(.Size(Size))counter_unitTest_bench_design(.clock(clock), .reset(reset), .count(count));
 
   // connect to the Ruby side of this bench
     initial begin

data/samp/pipelined_alu/Hw5UnitModel.rb

@@ -67,10 +67,10 @@ class Hw5UnitModel
 
   # Number of cycles each operation uses.
   OPERATION_LATENCIES = {
-    :add => 3, #1,
-    :sub => 3, #2,
-    :mul => 3, #3,
-    :nop => 3, #1,
+    :add => 1,
+    :sub => 2,
+    :mul => 3,
+    :nop => 1,
   }
 
   # The famous no-operation.

data/samp/pipelined_alu/hw5_unit.v

@@ -42,10 +42,9 @@ module hw5_unit(
 );
 
 
-  //-------------------------------------
-  // PHASE 0: perform the ALU operations
+  /* PHASE 0: perform the ALU operations */
 
-    // operation ID
+  // operation ID
     reg [`DATABITS-1:0] in_databits_phase0;
     reg [1:0] in_op_phase0;
 
@@ -54,24 +53,21 @@ module hw5_unit(
       in_op_phase0 = in_op;
     end
 
-
-    // addition
+  // addition
     reg [`WIDTH-1:0] add_result_phase0;
 
     always @(*) begin
       add_result_phase0 = a + b;
     end
 
-
-    // subtraction
+  // subtraction
     reg [`WIDTH-1:0] sub_result_phase0;
 
     always @(*) begin
       sub_result_phase0 = a - b;
     end
 
-
-    // multiplication
+  // multiplication
     reg [`WIDTH-1:0] mul_result_phase0;
 
     always @(*) begin
@@ -79,17 +75,16 @@ module hw5_unit(
     end
 
 
-    // always @(posedge clk) begin
-    // 	$display("in_databits_phase0 => %d", in_databits_phase0);
-    // 	$display("in_op_phase0 => %d", in_op_phase0);
-    // 	$display("add_result_phase0 => %d", add_result_phase0);
-    // 	$display("sub_result_phase0 => %d", sub_result_phase0);
-    // 	$display("mul_result_phase0 => %d", mul_result_phase0);
-    // end
+  // always @(posedge clk) begin
+  // 	$display("in_databits_phase0 => %d", in_databits_phase0);
+  // 	$display("in_op_phase0 => %d", in_op_phase0);
+  // 	$display("add_result_phase0 => %d", add_result_phase0);
+  // 	$display("sub_result_phase0 => %d", sub_result_phase0);
+  // 	$display("mul_result_phase0 => %d", mul_result_phase0);
+  // end
 
 
-  //-------------------------------------
-  // PHASE 1: delay the ALU results
+  /* PHASE 1: delay the ALU results */
 
     reg [`DATABITS-1:0] in_databits_phase1;
     reg [1:0] in_op_phase1;
@@ -116,8 +111,7 @@ module hw5_unit(
     // end
 
 
-  //-------------------------------------
-  // PHASE 2: delay the ALU results
+  /* PHASE 2: delay the ALU results */
 
     reg [`DATABITS-1:0] in_databits_phase2;
     reg [1:0] in_op_phase2;
@@ -144,8 +138,7 @@ module hw5_unit(
     // end
 
 
-  //-------------------------------------
-  // PHASE 3: produce the outputs
+  /* PHASE 3: produce the outputs */
 
     reg [`DATABITS-1:0] out_databits_next;
     reg [1:0] out_op_next;
@@ -160,7 +153,6 @@ module hw5_unit(
 
       out_databits_next = in_databits_phase2;
 
-      // determine res_next
       case (in_op_phase2)
         `OP_NOP:
           res_next = 0;

data/samp/pipelined_alu/hw5_unit_test_bench.rb

@@ -0,0 +1,9 @@
+## This is the Ruby side of the bench.
+
+require 'ruby-vpi'
+require 'test/unit'
+
+RubyVPI.init_bench 'hw5_unit_test', :Hw5_unitProto
+
+# service the $ruby_relay callback
+  # The UnitTest library will take control henceforth.

data/samp/pipelined_alu/hw5_unit_test_bench.v

@@ -0,0 +1,39 @@
+/* This is the Verilog side of the bench. */
+
+`define WIDTH 32
+`define DATABITS 7
+`define OP_NOP	0
+`define OP_ADD 1
+`define OP_SUB	2
+`define OP_MULT 3
+
+module hw5_unit_test_bench;
+
+  // instantiate the design under test
+    reg  clk;
+    reg  reset;
+    reg [`DATABITS-1:0] in_databits;
+    reg [`WIDTH-1:0] a;
+    reg [`WIDTH-1:0] b;
+    reg [1:0] in_op;
+    wire [`WIDTH-1:0] res;
+    wire [`DATABITS-1:0] out_databits;
+    wire [1:0] out_op;
+
+    hw5_unit hw5_unit_test_bench_design(.clk(clk), .reset(reset), .in_databits(in_databits), .a(a), .b(b), .in_op(in_op), .res(res), .out_databits(out_databits), .out_op(out_op));
+
+  // connect to the Ruby side of this bench
+    initial begin
+      clk = 0;
+      $ruby_init("ruby", "-w", "-rubygems", "hw5_unit_test_bench.rb");
+    end
+
+    always begin
+      #5 clk = ~clk;
+    end
+
+    always @(posedge clk) begin
+      #1 $ruby_relay;
+    end
+
+endmodule

data/samp/pipelined_alu/hw5_unit_test_design.rb

@@ -0,0 +1,88 @@
+# An interface to the design under test.
+class Hw5_unit
+  include Vpi
+
+  WIDTH = 32
+  DATABITS = 7
+  OP_NOP = 0
+  OP_ADD = 1
+  OP_SUB = 2
+  OP_MULT = 3
+
+  # Supported types of ALU operations.
+  OPERATIONS = constants.grep(/^OP_/).map {|s| const_get s}
+
+  # Number of cycles needed to reset this design.
+  RESET_DELAY = 5
+
+  attr_reader :clk, :reset, :in_databits, :a, :b, :in_op, :res, :out_databits, :out_op
+
+  def initialize
+    @clk = vpi_handle_by_name("hw5_unit_test_bench.clk", nil)
+    @reset = vpi_handle_by_name("hw5_unit_test_bench.reset", nil)
+    @in_databits = vpi_handle_by_name("hw5_unit_test_bench.in_databits", nil)
+    @a = vpi_handle_by_name("hw5_unit_test_bench.a", nil)
+    @b = vpi_handle_by_name("hw5_unit_test_bench.b", nil)
+    @in_op = vpi_handle_by_name("hw5_unit_test_bench.in_op", nil)
+    @res = vpi_handle_by_name("hw5_unit_test_bench.res", nil)
+    @out_databits = vpi_handle_by_name("hw5_unit_test_bench.out_databits", nil)
+    @out_op = vpi_handle_by_name("hw5_unit_test_bench.out_op", nil)
+  end
+
+  def reset!
+    @reset.hexStrVal = 'x'
+    @in_databits.hexStrVal = 'x'
+    @a.hexStrVal = 'x'
+    @b.hexStrVal = 'x'
+    @in_op.hexStrVal = 'x'
+
+
+    @reset.intVal = 1
+
+    RESET_DELAY.times do
+      relay_verilog
+    end
+
+    @reset.intVal = 0
+  end
+
+  # Represents an ALU operation.
+  class Operation
+    attr_accessor :type, :tag, :arg1, :arg2, :stage, :result
+
+    def initialize(type, tag, arg1 = 0, arg2 = 0)
+      raise ArgumentError unless OPERATIONS.include? type
+
+      @type = type
+      @tag = tag
+      @arg1 = arg1
+      @arg2 = arg2
+
+      @stage = 0
+    end
+
+    # Computes the result of this operation.
+    def compute
+      case @type
+        when OP_ADD
+          @arg1 + @arg2
+
+        when OP_SUB
+          @arg1 - @arg2
+
+        when OP_MULT
+          @arg1 * @arg2
+
+        when OP_NOP
+          nil
+
+        else
+          raise
+      end
+    end
+
+    def compute!
+      @result = compute
+    end
+  end
+end

data/samp/pipelined_alu/hw5_unit_test_proto.rb

@@ -0,0 +1,8 @@
+# A prototype of the design under test.
+class Hw5_unitProto < Hw5_unit
+  def simulate!
+    # read inputs
+    # simulate design's behavior
+    # produce outputs
+  end
+end

data/samp/pipelined_alu/hw5_unit_test_runner.rake

@@ -0,0 +1,28 @@
+## This file builds and runs the test.
+
+# These are source files that are to be simulated.
+SIMULATOR_SOURCES = [
+  'hw5_unit_test_bench.v',
+  'hw5_unit.v',
+]
+
+# This specifies the "top module" that is to be simulated.
+SIMULATOR_TARGET = 'hw5_unit_test_bench'
+
+# These are command-line arguments for the simulator.
+# They can be specified as a string or an array of strings.
+SIMULATOR_ARGS = {
+  # GPL Cver
+  :cver => '',
+
+  # Icarus Verilog
+  :ivl => '',
+
+  # Synopsys VCS
+  :vcs => '',
+
+  # Mentor Modelsim
+  :vsim => '',
+}
+
+require 'ruby-vpi/runner'

data/samp/pipelined_alu/hw5_unit_test_spec.rb

@@ -0,0 +1,88 @@
+## This specification verifies the design under test.
+=begin
+  Copyright 2006 Suraj N. Kurapati
+
+  This file is part of Ruby-VPI.
+
+  Ruby-VPI is free software; you can redistribute it and/or
+  modify it under the terms of the GNU General Public License
+  as published by the Free Software Foundation; either version 2
+  of the License, or (at your option) any later version.
+
+  Ruby-VPI is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with Ruby-VPI; if not, write to the Free Software Foundation,
+  Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+=end
+
+require 'InputGenerator'
+
+class Hw5_unit_test_spec < Test::Unit::TestCase
+  include Vpi
+
+  # Number of input sequences to test.
+  NUM_TESTS = 4000
+
+  # Bitmask capable of capturing ALU result.
+  ALU_RESULT_MASK = (2 ** Hw5_unit::WIDTH) - 1
+
+  # Upper limit of values allowed for an operation's tag.
+  OPERATION_TAG_LIMIT = 2 ** Hw5_unit::DATABITS
+
+  def setup
+    @ig = InputGenerator.new(Hw5_unit::WIDTH)
+
+    @design = Hw5_unit.new
+    @design.reset!
+  end
+
+  def test_pipeline
+    issuedOps = []
+    numIssued = numVerified = 0
+
+    until numVerified == NUM_TESTS
+      # issue a new operation
+        if numIssued < NUM_TESTS
+          op = Hw5_unit::Operation.new(
+            Hw5_unit::OPERATIONS[rand(Hw5_unit::OPERATIONS.size)],
+            numIssued % OPERATION_TAG_LIMIT,
+            @ig.gen.abs,
+            @ig.gen.abs
+          )
+
+          @design.a.intVal = op.arg1
+          @design.b.intVal = op.arg2
+          @design.in_op.intVal = op.type
+          @design.in_databits.intVal = op.tag
+
+          issuedOps << op
+          numIssued += 1
+        end
+
+      relay_verilog
+
+      # verify result of finished operation
+        unless @design.out_databits.x?
+          finishedOp = Hw5_unit::Operation.new(
+            @design.out_op.intVal,
+            @design.out_databits.intVal
+          )
+          finishedOp.result = @design.res.intVal & ALU_RESULT_MASK
+
+          expectedOp = issuedOps.shift
+          assert_equal expectedOp.type, finishedOp.type, "incorrect operation"
+          assert_equal expectedOp.tag, finishedOp.tag, "incorrect tag"
+
+          unless finishedOp.type == Hw5_unit::OP_NOP
+            assert_equal expectedOp.compute & ALU_RESULT_MASK, finishedOp.result, "incorrect result"
+          end
+
+          numVerified += 1
+        end
+    end
+  end
+end