ruby-vpi 14.0.0 → 15.0.0
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- data/bin/generate_test_tpl/proto.rb +8 -6
- data/doc/common.css +1 -0
- data/doc/history.html +357 -281
- data/doc/history.yml +35 -1
- data/doc/intro.inc +1 -1
- data/doc/manual.doc +38 -29
- data/doc/manual.html +109 -63
- data/doc/readme.html +6 -6
- data/doc/rss.xml +69 -1
- data/ext/Rakefile +1 -5
- data/ext/extconf.rb +0 -5
- data/ext/relay.c +1 -1
- data/ext/vlog.c +1 -1
- data/lib/ruby-vpi/vpi.rb +50 -4
- data/lib/ruby-vpi.rb +7 -7
- data/ref/c/annotated.html +6 -1
- data/ref/c/common_8h.html +1 -1
- data/ref/c/files.html +2 -1
- data/ref/c/functions.html +40 -20
- data/ref/c/functions_vars.html +40 -20
- data/ref/c/globals.html +212 -5
- data/ref/c/globals_0x62.html +62 -0
- data/ref/c/globals_0x63.html +19 -3
- data/ref/c/globals_0x65.html +8 -2
- data/ref/c/globals_0x66.html +19 -3
- data/ref/c/globals_0x67.html +64 -0
- data/ref/c/globals_0x69.html +62 -0
- data/ref/c/globals_0x6c.html +64 -0
- data/ref/c/globals_0x6d.html +10 -3
- data/ref/c/globals_0x6e.html +63 -0
- data/ref/c/globals_0x70.html +8 -2
- data/ref/c/globals_0x72.html +14 -4
- data/ref/c/globals_0x73.html +189 -3
- data/ref/c/globals_0x74.html +8 -2
- data/ref/c/globals_0x75.html +63 -0
- data/ref/c/globals_0x76.html +14 -4
- data/ref/c/globals_0x78.html +8 -2
- data/ref/c/globals_defs.html +6 -1
- data/ref/c/globals_defs_0x65.html +6 -1
- data/ref/c/globals_defs_0x6c.html +57 -0
- data/ref/c/globals_defs_0x6e.html +56 -0
- data/ref/c/globals_defs_0x70.html +6 -1
- data/ref/c/globals_defs_0x72.html +57 -0
- data/ref/c/globals_defs_0x73.html +165 -0
- data/ref/c/globals_defs_0x75.html +56 -0
- data/ref/c/globals_defs_0x76.html +10 -3
- data/ref/c/globals_defs_0x78.html +6 -1
- data/ref/c/globals_enum.html +1 -1
- data/ref/c/globals_eval.html +1 -1
- data/ref/c/globals_func.html +174 -14
- data/ref/c/globals_func_0x66.html +63 -0
- data/ref/c/globals_func_0x67.html +56 -0
- data/ref/c/globals_func_0x69.html +54 -0
- data/ref/c/globals_func_0x6d.html +56 -0
- data/ref/c/globals_func_0x70.html +54 -0
- data/ref/c/globals_func_0x72.html +57 -0
- data/ref/c/globals_func_0x73.html +113 -0
- data/ref/c/globals_func_0x76.html +58 -0
- data/ref/c/globals_type.html +6 -3
- data/ref/c/globals_vars.html +89 -3
- data/ref/c/index.html +1 -1
- data/ref/c/main_8c.html +2 -2
- data/ref/c/main_8h.html +1 -1
- data/ref/c/relay_8c.html +1 -1
- data/ref/c/relay_8h.html +1 -1
- data/ref/c/structswig__cast__info.html +98 -0
- data/ref/c/structswig__class.html +115 -0
- data/ref/c/structswig__module__info.html +132 -0
- data/ref/c/structswig__type__info.html +132 -0
- data/ref/c/structt__cb__data.html +1 -1
- data/ref/c/structt__vpi__delay.html +1 -1
- data/ref/c/structt__vpi__error__info.html +1 -1
- data/ref/c/structt__vpi__strengthval.html +1 -1
- data/ref/c/structt__vpi__systf__data.html +1 -1
- data/ref/c/structt__vpi__time.html +1 -1
- data/ref/c/structt__vpi__value.html +1 -1
- data/ref/c/structt__vpi__vecval.html +1 -1
- data/ref/c/structt__vpi__vlog__info.html +1 -1
- data/ref/c/swig__wrap_8cin.html +11610 -0
- data/ref/c/unions__vpi__value__value.html +166 -0
- data/ref/c/verilog_8h.html +1 -1
- data/ref/c/vlog_8c.html +3 -3
- data/ref/c/vlog_8h.html +1 -1
- data/ref/c/vpi__user_8h.html +1 -1
- data/ref/ruby/classes/RDoc.html +5 -5
- data/ref/ruby/classes/RDoc.src/{M000045.html → M000053.html} +0 -0
- data/ref/ruby/classes/RubyVpi.src/M000029.html +27 -27
- data/ref/ruby/classes/Vpi/Handle.html +93 -57
- data/ref/ruby/classes/Vpi/Handle.src/M000037.html +5 -5
- data/ref/ruby/classes/Vpi/Handle.src/M000038.html +5 -9
- data/ref/ruby/classes/Vpi/Handle.src/M000039.html +5 -31
- data/ref/ruby/classes/Vpi/Handle.src/M000040.html +5 -74
- data/ref/ruby/classes/Vpi/Handle.src/M000041.html +8 -17
- data/ref/ruby/classes/Vpi/Handle.src/M000042.html +8 -11
- data/ref/ruby/classes/Vpi/Handle.src/M000043.html +22 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000044.html +31 -55
- data/ref/ruby/classes/Vpi/Handle.src/M000045.html +87 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000046.html +30 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000047.html +24 -0
- data/ref/ruby/classes/Vpi/Handle.src/M000049.html +68 -0
- data/ref/ruby/classes/Vpi/S_vpi_time.html +186 -0
- data/ref/ruby/classes/Vpi/S_vpi_time.src/M000050.html +18 -0
- data/ref/ruby/classes/Vpi/S_vpi_time.src/M000051.html +19 -0
- data/ref/ruby/classes/Vpi/S_vpi_value.html +167 -0
- data/ref/ruby/classes/Vpi/S_vpi_value.src/M000034.html +18 -0
- data/ref/ruby/classes/Vpi/S_vpi_value.src/M000035.html +18 -0
- data/ref/ruby/classes/Vpi/S_vpi_value.src/M000036.html +18 -0
- data/ref/ruby/classes/Vpi.html +3 -1
- data/ref/ruby/classes/Vpi.src/M000030.html +14 -14
- data/ref/ruby/classes/Vpi.src/M000031.html +4 -4
- data/ref/ruby/classes/Vpi.src/M000032.html +24 -25
- data/ref/ruby/classes/Vpi.src/M000033.html +8 -8
- data/ref/ruby/created.rid +1 -1
- data/ref/ruby/files/lib/ruby-vpi/vpi_rb.html +1 -1
- data/ref/ruby/files/lib/ruby-vpi_rb.html +1 -1
- data/ref/ruby/fr_class_index.html +2 -0
- data/ref/ruby/fr_method_index.html +22 -14
- data/samp/counter/counter_rspec_proto.rb +8 -6
- data/samp/counter/counter_xunit_proto.rb +8 -6
- data/samp/pipelined_alu/hw5_unit_test_proto.rb +2 -2
- metadata +42 -6
- data/ref/ruby/classes/Vpi/Handle.src/M000034.html +0 -18
- data/ref/ruby/classes/Vpi/Handle.src/M000035.html +0 -18
- data/ref/ruby/classes/Vpi/Handle.src/M000036.html +0 -18
data/doc/history.yml
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Version: 15.0.0
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Date: 2007-01-13
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Summary: |
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This release fixes a problem with compilation of the C extension, and makes clock generation code correctly affect Ruby prototypes.
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Acknowledgment: |
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Thanks to Derek Graham for reporting the problem with compilation of the C extension.
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Notice: |
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* The @Vpi::advance_time@ method (instead of the @Vpi::simulate@ method) now invokes the design's @simulate!@ method when prototyping is enabled.
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This makes clock generation code (passed to the @RubyVpi::init_bench@ method) affect Ruby prototypes, just as it affects a real Verilog design.
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As a result, Ruby prototypes may need to check for edge-triggering through the new @Vpi::Handle.posedge?@ and @Vpi::Handle.negedge?@ methods. For example, see the "new implementation of the Counter prototype":manual.html#fig..counter_proto.rb.
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h3. New features
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* Added @Vpi::Handle.posedge?@ and @Vpi::Handle.negedge?@ methods which check if a handle's logic value is currently at a positive or negative edge, respectively.
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* Added @Vpi::S_vpi_time.integer@ and @Vpi::S_vpi_time.integer=@ methods which access the @high@ and @low@ integer fields as a single 64-bit integer.
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* Added utility methods for accessing the @value@ field in the @Vpi::S_vpi_value@ structure.
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Details: |
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* Fixed problem with incorrect Ruby library flag in <tt>ext/extconf.rb</tt>. It happens that the @mkmf@ library determines the correct library flag all by itself!
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* Added new "prototyping section":manual.html#usage.prototyping to user manual.
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* Fixed some broken URLs in user documentation.
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Version: 14.0.0
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Date: 1999-10-31
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Summary: |
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This is Kazuhiro HIWADA's initial testing release of Ruby-VPI. See its "original announcement":http://
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This is Kazuhiro HIWADA's initial testing release of Ruby-VPI. See its "original announcement":http://blade.nagaokaut.ac.jp/cgi-bin/scat.rb/ruby/ruby-list/18193 and "source code":http://rubyforge.org/frs/?group_id=1339&release_id=8852.
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* Added ability to relay control from Verilog test bench to Ruby (using @$ruby_callback@) and vice versa (using @PLI::relay_Verilog@).
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data/doc/intro.inc
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h3. Portable
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* Supports the _entire_ "IEEE Std 1364-2005"
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* Supports the _entire_ "IEEE Std 1364-2005":http://ieeexplore.ieee.org/xpl/standardstoc.jsp?isnumber=33945 VPI standard.
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* Works with all "major Verilog simulators":manual.html#setup.reqs available today.
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** Compiled _just once_ during "installation":manual.html#setup.installation and used forever!
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data/doc/manual.doc
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For example, the @s_vpi_value@ structure becomes the @S_vpi_value@ class in Ruby. Likewise, the @vpiIntVal@ constant becomes the @VpiIntVal@ constant in Ruby.
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Note that this capitalization rule does
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Note that this capitalization rule does _not_ apply to VPI functions; their names remain unchanged in Ruby.
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h3(#usage.vpi.handles). Handles
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h4. Accessing a handle's properties
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To access a handle's properties, invoke the
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To access a handle's properties, invoke the property name, using the following format, as a method on the handle. <xref ex..properties> shows how this naming format is used.
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<% figure "Method naming format for accessing a handle's properties" do %>
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|_. Operation |_. _ |_. Property |_. _ |_. Accessor |_. Addendum |
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In this example, the handle being monitored is the @Counter.count@ signal from <xref#fig..counter.v_decl>.
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<code>
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cbTime = S_vpi_time.new
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cbTime.type = VpiSimTime
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cbTime.low = 0
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cbTime.high = 0
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cbValue = S_vpi_value.new
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cbValue.format = VpiIntVal
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cbData = S_cb_data.new
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cbData.reason = CbValueChange
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cbData.obj = Counter.count
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cbData.time = cbTime
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cbData.value = cbValue
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cbData.index = 0
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cbHandle = vpi_register_cb(cbData) do |data|
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time = (data.time.high << 32) | data.time.low
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count = data.value.value.integer
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<% end %>
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h2(#usage.prototyping). Prototyping
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Ruby-VPI enables you to rapidly prototype your designs in Ruby without having to do full-scale implementations in Verilog. This lets you explore and evaluate different design choices quickly.
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In order to create a prototype,
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# "Determine the *interface*":#usage.tutorial.declare-design (Verilog module declaration) of your design.
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# "Generate a test":#usage.tutorial.generate-test for that interface.
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# "Implement the prototype":#usage.tutorial.implement-proto in the generated <tt>proto.rb</tt> file.
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# "Verify the prototype":#usage.tutorial.test-proto against its specification.
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Once you are satisfied with your prototype, you can proceed to "implement your design in Verilog":#usage.tutorial.implement-design. This process is often a simple translation your Ruby prototype into your Verilog. At the very least, your prototype serves as a reference while you are implementing your Verilog design.
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Once your design has been implemented in Verilog, you can use the _same_ specification, which was originally used to verify your prototype, to verify your Verilog design.
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h2(#usage.debugger). Debugging
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The "ruby-debug project":http://www.datanoise.com/articles/category/ruby-debug serves as the interactive debugger for Ruby-VPI.
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Now that we have a "specification":#glossary.specification against which to verify our "design":#glossary.design, let us build a prototype of our design. By doing so, we exercise our specification, experience potential problems that may arise when we later implement our design in Verilog, and gain confidence in our work. The result of this proceess is illustrated by <xref #fig..counter_proto.rb>.
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<% example "Ruby prototype of our Verilog design", "#fig..counter_proto.rb" do %>
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<code>
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def Counter.simulate!
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if reset.intVal == 1
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count.intVal = 0
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else
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count.intVal += 1
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end
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end
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</code>
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<code><%= File.read '../samp/counter/counter_rspec_proto.rb' %></code>
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<% end %>
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<% important "Before we continue..." do %>
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Now that we have implemented our prototype, we are ready to verify it against our "specification":#glossary.specification by running the "test":#glossary.test. This process is illustrated by <xref #fig..test-proto.rspec> and <xref #fig..test-proto.unit-test>.
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In these examples, the @PROTOTYPE@ environment variable is assigned a non-empty value while running the test so that, instead of our design, our prototype is verified against our specification. You can also assign a value to @PROTOTYPE@ before running the test, by using your shell's *export* or *setenv* command. Finally, the "GPL Cver simulator":#setup.reqs, denoted by _cver_, is used to run the simulation.
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<% example "Running a test with specification in rSpec format", "#fig..test-proto.rspec" do %>
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</pre>
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<% end %>
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In these examples, the @PROTOTYPE@ environment variable is assigned a non-empty value while running the test so that, instead of our design, our prototype is verified against our specification. You can also assign a value to @PROTOTYPE@ before running the test, by using your shell's *export* or *setenv* command. Finally, the "GPL Cver simulator":#setup.reqs, denoted by _cver_, is used to run the simulation.
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<% tip "What can the test runner do?" do %>
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If you invoke the test runner (1) without any arguments or (2) with the <tt>--tasks</tt> option, it will show you a list of tasks that it can perform for you.
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<% end %>
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Now that we have implemented our "design":#glossary.design, we are ready to verify it against our "specification":#glossary.specification by running the "test":#glossary.test. <xref #fig..test-design.rspec> and <xref #fig..test-design.unit-test> illustrate this process.
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In these examples, the @PROTOTYPE@ environment variable is _not_ specified while running the test, so that our design, instead of our prototype, is verified against our specification. You can also achieve this effect by assigning an empty value to @PROTOTYPE@, or by using your shell's *unset* command. Finally, the "GPL Cver simulator":#setup.reqs, denoted by _cver_, is used to run the simulation.
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<% end %>
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In these examples, the @PROTOTYPE@ environment variable is _not_ specified while running the test, so that our design, instead of our prototype, is verified against our specification. You can also achieve this effect by assigning an empty value to @PROTOTYPE@, or by using your shell's *unset* command. Finally, the "GPL Cver simulator":#setup.reqs, denoted by _cver_, is used to run the simulation.
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h1(#hacking). Hacking
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h3(#problems.ivl.vpi_reset). Vpi::reset
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<% caution do %>
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The @vpi_control@ method was removed in release 3.0.0 (2006-04-23). Please use @Vpi::vpi_control(VpiReset)@ instead.
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<% end %>
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In version 0.8 of Icarus Verilog, the @vpi_control(vpiReset)@ VPI function causes an assertion to fail inside the simulator. As a result, the simulation terminates and a core dump is produced.
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<li>5.1.2 <a href="#usage.vpi.callbacks">Callbacks</a></li>
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<li>5.2 <a href="#usage.
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<p>It is meant to be read in conjunction with the <a href="../ref/ruby/index.html">reference documentation for Ruby-VPI</a>. In addition, if you are new to <a href="http://www.ruby-lang.org">the Ruby language</a>, you are encouraged to <a href="http://www.ruby-lang.org/en/documentation/">explore its documentation</a> alongside this manual.</p>
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<p>For example, the <code class="code">s_vpi_value</code> structure becomes the <code class="code"><span style="color:#036; font-weight:bold">S_vpi_value</span></code> class in Ruby. Likewise, the <code class="code">vpiIntVal</code> constant becomes the <code class="code"><span style="color:#036; font-weight:bold">VpiIntVal</span></code> constant in Ruby.</p>
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<p>Once you are satisfied with your prototype, you can proceed to <a href="#usage.tutorial.implement-design">implement your design in Verilog</a>. This process is often a simple translation your Ruby prototype into your Verilog. At the very least, your prototype serves as a reference while you are implementing your Verilog design.</p>
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<p>The <tt>samp</tt> directory contains several sample tests which illustrate how Ruby-VPI can be used. Each sample has an associated <tt>Rakefile</tt> which simplifies the process of running it. Therefore, simply navigate into an example directory and run the <pre>rake</pre> command to get started.</p>
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<p>By converting Verilog header files into Ruby, your <a href="#glossary.test">test</a> can utilize the same <code class="code"><span style="background-color:#f0fff0"><span style="color:#161">`</span><span style="color:#2B2">define</span></span></code> constants that are used in the Verilog <a href="#glossary.design">design</a>.</p>
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<p>First, we need a <a href="#glossary.design">design</a> to verify. In this tutorial, <a href="#fig..counter.v_decl">the example named “Declaration of a simple up-counter with synchronous reset”</a> will serve as our design. Its interface is composed of the following parts:</p>
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<p>Now that we have a <a href="#glossary.design">design</a> to verify, let us generate a <a href="#glossary.test">test</a> for it using the <a href="#usage.tools.generate-test">automated test generator</a>. This tool allows us to implement our specification in either rSpec, xUnit, or our very own format.</p>
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<p>So far, the test generation tool has created a basic foundation for our <a href="#glossary.test">test</a>. Now we must build upon this foundation by identifying our <a href="#glossary.expectation">expectation</a> of the <a href="#glossary.design">design</a>. That is, how do we expect the design to <em>behave</em> under certain conditions?</p>
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<p>Now that we have a <a href="#glossary.specification">specification</a> against which to verify our <a href="#glossary.design">design</a>, let us build a prototype of our design. By doing so, we exercise our specification, experience potential problems that may arise when we later implement our design in Verilog, and gain confidence in our work. The result of this proceess is illustrated by <a href="#fig..counter_proto.rb">the example named “Ruby prototype of our Verilog design”</a>.</p>
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<p>Now that we have implemented our prototype, we are ready to verify it against our <a href="#glossary.specification">specification</a> by running the <a href="#glossary.test">test</a>. This process is illustrated by <a href="#fig..test-proto.rspec">the example named “Running a test with specification in rSpec format”</a> and <a href="#fig..test-proto.unit-test">the example named “Running a test with specification in xUnit format”</a>.</p>
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<p>In these examples, the <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code> environment variable is assigned a non-empty value while running the test so that, instead of our design, our prototype is verified against our specification. You can also assign a value to <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code> before running the test, by using your shell’s <strong>export</strong> or <strong>setenv</strong> command. Finally, the <a href="#setup.reqs"><span class="caps">GPL</span> Cver simulator</a>, denoted by <em>cver</em>, is used to run the simulation.</p>
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<p>In these examples, the <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code> environment variable is assigned a non-empty value while running the test so that, instead of our design, our prototype is verified against our specification. You can also assign a value to <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code> before running the test, by using your shell’s <strong>export</strong> or <strong>setenv</strong> command. Finally, the <a href="#setup.reqs"><span class="caps">GPL</span> Cver simulator</a>, denoted by <em>cver</em>, is used to run the simulation.</p>
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<p>Now that we have implemented and verified our prototype, we are ready to implement our <a href="#glossary.design">design</a>. This is often quite simple because we translate <em>existing</em> code from Ruby (our prototype) into Verilog (our design). The result of this process is illustrated by <a href="#fig..counter.v_impl">the example named “Implementation of a simple up-counter with synchronous reset”</a>.</p>
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<p>Now that we have implemented our <a href="#glossary.design">design</a>, we are ready to verify it against our <a href="#glossary.specification">specification</a> by running the <a href="#glossary.test">test</a>. <a href="#fig..test-design.rspec">the example named “Running a test with specification in rSpec format”</a> and <a href="#fig..test-design.unit-test">the example named “Running a test with specification in xUnit format”</a> illustrate this process.</p>
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<p>In these examples, the <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code> environment variable is <em>not</em> specified while running the test, so that our design, instead of our prototype, is verified against our specification. You can also achieve this effect by assigning an empty value to <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code>, or by using your shell’s <strong>unset</strong> command. Finally, the <a href="#setup.reqs"><span class="caps">GPL</span> Cver simulator</a>, denoted by <em>cver</em>, is used to run the simulation.</p>
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<p>In these examples, the <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code> environment variable is <em>not</em> specified while running the test, so that our design, instead of our prototype, is verified against our specification. You can also achieve this effect by assigning an empty value to <code class="code"><span style="color:#036; font-weight:bold">PROTOTYPE</span></code>, or by using your shell’s <strong>unset</strong> command. Finally, the <a href="#setup.reqs"><span class="caps">GPL</span> Cver simulator</a>, denoted by <em>cver</em>, is used to run the simulation.</p>
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<p>The <code class="code">vpi_control</code> method was removed in release 3.0.0 (2006-04-23). Please use <code class="code"><span style="color:#036; font-weight:bold">Vpi</span>::vpi_control(<span style="color:#036; font-weight:bold">VpiReset</span>)</code> instead.</p>
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<p>Ruby-VPI is a <a href="http://www.ruby-lang.org">Ruby</a> interface to <a href="http://ieeexplore.ieee.org/xpl/standardstoc.jsp?isnumber=33945"><span class="caps">IEEE 1364</span>-2005 Verilog <span class="caps">VPI</span></a>. It lets you create complex Verilog test benches easily and wholly in Ruby.</p>
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