rtl_circuit 0.7

checksums.yaml

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+---
+SHA256:
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+  data.tar.gz: 6a39ac68ccf30ff37ab674dad83ff74686fe81d6e3cf6e1c8b1cca5d0d88c384
+SHA512:
+  metadata.gz: c5af6786663be64b4ff0dff83e240732a48ba17e0980ae7585f7a8d8967f107a81cf106608049829330f6aa094fd777bf9c26543595501ee469b4015ed6eecd2
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data/lib/rtl/circuit.rb

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+module RTL
+
+  class Circuit
+    attr_accessor :name
+    attr_accessor :iname
+    attr_accessor :ports
+    attr_accessor :components
+    attr_accessor :father
+    attr_accessor :signals
+    attr_accessor :properties
+
+    @@id=-1
+
+    def initialize name=nil
+      @name=name
+      @iname="#{name}_#{@@id+=1}"
+      @ports={in:[],out:[]}
+      @signals=[]
+      @components=[]
+      @properties={}
+      @color="cadetblue"
+    end
+
+    def add element
+      port=circuit=sig=element
+      case element
+      when Sig
+        @signals<< sig
+        sig.circuit=self
+      when Port
+        @ports[port.dir] << port
+        port.circuit=self
+      when Circuit
+        @components << circuit
+        circuit.father=self
+      else
+        raise "ERROR : when adding '#{element}'"
+      end
+    end
+
+    def port_named dir,name
+      @ports[dir].find{|p| p.name==name}
+    end
+
+    def port name
+      all=@ports[:in]+@ports[:out]
+      all.flatten.find{|p| p.name==name}
+    end
+
+    def component_named name
+      @components.find{|comp| comp.iname==name}
+    end
+
+    def inputs
+      @ports[:in]
+    end
+
+    def outputs
+      @ports[:out]
+    end
+
+    def wires
+      wires=[]
+      wires << inputs.map{|p| p.fanout}
+      wires << signals.map{|p| p.fanout}
+      wires << components.map{|comp| comp.outputs.map{|o| o.fanout}}
+      wires.flatten
+    end
+
+    def new_instance
+      @@clone_id||={}
+      @@clone_id[name]||=-1
+      @@clone_id[name]+=1
+      clone=Marshal.load(Marshal.dump(self))
+      clone.iname=self.name+"_#{@@clone_id[name]}"
+      clone
+    end
+
+    def make_lib
+      filename="#{name}.lib"
+      File.open(filename,'w') do |f|
+        f.puts Marshal.dump(self)
+      end
+    end
+
+    def to_dot
+      Printer.new.print self
+    end
+  end
+
+  class Port
+    attr_accessor :dir
+    attr_accessor :name
+    attr_accessor :circuit
+    attr_accessor :fanout
+    attr_accessor :properties
+    def initialize dir,name
+      @dir=dir
+      @name=name
+      @fanout=[]
+      @properties={}
+    end
+
+    def connect port
+      puts "connecting #{self.name}-> #{port.name}" if $verbose
+      @fanout << Wire.new(self,port)
+    end
+
+    def type=(t)
+      @properties[:type]=t
+    end
+
+    def type
+      @properties[:type]
+    end
+  end
+
+  class Sig < Port
+    def initialize name
+      super(:out,name)
+    end
+  end
+
+  class Wire
+    @@id=-1
+    attr_accessor :name
+    attr_accessor :source,:sink
+    attr_accessor :properties
+    def initialize source,sink
+      @name="w_#{@@id+=1}"
+      @source=source
+      @sink=sink
+      @properties={}
+    end
+  end
+end

data/lib/rtl/code.rb

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+class Code
+
+  attr_accessor :indent,:lines
+
+  def initialize str=nil
+    @lines=[]
+    (@lines << str) if str
+    @indent=0
+  end
+
+  def <<(thing)
+    if (code=thing).is_a? Code
+      code.lines.each do |line|
+        @lines << " "*@indent+line.to_s
+      end
+    elsif thing.is_a? Array
+      thing.each do |kode|
+        @lines << kode
+      end
+    elsif thing.nil?
+    else
+      @lines << " "*@indent+thing.to_s
+    end
+  end
+
+  def finalize
+    return @lines.join("\n") if @lines.any?
+    ""
+  end
+
+  def newline
+    @lines << " "
+  end
+
+  def save_as filename,verbose=true
+    str=self.finalize
+    File.open(filename,'w'){|f| f.puts(str)}
+    puts "code saved as : #{filename}" if verbose
+    return filename
+  end
+
+  def size
+    @lines.size
+  end
+
+
+end

data/lib/rtl/library.rb

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+require_relative "circuit"
+
+module RTL
+
+  class UnaryGate < Circuit
+    def initialize
+      name=self.class.to_s.split("::").last
+      super(name)
+      add Port.new(:in,"i")
+      add Port.new(:out,"f")
+    end
+  end
+
+  class BinaryGate < Circuit
+    def initialize
+      name=self.class.to_s.split("::").last
+      super(name)
+      add Port.new(:in,"i1")
+      add Port.new(:in,"i2")
+      add Port.new(:out,"f")
+    end
+  end
+
+  class Not < UnaryGate
+  end
+
+  class Or < BinaryGate
+  end
+
+  class And < BinaryGate
+  end
+
+  class Nand < BinaryGate
+  end
+
+  class Nor < BinaryGate
+  end
+
+  class Xor < BinaryGate
+  end
+
+  class Reg < Circuit
+    def initialize
+      name="Reg"
+      super(name)
+      add Port.new(:in ,"d")
+      add Port.new(:out,"q")
+      @color="darkorange"
+    end
+  end
+
+  class Mux < Circuit
+    attr_accessor :arity
+    def initialize
+      name="Mux"
+      super(name)
+      @arity=0
+      add Port.new("i0",:in)
+      add Port.new("i1",:in)
+      add Port.new("sel",:in)
+      add Port.new("f",:out)
+    end
+
+    def add port
+      @arity+=1
+      super port
+    end
+  end
+
+  class Add < BinaryGate
+  end
+
+  class Sub < BinaryGate
+  end
+
+  class Mul < BinaryGate
+  end
+
+  class Div < BinaryGate
+  end
+
+  class Rem < BinaryGate
+  end
+
+end

data/lib/rtl/printer.rb

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+require_relative 'code'
+
+module RTL
+
+  class Printer
+
+    def print circuit
+      dot=Code.new
+      dot << "digraph G {"
+      dot.indent=2
+      dot << "graph [rankdir = LR];"
+      circuit.components.each do |comp|
+        inputs_dot ="{"+comp.ports[:in].collect{|e| "<#{e.name}>#{e.name}"}.join("|")+"}"
+        outputs_dot="{"+comp.ports[:out].collect{|e| "<#{e.name}>#{e.name}"}.join("|")+"}"
+        p color=circuit.color
+        dot << "#{comp.iname}[ shape=record; style=filled ; color=#{color} ; label=\"{ #{inputs_dot}| #{comp.name} | #{outputs_dot} }\"];"
+      end
+      circuit.ports[:in].each do |p|
+        dot << "#{p.name}[shape=cds label=\"#{p.name}\"];"
+      end
+      circuit.ports[:out].each do |p|
+        dot << "#{p.name}[shape=cds label=\"#{p.name}\"];"
+      end
+      circuit.signals.each do |sig|
+        dot << "#{sig.name}[shape=point ; xlabel=\"#{sig.name}\"]; /* sig */"
+      end
+      circuit.ports[:in].each do |source|
+        source.fanout.each do |wire|
+          source_name=source.name
+          sink=wire.sink
+          sink_name=sink.name
+          if sink.circuit!=circuit
+            sink_name="#{sink.circuit.iname}:#{sink_name}"
+          end
+          wire_name=wire.name if $verbose
+          dot << "#{source_name} -> #{sink_name} [label=\"#{wire_name}\"]/* pin */"
+        end
+      end
+      circuit.signals.each do |sig|
+        sig.fanout.each do |wire|
+          source_name=sig.name
+          sink  =wire.sink
+          sink_name=sink.name
+          if sink.circuit!=circuit
+            sink_name="#{sink.circuit.iname}:#{sink_name}"
+          end
+          wire_name=wire.name if $verbose
+          dot << "#{source_name} -> #{sink_name} [label=\"#{wire_name}\"] /* sig */"
+        end
+      end
+
+      circuit.components.each do |c|
+        c.ports[:out].each do |p|
+          p.fanout.each do |wire| #pin
+            pout=wire.sink
+            c=pout.circuit==circuit ? "#{pout.name}" : "#{pout.circuit.iname}:#{pout.name}"
+            if c!=p.circuit.iname+":"+p.name
+              wire_name=wire.name if $verbose
+              dot << "#{p.circuit.iname}:#{p.name} -> #{c}[label=\"#{wire_name}\"]; /* tag3 */"
+            end
+          end
+        end
+      end
+      dot.indent=0
+      dot << "}"
+      dot.save_as "#{circuit.name}.dot",verbose=false
+    end
+
+    def print_svg circuit
+      svg=Code.new
+      svg << "{"
+      svg.indent=2
+      svg << "creator: \"RTL::printer version #{version}\","
+      svg << "modules: "
+      svg.indent=4
+      svg.indent=2
+      svg.indent=0
+      svg << "}"
+      svg
+    end
+  end
+end

data/lib/rtl.rb

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+require_relative "./rtl/circuit"
+require_relative "./rtl/library"
+require_relative "./rtl/printer"
+require_relative "./rtl/placer"
+require_relative "./rtl/json_parser"
+
+module RTL
+end

data/tests/json/testing_json.rb

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+require_relative "../../lib/rtl"
+puts "testing json".center(40,'=')
+g=Parser.new.parse "ex_1.json"
+g.print_info

data/tests/pnr/pnr_0.rb

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+#require "rtl_circuit"
+require_relative "../../../rtl/lib/rtl.rb"
+
+include RTL
+
+top=Circuit.new("top_0")
+top.add a=Port.new(:in,"a")
+top.add b=Port.new(:in,"b")
+top.add f=Port.new(:out,"f")
+top.add g1=And.new
+top.add g2=Xor.new
+
+a.connect g1.port("i1")
+b.connect g1.port("i2")
+b.connect g2.port("i2")
+g1.port("f").connect g2.port("i1")
+g2.port("f").connect f
+top.to_dot
+
+Placer.new.place top

data/tests/pnr/pnr_1.rb

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+#require "rtl_circuit"
+require_relative "../../../rtl/lib/rtl.rb"
+
+include RTL
+
+top=Circuit.new("top_1")
+top.add a=Port.new(:in,"a")
+top.add b=Port.new(:in,"b")
+top.add c=Port.new(:in,"c")
+top.add d=Port.new(:in,"d")
+top.add f=Port.new(:out,"f")
+
+top.add a1=And.new
+top.add a2=Or.new
+top.add a3=Nor.new
+top.add a4=Nand.new
+top.add a5=Xor.new
+
+a.connect a1.port("i1")
+b.connect a1.port("i2")
+b.connect a2.port("i1")
+c.connect a2.port("i2")
+c.connect a3.port("i1")
+d.connect a3.port("i2")
+a2.port("f").connect a4.port("i1")
+a3.port("f").connect a4.port("i2")
+a1.port("f").connect a5.port("i1")
+a4.port("f").connect a5.port("i2")
+a5.port("f").connect f
+top.to_dot
+
+Placer.new.place top

data/tests/pnr/sync_0.rb

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+require_relative "../../../synchrony/lib/synchrony"
+
+puts "synchrony 1"
+
+sync= %{
+  circuit sync1
+    input a,b,c,d,e,f,g,h,i,j
+    output o1,o2
+    sig s1
+    s1=(a and !b) or (c and d)
+    o1=((e and f) xor s1) and g
+    o2=(e and f) or (s1 and h) and reg(i or j)
+  end
+}
+filename="sync_0.syc"
+File.open(filename,'w'){|f| f.puts(sync)}
+
+Synchrony::Compiler.new.compile filename

metadata

@@ -0,0 +1,51 @@
+--- !ruby/object:Gem::Specification
+name: rtl_circuit
+version: !ruby/object:Gem::Version
+  version: '0.7'
+platform: ruby
+authors:
+- Jean-Christophe Le Lann
+autorequire: 
+bindir: bin
+cert_chain: []
+date: 2021-02-16 00:00:00.000000000 Z
+dependencies: []
+description: simple digital circuit modeling, with hierarchy and graphviz output
+email: jean-christophe.le_lann@ensta-bretagne.fr
+executables: []
+extensions: []
+extra_rdoc_files: []
+files:
+- lib/rtl.rb
+- lib/rtl/circuit.rb
+- lib/rtl/code.rb
+- lib/rtl/library.rb
+- lib/rtl/printer.rb
+- tests/json/testing_json.rb
+- tests/pnr/pnr_0.rb
+- tests/pnr/pnr_1.rb
+- tests/pnr/sync_0.rb
+homepage: http://www.github.com/JC-LL/rtl
+licenses:
+- GPL-2.0-only
+metadata: {}
+post_install_message: 
+rdoc_options: []
+require_paths:
+- lib
+required_ruby_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+required_rubygems_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+requirements: []
+rubygems_version: 3.0.6
+signing_key: 
+specification_version: 4
+summary: simple digital circuit modeling
+test_files: []