rpi_gpio 0.4.0

checksums.yaml

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+---
+SHA256:
+  metadata.gz: cf2e5fe321ddea6602db36bf081dcdd9b16d1248a584c9fe2156cf3b1cc8764b
+  data.tar.gz: aea0df6d2ce23b6b60ffdd35a1a856c09920fda38dfdcc197f4d38b417129935
+SHA512:
+  metadata.gz: e2d50e340b0d24349c291b4927fa4bc03e3c477862659a4b6a4f81c5a6c10a94e612e70acef98299627fc299f53cad68f15606b9795b610af1e82d559face6d3
+  data.tar.gz: f6495cbea95ddfe0348bd9be92d716d4929329414ef49d6d6649a373f87af4a62346d1fe74631771de24a066b3b7bfcb1335efda76bda8dbd934e5d1eab644de

data/Gemfile

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+source "https://rubygems.org"
+
+gemspec
+

data/Gemfile.lock

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+PATH
+  remote: .
+  specs:
+    rpi_gpio (0.4.0)
+
+GEM
+  remote: https://rubygems.org/
+  specs:
+    diff-lcs (1.4.4)
+    rake (13.0.1)
+    rake-compiler (1.1.1)
+      rake
+    rspec (3.9.0)
+      rspec-core (~> 3.9.0)
+      rspec-expectations (~> 3.9.0)
+      rspec-mocks (~> 3.9.0)
+    rspec-core (3.9.2)
+      rspec-support (~> 3.9.3)
+    rspec-expectations (3.9.2)
+      diff-lcs (>= 1.2.0, < 2.0)
+      rspec-support (~> 3.9.0)
+    rspec-mocks (3.9.1)
+      diff-lcs (>= 1.2.0, < 2.0)
+      rspec-support (~> 3.9.0)
+    rspec-support (3.9.3)
+
+PLATFORMS
+  ruby
+
+DEPENDENCIES
+  rake-compiler
+  rpi_gpio!
+  rspec
+
+BUNDLED WITH
+   2.1.4

data/LICENSE

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+The MIT License (MIT)
+
+Copyright (c) 2014-2020 Nick Lowery
+Copyright (c) 2012-2014 Ben Croston
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

data/README.md

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+# rpi_gpio v0.4.0
+
+Ruby conversion of [RPi.GPIO Python module](https://pypi.python.org/pypi/RPi.GPIO)
+
+## Features
+
+Manipulate your Raspberry Pi's GPIO pins from Ruby!
+
+- Boolean input/output
+- Software-driven PWM (written in C for speed)
+
+Up-to-date with RPi.GPIO Python module version 0.7.0, so it works on all Raspberry Pi models!
+
+## Sample Usage
+
+I aimed to make the gem's usage exactly the same as its Python counterpart -- only with a few semantic differences to utilize Ruby's readability. If anything is confusing, you can always check [here](http://sourceforge.net/p/raspberry-gpio-python/wiki/Examples/) for the original Python module's documentation.
+
+#### Download the gem
+
+The easiest way to download the gem is to use [Bundler](http://bundler.io/) with a Gemfile. In your Gemfile, include the line 
+```ruby
+gem 'rpi_gpio'
+```
+Then you can run `bundle install` to automatically download and compile the gem for your system. To include the gem in a Ruby file, use the line `require 'rpi_gpio'`.
+
+#### Pin numbering
+
+Before you can do anything with the GPIO pins, you need to specify how you want to number them.
+```ruby
+RPi::GPIO.set_numbering :board
+# or
+RPi::GPIO.set_numbering :bcm
+````
+`:board` numbering refers to the physical pin numbers on the Pi, whereas `:bcm` numbering refers to the Broadcom SOC channel numbering. Note that `:bcm` numbering differs between Pi models, while `:board` numbering does not.
+
+#### Input
+
+To receive input from a GPIO pin, you must first initialize it as an input pin:
+```ruby
+RPi::GPIO.setup PIN_NUM, :as => :input
+```
+The pin number will differ based on your selected numbering system and which pin you want to use.
+
+Now you can use the calls
+```ruby
+RPi::GPIO.high? PIN_NUM
+RPi::GPIO.low? PIN_NUM
+```
+to receive either `true` or `false`.
+
+You can use the additional hash argument `:pull` to apply a pull-up or pull-down resistor to the input pin like so:
+```ruby
+RPi::GPIO.setup PIN_NUM, :as => :input, :pull => :down
+# or
+RPi::GPIO.setup PIN_NUM, :as => :input, :pull => :up
+# or (not necessary; :off is the default value)
+RPi::GPIO.setup PIN_NUM, :as => :input, :pull => :off
+```
+
+#### Output
+
+To send output to a GPIO pin, you must first initialize it as an output pin:
+```ruby
+RPi::GPIO.setup PIN_NUM, :as => :output
+```
+Now you can use the calls
+```ruby
+RPi::GPIO.set_high PIN_NUM
+RPi::GPIO.set_low PIN_NUM
+```
+to set the pin either high or low.
+
+You can use the additional hash argument `:initialize` to set the pin's initial state like so:
+```ruby
+RPi::GPIO.setup PIN_NUM, :as => :output, :initialize => :high
+# or
+RPi::GPIO.setup PIN_NUM, :as => :output, :initialize => :low
+```
+
+#### PWM (pulse-width modulation)
+
+Pulse-width modulation is a useful tool for controlling things like LED brightness or motor speed. To utilize PWM, first create a PWM object for an [output pin](#output).
+```ruby
+pwm = RPi::GPIO::PWM.new(PIN_NUM, PWM_FREQ)
+```
+The `PWM_FREQ` is a value in hertz that specifies the amount of pulse cycles per second.
+
+Now you can call the following method to start PWM:
+```ruby
+pwm.start DUTY_CYCLE
+```
+`DUTY_CYCLE` is a value from `0.0` to `100.0` indicating the percent of the time that the signal will be high.
+
+Once running, you can get/set the PWM duty cycle with
+```ruby
+pwm.duty_cycle # get
+pwm.duty_cycle = NEW_DUTY_CYCLE # set
+```
+get/set the PWM frequency with
+```ruby
+pwm.frequency # get
+pwm.frequency = NEW_FREQUENCY # set
+```
+and get the PWM GPIO number with
+```ruby
+pwm.gpio
+```
+Note that this number corresponds to `:bcm` numbering of the GPIO pins, so it will be different than pin number you used if you created the PWM with `:board` numbering.
+
+To stop PWM, use
+```ruby
+pwm.stop
+```
+
+To check if a PWM object is currently running, use
+```ruby
+pwm.running?
+```
+
+#### Cleaning up
+
+After your program is finished using the GPIO pins, it's a good idea to release them so other programs can use them later. Simply call
+```ruby
+RPi::GPIO.clean_up PIN_NUM
+```
+to release a specific pin, or
+```ruby
+RPi::GPIO.clean_up
+```
+to release all allocated pins.
+
+Alternatively, you can call
+```ruby
+RPi::GPIO.reset
+```
+to clean up all pins and to also reset the selected numbering mode.
+
+## Credits
+
+Original Python code by Ben Croston modified for Ruby by Nick Lowery
+
+Copyright (c) 2014-2020 [Nick Lowery](https://github.com/ClockVapor)
+
+View LICENSE for full license.
+

data/Rakefile

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+require 'rake/extensiontask'
+
+Rake::ExtensionTask.new('rpi_gpio')

data/ext/rpi_gpio/c_gpio.c

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+/*
+Original code by Ben Croston modified for Ruby by Nick Lowery
+(github.com/clockvapor)
+Copyright (c) 2014-2020 Nick Lowery
+
+Copyright (c) 2012-2019 Ben Croston
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+#include <string.h>
+#include "c_gpio.h"
+
+#define BCM2708_PERI_BASE_DEFAULT   0x20000000
+#define BCM2709_PERI_BASE_DEFAULT   0x3f000000
+#define GPIO_BASE_OFFSET            0x200000
+#define FSEL_OFFSET                 0   // 0x0000
+#define SET_OFFSET                  7   // 0x001c / 4
+#define CLR_OFFSET                  10  // 0x0028 / 4
+#define PINLEVEL_OFFSET             13  // 0x0034 / 4
+#define EVENT_DETECT_OFFSET         16  // 0x0040 / 4
+#define RISING_ED_OFFSET            19  // 0x004c / 4
+#define FALLING_ED_OFFSET           22  // 0x0058 / 4
+#define HIGH_DETECT_OFFSET          25  // 0x0064 / 4
+#define LOW_DETECT_OFFSET           28  // 0x0070 / 4
+#define PULLUPDN_OFFSET             37  // 0x0094 / 4
+#define PULLUPDNCLK_OFFSET          38  // 0x0098 / 4
+
+#define PULLUPDN_OFFSET_2711_0      57
+#define PULLUPDN_OFFSET_2711_1      58
+#define PULLUPDN_OFFSET_2711_2      59
+#define PULLUPDN_OFFSET_2711_3      60
+
+#define PAGE_SIZE  (4*1024)
+#define BLOCK_SIZE (4*1024)
+
+static volatile uint32_t *gpio_map;
+
+void short_wait(void)
+{
+    int i;
+
+    for (i=0; i<150; i++) {    // wait 150 cycles
+        asm volatile("nop");
+    }
+}
+
+int setup(void)
+{
+    int mem_fd;
+    uint8_t *gpio_mem;
+    uint32_t peri_base = 0;
+    uint32_t gpio_base;
+    unsigned char buf[4];
+    FILE *fp;
+    char buffer[1024];
+    char hardware[1024];
+    int found = 0;
+
+    // try /dev/gpiomem first - this does not require root privs
+    if ((mem_fd = open("/dev/gpiomem", O_RDWR|O_SYNC)) > 0)
+    {
+        if ((gpio_map = (uint32_t *)mmap(NULL, BLOCK_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, mem_fd, 0)) == MAP_FAILED) {
+            return SETUP_MMAP_FAIL;
+        } else {
+            return SETUP_OK;
+        }
+    }
+
+    // revert to /dev/mem method - requires root
+
+    // determine peri_base
+    if ((fp = fopen("/proc/device-tree/soc/ranges", "rb")) != NULL) {
+        // get peri base from device tree
+        fseek(fp, 4, SEEK_SET);
+        if (fread(buf, 1, sizeof buf, fp) == sizeof buf) {
+            peri_base = buf[0] << 24 | buf[1] << 16 | buf[2] << 8 | buf[3] << 0;
+        }
+        fclose(fp);
+    } else {
+        // guess peri base based on /proc/cpuinfo hardware field
+        if ((fp = fopen("/proc/cpuinfo", "r")) == NULL)
+            return SETUP_CPUINFO_FAIL;
+
+        while(!feof(fp) && !found && fgets(buffer, sizeof(buffer), fp)) {
+            sscanf(buffer, "Hardware	: %s", hardware);
+            if (strcmp(hardware, "BCM2708") == 0 || strcmp(hardware, "BCM2835") == 0) {
+                // pi 1 hardware
+                peri_base = BCM2708_PERI_BASE_DEFAULT;
+                found = 1;
+            } else if (strcmp(hardware, "BCM2709") == 0 || strcmp(hardware, "BCM2836") == 0) {
+                // pi 2 hardware
+                peri_base = BCM2709_PERI_BASE_DEFAULT;
+                found = 1;
+            }
+        }
+        fclose(fp);
+        if (!found)
+            return SETUP_NOT_RPI_FAIL;
+    }
+
+    if (!peri_base)
+        return SETUP_NOT_RPI_FAIL;
+    gpio_base = peri_base + GPIO_BASE_OFFSET;
+
+    // mmap the GPIO memory registers
+    if ((mem_fd = open("/dev/mem", O_RDWR|O_SYNC) ) < 0)
+        return SETUP_DEVMEM_FAIL;
+
+    if ((gpio_mem = malloc(BLOCK_SIZE + (PAGE_SIZE-1))) == NULL)
+        return SETUP_MALLOC_FAIL;
+
+    if ((uint32_t)gpio_mem % PAGE_SIZE)
+        gpio_mem += PAGE_SIZE - ((uint32_t)gpio_mem % PAGE_SIZE);
+
+    if ((gpio_map = (uint32_t *)mmap( (void *)gpio_mem, BLOCK_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED|MAP_FIXED, mem_fd, gpio_base)) == MAP_FAILED)
+        return SETUP_MMAP_FAIL;
+
+    return SETUP_OK;
+}
+
+void clear_event_detect(int gpio)
+{
+    int offset = EVENT_DETECT_OFFSET + (gpio/32);
+    int shift = (gpio%32);
+
+    *(gpio_map+offset) |= (1 << shift);
+    short_wait();
+    *(gpio_map+offset) = 0;
+}
+
+int eventdetected(int gpio)
+{
+    int offset, value, bit;
+
+    offset = EVENT_DETECT_OFFSET + (gpio/32);
+    bit = (1 << (gpio%32));
+    value = *(gpio_map+offset) & bit;
+    if (value)
+        clear_event_detect(gpio);
+    return value;
+}
+
+void set_rising_event(int gpio, int enable)
+{
+    int offset = RISING_ED_OFFSET + (gpio/32);
+    int shift = (gpio%32);
+
+    if (enable)
+        *(gpio_map+offset) |= 1 << shift;
+    else
+        *(gpio_map+offset) &= ~(1 << shift);
+    clear_event_detect(gpio);
+}
+
+void set_falling_event(int gpio, int enable)
+{
+    int offset = FALLING_ED_OFFSET + (gpio/32);
+    int shift = (gpio%32);
+
+    if (enable) {
+        *(gpio_map+offset) |= (1 << shift);
+        *(gpio_map+offset) = (1 << shift);
+    } else {
+        *(gpio_map+offset) &= ~(1 << shift);
+    }
+    clear_event_detect(gpio);
+}
+
+void set_high_event(int gpio, int enable)
+{
+    int offset = HIGH_DETECT_OFFSET + (gpio/32);
+    int shift = (gpio%32);
+
+    if (enable)
+        *(gpio_map+offset) |= (1 << shift);
+    else
+        *(gpio_map+offset) &= ~(1 << shift);
+    clear_event_detect(gpio);
+}
+
+void set_low_event(int gpio, int enable)
+{
+    int offset = LOW_DETECT_OFFSET + (gpio/32);
+    int shift = (gpio%32);
+
+    if (enable)
+        *(gpio_map+offset) |= 1 << shift;
+    else
+        *(gpio_map+offset) &= ~(1 << shift);
+    clear_event_detect(gpio);
+}
+
+void set_pullupdn(int gpio, int pud)
+{
+    // Check GPIO register
+    int is2711 = *(gpio_map+PULLUPDN_OFFSET_2711_3) != 0x6770696f;
+    if (is2711) {
+        // Pi 4 Pull-up/down method
+        int pullreg = PULLUPDN_OFFSET_2711_0 + (gpio >> 4);
+        int pullshift = (gpio & 0xf) << 1;
+        unsigned int pullbits;
+        unsigned int pull = 0;
+        switch (pud) {
+            case PUD_OFF:  pull = 0; break;
+            case PUD_UP:   pull = 1; break;
+            case PUD_DOWN: pull = 2; break;
+            default:       pull = 0; // switch PUD to OFF for other values
+        }
+        pullbits = *(gpio_map + pullreg);
+        pullbits &= ~(3 << pullshift);
+        pullbits |= (pull << pullshift);
+        *(gpio_map + pullreg) = pullbits;
+    } else {
+        // Legacy Pull-up/down method
+        int clk_offset = PULLUPDNCLK_OFFSET + (gpio/32);
+        int shift = (gpio%32);
+
+        if (pud == PUD_DOWN) {
+            *(gpio_map+PULLUPDN_OFFSET) = (*(gpio_map+PULLUPDN_OFFSET) & ~3) | PUD_DOWN;
+        } else if (pud == PUD_UP) {
+            *(gpio_map+PULLUPDN_OFFSET) = (*(gpio_map+PULLUPDN_OFFSET) & ~3) | PUD_UP;
+        } else  { // pud == PUD_OFF
+            *(gpio_map+PULLUPDN_OFFSET) &= ~3;
+        }
+        short_wait();
+        *(gpio_map+clk_offset) = 1 << shift;
+        short_wait();
+        *(gpio_map+PULLUPDN_OFFSET) &= ~3;
+        *(gpio_map+clk_offset) = 0;
+    }
+}
+
+void setup_gpio(int gpio, int direction, int pud)
+{
+    int offset = FSEL_OFFSET + (gpio/10);
+    int shift = (gpio%10)*3;
+
+    set_pullupdn(gpio, pud);
+    if (direction == OUTPUT)
+        *(gpio_map+offset) = (*(gpio_map+offset) & ~(7<<shift)) | (1<<shift);
+    else  // direction == INPUT
+        *(gpio_map+offset) = (*(gpio_map+offset) & ~(7<<shift));
+}
+
+// Contribution by Eric Ptak <trouch@trouch.com>
+int gpio_function(int gpio)
+{
+    int offset = FSEL_OFFSET + (gpio/10);
+    int shift = (gpio%10)*3;
+    int value = *(gpio_map+offset);
+    value >>= shift;
+    value &= 7;
+    return value; // 0=input, 1=output, 4=alt0
+}
+
+void output_gpio(int gpio, int value)
+{
+    int offset, shift;
+
+    if (value) // value == HIGH
+        offset = SET_OFFSET + (gpio/32);
+    else       // value == LOW
+       offset = CLR_OFFSET + (gpio/32);
+
+    shift = (gpio%32);
+
+    *(gpio_map+offset) = 1 << shift;
+}
+
+int input_gpio(int gpio)
+{
+   int offset, value, mask;
+
+   offset = PINLEVEL_OFFSET + (gpio/32);
+   mask = (1 << gpio%32);
+   value = *(gpio_map+offset) & mask;
+   return value;
+}
+
+void cleanup(void)
+{
+    munmap((void *)gpio_map, BLOCK_SIZE);
+}