rggen 0.7.1 → 0.7.2

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Files changed (8) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +2 -3
  3. data/lib/rggen/builtins/register_block/host_ifs/axi4lite.erb +1 -0
  4. data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb +3 -3
  5. data/lib/rggen/version.rb +1 -1
  6. data/rtl/rggen_axi4lite_if.sv +3 -3
  7. data/rtl/rggen_host_if_axi4lite.sv +152 -5
  8. metadata +2 -2
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data/README.md CHANGED
@@ -1,8 +1,7 @@
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  [![Gem Version](https://badge.fury.io/rb/rggen.svg)](https://badge.fury.io/rb/rggen)
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  [![Build Status](https://travis-ci.org/taichi-ishitani/rggen.svg?branch=master)](https://travis-ci.org/taichi-ishitani/rggen)
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- [![Dependency Status](https://dependencyci.com/github/taichi-ishitani/rggen/badge)](https://dependencyci.com/github/taichi-ishitani/rggen)
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- [![Code Climate](https://codeclimate.com/github/taichi-ishitani/rggen/badges/gpa.svg)](https://codeclimate.com/github/taichi-ishitani/rggen)
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- [![Test Coverage](https://codeclimate.com/github/taichi-ishitani/rggen/badges/coverage.svg)](https://codeclimate.com/github/taichi-ishitani/rggen/coverage)
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+ [![Maintainability](https://api.codeclimate.com/v1/badges/8f184e6e714a0fbdb6b0/maintainability)](https://codeclimate.com/github/taichi-ishitani/rggen/maintainability)
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+ [![codecov](https://codecov.io/gh/taichi-ishitani/rggen/branch/master/graph/badge.svg)](https://codecov.io/gh/taichi-ishitani/rggen)
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  [![Join the chat at https://gitter.im/taichi-ishitani/rggen](https://badges.gitter.im/taichi-ishitani/rggen.svg)](https://gitter.im/taichi-ishitani/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
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  # RgGen
data/lib/rggen/builtins/register_block/host_ifs/axi4lite.erb CHANGED
@@ -1,6 +1,7 @@
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  rggen_host_if_axi4lite #(
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  .LOCAL_ADDRESS_WIDTH (<%= local_address_width %>),
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  .DATA_WIDTH (<%= data_width %>),
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+ .TOTAL_REGISTERS (<%= total_registers %>),
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  .ACCESS_PRIORITY (<%= access_priority %>)
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  ) u_host_if (
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  .clk (<%= clock %>),
data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb CHANGED
@@ -11,9 +11,9 @@ list_item :register_block, :host_if, :axi4lite do
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  rtl do
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  build do
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  parameter :register_block, :access_priority,
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- name: 'ACCESS_PRIORITY',
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- type: :'rggen_rtl_pkg::rggen_direction',
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- default: :'rggen_rtl_pkg::RGGEN_WRITE'
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+ name: 'ACCESS_PRIORITY',
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+ data_type: :'rggen_rtl_pkg::rggen_direction',
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+ default: :'rggen_rtl_pkg::RGGEN_WRITE'
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  interface_port :register_block, :axi4lite_if,
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  type: :rggen_axi4lite_if,
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  modport: :slave
data/lib/rggen/version.rb CHANGED
@@ -1,6 +1,6 @@
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  module RgGen
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  MAJOR = 0
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  MINOR = 7
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- TEENY = 1
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+ TEENY = 2
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  VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
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  end
data/rtl/rggen_axi4lite_if.sv CHANGED
@@ -7,7 +7,7 @@ interface rggen_axi4lite_if #(
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  logic [ADDRESS_WIDTH-1:0] awaddr;
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  logic [2:0] awprot;
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  logic wvalid;
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- logic wraedy;
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+ logic wready;
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  logic [DATA_WIDTH-1:0] wdata;
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  logic [DATA_WIDTH/8-1:0] wstrb;
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  logic bvalid;
@@ -28,7 +28,7 @@ interface rggen_axi4lite_if #(
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  output awaddr,
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  output awprot,
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  output wvalid,
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- input wraedy,
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+ input wready,
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  output wdata,
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  output wstrb,
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  input bvalid,
@@ -50,7 +50,7 @@ interface rggen_axi4lite_if #(
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  input awaddr,
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  input awprot,
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  input wvalid,
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- output wraedy,
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+ output wready,
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  input wdata,
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  input wstrb,
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  output bvalid,
data/rtl/rggen_host_if_axi4lite.sv CHANGED
@@ -3,12 +3,159 @@ module rggen_host_if_axi4lite
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  #(
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  parameter int LOCAL_ADDRESS_WIDTH = 16,
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  parameter int DATA_WIDTH = 32,
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+ parameter int TOTAL_REGISTERS = 1,
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  parameter rggen_direction ACCESS_PRIORITY = RGGEN_WRITE
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  )(
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- input clk,
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- input rst_n,
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- rggen_axi4lite_if.slave axi4lite_if,
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- rggen_bus_if.master bus_if
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+ input logic clk,
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+ input logic rst_n,
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+ rggen_axi4lite_if.slave axi4lite_if,
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+ rggen_register_if.master register_if[TOTAL_REGISTERS]
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  );
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- // TODO
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+ typedef enum logic [4:0] {
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+ IDLE = 5'b00001,
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+ WRITE_IN_PROGRESS = 5'b00010,
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+ WAIT_FOR_BREADY = 5'b00100,
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+ READ_IN_PROGRESS = 5'b01000,
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+ WAIT_FOR_RREADY = 5'b10000
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+ } e_state;
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+
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+ rggen_bus_if #(LOCAL_ADDRESS_WIDTH, DATA_WIDTH) bus_if();
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+ e_state state;
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+
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+ //--------------------------------------------------------------
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+ // AXI4 Lite
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+ //--------------------------------------------------------------
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+ logic write_request;
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+ logic valid_write_request;
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+ logic write_request_ack;
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+ logic read_request;
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+ logic valid_read_request;
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+ logic read_request_ack;
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+ logic [DATA_WIDTH-1:0] read_data;
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+ rggen_status status;
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+
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+ assign axi4lite_if.awready = write_request_ack;
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+ assign axi4lite_if.wready = write_request_ack;
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+ assign axi4lite_if.bvalid = state[2];
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+ assign axi4lite_if.bresp = status;
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+ assign axi4lite_if.arready = read_request_ack;
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+ assign axi4lite_if.rvalid = state[4];
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+ assign axi4lite_if.rdata = read_data;
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+ assign axi4lite_if.rresp = status;
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+
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+ assign write_request = (axi4lite_if.awvalid && axi4lite_if.wvalid) ? '1 : '0;
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+ assign read_request = axi4lite_if.arvalid;
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+
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+ generate if (ACCESS_PRIORITY == RGGEN_WRITE) begin
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+ assign valid_write_request = (state[0]) ? write_request : '0;
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+ assign valid_read_request = (state[0] && (!valid_write_request)) ? read_request : '0;
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+ end
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+ else begin
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+ assign valid_write_request = (state[0] && (!valid_read_request)) ? write_request : '0;
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+ assign valid_read_request = (state[0]) ? read_request : '0;
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+ end endgenerate
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+
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+ always_ff @(posedge clk, negedge rst_n) begin
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+ if (!rst_n) begin
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+ write_request_ack <= '0;
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+ read_request_ack <= '0;
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+ end
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+ else begin
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+ write_request_ack <= valid_write_request;
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+ read_request_ack <= valid_read_request;
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+ end
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+ end
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+
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+ always_ff @(posedge clk, negedge rst_n) begin
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+ if (!rst_n) begin
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+ read_data <= '0;
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+ status <= RGGEN_OKAY;
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+ end
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+ else if ((state[1] || state[3]) && bus_if.done) begin
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+ read_data <= bus_if.read_data;
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+ status <= bus_if.status;
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+ end
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+ end
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+
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+ //--------------------------------------------------------------
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+ // Bus IF
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+ //--------------------------------------------------------------
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+ rggen_direction direction;
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+ logic [LOCAL_ADDRESS_WIDTH-1:0] address;
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+ logic [DATA_WIDTH-1:0] write_data;
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+ logic [DATA_WIDTH/8-1:0] write_strobe;
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+
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+ assign bus_if.request = (state[1] || state[3]) ? '1 : '0;
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+ assign bus_if.direction = direction;
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+ assign bus_if.address = address;
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+ assign bus_if.write_data = write_data;
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+ assign bus_if.write_strobe = write_strobe;
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+
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+ always_ff @(posedge clk, negedge rst_n) begin
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+ if (!rst_n) begin
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+ direction <= RGGEN_READ;
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+ address <= '0;
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+ write_data <= '0;
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+ write_strobe <= '0;
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+ end
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+ else if (state[0]) begin
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+ if (valid_write_request) begin
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+ direction <= RGGEN_WRITE;
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+ address <= axi4lite_if.awaddr;
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+ write_data <= axi4lite_if.wdata;
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+ write_strobe <= axi4lite_if.wstrb;
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+ end
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+ else if (valid_read_request) begin
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+ direction <= RGGEN_READ;
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+ address <= axi4lite_if.araddr;
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+ end
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+ end
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+ end
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+
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+ rggen_bus_splitter #(
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+ DATA_WIDTH, TOTAL_REGISTERS
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+ ) u_bus_splitter (
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+ clk, rst_n, bus_if, register_if
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+ );
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+
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+ //--------------------------------------------------------------
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+ // State Machine
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+ //--------------------------------------------------------------
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+ always_ff @(posedge clk, negedge rst_n) begin
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+ if (!rst_n) begin
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+ state <= IDLE;
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+ end
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+ else begin
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+ case (state)
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+ IDLE: begin
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+ if (valid_write_request) begin
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+ state <= WRITE_IN_PROGRESS;
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+ end
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+ else if (valid_read_request) begin
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+ state <= READ_IN_PROGRESS;
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+ end
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+ end
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+ WRITE_IN_PROGRESS: begin
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+ if (bus_if.write_done) begin
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+ state <= WAIT_FOR_BREADY;
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+ end
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+ end
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+ WAIT_FOR_BREADY: begin
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+ if (axi4lite_if.bready) begin
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+ state <= IDLE;
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+ end
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+ end
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+ READ_IN_PROGRESS: begin
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+ if (bus_if.read_done) begin
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+ state <= WAIT_FOR_RREADY;
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+ end
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+ end
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+ WAIT_FOR_RREADY: begin
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+ if (axi4lite_if.rready) begin
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+ state <= IDLE;
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+ end
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+ end
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+ endcase
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+ end
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+ end
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  endmodule
metadata CHANGED
@@ -1,14 +1,14 @@
1
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  --- !ruby/object:Gem::Specification
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  name: rggen
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  version: !ruby/object:Gem::Version
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- version: 0.7.1
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+ version: 0.7.2
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  platform: ruby
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  authors:
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  - Taichi Ishitani
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2018-12-20 00:00:00.000000000 Z
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+ date: 2019-01-14 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: erubi