rggen 0.7.1 → 0.7.2

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (8) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +2 -3
  3. data/lib/rggen/builtins/register_block/host_ifs/axi4lite.erb +1 -0
  4. data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb +3 -3
  5. data/lib/rggen/version.rb +1 -1
  6. data/rtl/rggen_axi4lite_if.sv +3 -3
  7. data/rtl/rggen_host_if_axi4lite.sv +152 -5
  8. metadata +2 -2
checksums.yaml CHANGED
@@ -1,7 +1,7 @@
1
1
  ---
2
2
  SHA256:
3
- metadata.gz: 7c54a20b8705880df3f42cfb91725c2a19e5eaf7a81c63a70510d3417c7d1590
4
- data.tar.gz: 3d578cabcd7397ebbfb61dfbb62f5b18e8fe40341ac499d00f7c7bc22d6c7a36
3
+ metadata.gz: d5c1f1db3a8cc427d2e94bde9851c13f2df926db959713dd2b630e7b759976b9
4
+ data.tar.gz: 722aa640d20ca719816965d83b16f5b67fafc26597c8f7b2083986e1ba24ee6e
5
5
  SHA512:
6
- metadata.gz: 35a1a1af09286d000cbb2d467b0edb391fd2d0807df34fca3f4b03d21e430ff276619edc25d146bd8c955bca327b2636af48def53971d3b41dca2bd7539d4cad
7
- data.tar.gz: 9605cb496500ddf9a913c1d5284fd64c8b2a73c3e4e228d245cb9721ed56da494116b7b0f39425fba13c2c95ab5fc30644cc49e806aa4ce7f3729f78b7c0a4d4
6
+ metadata.gz: 4c2a82e29f6dfc122ed6e29f84f5730b6cdfe2c27151734f811717ea131d46ab8753e9d59a01823525bf3ef5bd67fa78dc22e9dcad868a88585a756353fd8c4e
7
+ data.tar.gz: fc5ae08031cc4057fb74f09642bb5d636b599598bff26eb79f4a0fea0314711c7d65aeb0e598147d7569cde0b6da2aaa0f82eb9f5b34961f3e55ef7ae5830ef5
data/README.md CHANGED
@@ -1,8 +1,7 @@
1
1
  [![Gem Version](https://badge.fury.io/rb/rggen.svg)](https://badge.fury.io/rb/rggen)
2
2
  [![Build Status](https://travis-ci.org/taichi-ishitani/rggen.svg?branch=master)](https://travis-ci.org/taichi-ishitani/rggen)
3
- [![Dependency Status](https://dependencyci.com/github/taichi-ishitani/rggen/badge)](https://dependencyci.com/github/taichi-ishitani/rggen)
4
- [![Code Climate](https://codeclimate.com/github/taichi-ishitani/rggen/badges/gpa.svg)](https://codeclimate.com/github/taichi-ishitani/rggen)
5
- [![Test Coverage](https://codeclimate.com/github/taichi-ishitani/rggen/badges/coverage.svg)](https://codeclimate.com/github/taichi-ishitani/rggen/coverage)
3
+ [![Maintainability](https://api.codeclimate.com/v1/badges/8f184e6e714a0fbdb6b0/maintainability)](https://codeclimate.com/github/taichi-ishitani/rggen/maintainability)
4
+ [![codecov](https://codecov.io/gh/taichi-ishitani/rggen/branch/master/graph/badge.svg)](https://codecov.io/gh/taichi-ishitani/rggen)
6
5
  [![Join the chat at https://gitter.im/taichi-ishitani/rggen](https://badges.gitter.im/taichi-ishitani/rggen.svg)](https://gitter.im/taichi-ishitani/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
7
6
 
8
7
  # RgGen
data/lib/rggen/builtins/register_block/host_ifs/axi4lite.erb CHANGED
@@ -1,6 +1,7 @@
1
1
  rggen_host_if_axi4lite #(
2
2
  .LOCAL_ADDRESS_WIDTH (<%= local_address_width %>),
3
3
  .DATA_WIDTH (<%= data_width %>),
4
+ .TOTAL_REGISTERS (<%= total_registers %>),
4
5
  .ACCESS_PRIORITY (<%= access_priority %>)
5
6
  ) u_host_if (
6
7
  .clk (<%= clock %>),
data/lib/rggen/builtins/register_block/host_ifs/axi4lite.rb CHANGED
@@ -11,9 +11,9 @@ list_item :register_block, :host_if, :axi4lite do
11
11
  rtl do
12
12
  build do
13
13
  parameter :register_block, :access_priority,
14
- name: 'ACCESS_PRIORITY',
15
- type: :'rggen_rtl_pkg::rggen_direction',
16
- default: :'rggen_rtl_pkg::RGGEN_WRITE'
14
+ name: 'ACCESS_PRIORITY',
15
+ data_type: :'rggen_rtl_pkg::rggen_direction',
16
+ default: :'rggen_rtl_pkg::RGGEN_WRITE'
17
17
  interface_port :register_block, :axi4lite_if,
18
18
  type: :rggen_axi4lite_if,
19
19
  modport: :slave
data/lib/rggen/version.rb CHANGED
@@ -1,6 +1,6 @@
1
1
  module RgGen
2
2
  MAJOR = 0
3
3
  MINOR = 7
4
- TEENY = 1
4
+ TEENY = 2
5
5
  VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
6
6
  end
data/rtl/rggen_axi4lite_if.sv CHANGED
@@ -7,7 +7,7 @@ interface rggen_axi4lite_if #(
7
7
  logic [ADDRESS_WIDTH-1:0] awaddr;
8
8
  logic [2:0] awprot;
9
9
  logic wvalid;
10
- logic wraedy;
10
+ logic wready;
11
11
  logic [DATA_WIDTH-1:0] wdata;
12
12
  logic [DATA_WIDTH/8-1:0] wstrb;
13
13
  logic bvalid;
@@ -28,7 +28,7 @@ interface rggen_axi4lite_if #(
28
28
  output awaddr,
29
29
  output awprot,
30
30
  output wvalid,
31
- input wraedy,
31
+ input wready,
32
32
  output wdata,
33
33
  output wstrb,
34
34
  input bvalid,
@@ -50,7 +50,7 @@ interface rggen_axi4lite_if #(
50
50
  input awaddr,
51
51
  input awprot,
52
52
  input wvalid,
53
- output wraedy,
53
+ output wready,
54
54
  input wdata,
55
55
  input wstrb,
56
56
  output bvalid,
data/rtl/rggen_host_if_axi4lite.sv CHANGED
@@ -3,12 +3,159 @@ module rggen_host_if_axi4lite
3
3
  #(
4
4
  parameter int LOCAL_ADDRESS_WIDTH = 16,
5
5
  parameter int DATA_WIDTH = 32,
6
+ parameter int TOTAL_REGISTERS = 1,
6
7
  parameter rggen_direction ACCESS_PRIORITY = RGGEN_WRITE
7
8
  )(
8
- input clk,
9
- input rst_n,
10
- rggen_axi4lite_if.slave axi4lite_if,
11
- rggen_bus_if.master bus_if
9
+ input logic clk,
10
+ input logic rst_n,
11
+ rggen_axi4lite_if.slave axi4lite_if,
12
+ rggen_register_if.master register_if[TOTAL_REGISTERS]
12
13
  );
13
- // TODO
14
+ typedef enum logic [4:0] {
15
+ IDLE = 5'b00001,
16
+ WRITE_IN_PROGRESS = 5'b00010,
17
+ WAIT_FOR_BREADY = 5'b00100,
18
+ READ_IN_PROGRESS = 5'b01000,
19
+ WAIT_FOR_RREADY = 5'b10000
20
+ } e_state;
21
+
22
+ rggen_bus_if #(LOCAL_ADDRESS_WIDTH, DATA_WIDTH) bus_if();
23
+ e_state state;
24
+
25
+ //--------------------------------------------------------------
26
+ // AXI4 Lite
27
+ //--------------------------------------------------------------
28
+ logic write_request;
29
+ logic valid_write_request;
30
+ logic write_request_ack;
31
+ logic read_request;
32
+ logic valid_read_request;
33
+ logic read_request_ack;
34
+ logic [DATA_WIDTH-1:0] read_data;
35
+ rggen_status status;
36
+
37
+ assign axi4lite_if.awready = write_request_ack;
38
+ assign axi4lite_if.wready = write_request_ack;
39
+ assign axi4lite_if.bvalid = state[2];
40
+ assign axi4lite_if.bresp = status;
41
+ assign axi4lite_if.arready = read_request_ack;
42
+ assign axi4lite_if.rvalid = state[4];
43
+ assign axi4lite_if.rdata = read_data;
44
+ assign axi4lite_if.rresp = status;
45
+
46
+ assign write_request = (axi4lite_if.awvalid && axi4lite_if.wvalid) ? '1 : '0;
47
+ assign read_request = axi4lite_if.arvalid;
48
+
49
+ generate if (ACCESS_PRIORITY == RGGEN_WRITE) begin
50
+ assign valid_write_request = (state[0]) ? write_request : '0;
51
+ assign valid_read_request = (state[0] && (!valid_write_request)) ? read_request : '0;
52
+ end
53
+ else begin
54
+ assign valid_write_request = (state[0] && (!valid_read_request)) ? write_request : '0;
55
+ assign valid_read_request = (state[0]) ? read_request : '0;
56
+ end endgenerate
57
+
58
+ always_ff @(posedge clk, negedge rst_n) begin
59
+ if (!rst_n) begin
60
+ write_request_ack <= '0;
61
+ read_request_ack <= '0;
62
+ end
63
+ else begin
64
+ write_request_ack <= valid_write_request;
65
+ read_request_ack <= valid_read_request;
66
+ end
67
+ end
68
+
69
+ always_ff @(posedge clk, negedge rst_n) begin
70
+ if (!rst_n) begin
71
+ read_data <= '0;
72
+ status <= RGGEN_OKAY;
73
+ end
74
+ else if ((state[1] || state[3]) && bus_if.done) begin
75
+ read_data <= bus_if.read_data;
76
+ status <= bus_if.status;
77
+ end
78
+ end
79
+
80
+ //--------------------------------------------------------------
81
+ // Bus IF
82
+ //--------------------------------------------------------------
83
+ rggen_direction direction;
84
+ logic [LOCAL_ADDRESS_WIDTH-1:0] address;
85
+ logic [DATA_WIDTH-1:0] write_data;
86
+ logic [DATA_WIDTH/8-1:0] write_strobe;
87
+
88
+ assign bus_if.request = (state[1] || state[3]) ? '1 : '0;
89
+ assign bus_if.direction = direction;
90
+ assign bus_if.address = address;
91
+ assign bus_if.write_data = write_data;
92
+ assign bus_if.write_strobe = write_strobe;
93
+
94
+ always_ff @(posedge clk, negedge rst_n) begin
95
+ if (!rst_n) begin
96
+ direction <= RGGEN_READ;
97
+ address <= '0;
98
+ write_data <= '0;
99
+ write_strobe <= '0;
100
+ end
101
+ else if (state[0]) begin
102
+ if (valid_write_request) begin
103
+ direction <= RGGEN_WRITE;
104
+ address <= axi4lite_if.awaddr;
105
+ write_data <= axi4lite_if.wdata;
106
+ write_strobe <= axi4lite_if.wstrb;
107
+ end
108
+ else if (valid_read_request) begin
109
+ direction <= RGGEN_READ;
110
+ address <= axi4lite_if.araddr;
111
+ end
112
+ end
113
+ end
114
+
115
+ rggen_bus_splitter #(
116
+ DATA_WIDTH, TOTAL_REGISTERS
117
+ ) u_bus_splitter (
118
+ clk, rst_n, bus_if, register_if
119
+ );
120
+
121
+ //--------------------------------------------------------------
122
+ // State Machine
123
+ //--------------------------------------------------------------
124
+ always_ff @(posedge clk, negedge rst_n) begin
125
+ if (!rst_n) begin
126
+ state <= IDLE;
127
+ end
128
+ else begin
129
+ case (state)
130
+ IDLE: begin
131
+ if (valid_write_request) begin
132
+ state <= WRITE_IN_PROGRESS;
133
+ end
134
+ else if (valid_read_request) begin
135
+ state <= READ_IN_PROGRESS;
136
+ end
137
+ end
138
+ WRITE_IN_PROGRESS: begin
139
+ if (bus_if.write_done) begin
140
+ state <= WAIT_FOR_BREADY;
141
+ end
142
+ end
143
+ WAIT_FOR_BREADY: begin
144
+ if (axi4lite_if.bready) begin
145
+ state <= IDLE;
146
+ end
147
+ end
148
+ READ_IN_PROGRESS: begin
149
+ if (bus_if.read_done) begin
150
+ state <= WAIT_FOR_RREADY;
151
+ end
152
+ end
153
+ WAIT_FOR_RREADY: begin
154
+ if (axi4lite_if.rready) begin
155
+ state <= IDLE;
156
+ end
157
+ end
158
+ endcase
159
+ end
160
+ end
14
161
  endmodule
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.7.1
4
+ version: 0.7.2
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2018-12-20 00:00:00.000000000 Z
11
+ date: 2019-01-14 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: erubi