rggen 0.6.1 → 0.6.2

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checksums.yaml CHANGED
@@ -1,7 +1,7 @@
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data/README.md CHANGED
@@ -8,8 +8,8 @@
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  # RgGen
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- RgGen is a code generation tool for SoC designers.
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- It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, C header file, from its register map document.
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+ RgGen is a code generator tool for SoC/IP/FPGA/RTL engineers.
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+ It will automatically generate source code for control/status registers, e.g. RTL, UVM RAL model, C header file, from its register map document.
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  Also RgGen is customizable so you can build your specific generate tool.
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  ## Ruby
@@ -2,7 +2,16 @@ module RgGen
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  module RegisterMap
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  class GenericMap
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  class Cell
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- Position = Struct.new(:file, :sheet, :row, :column)
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+ Position = Struct.new(:file, :sheet, :row, :column) do
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+ def to_s
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+ [
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+ "file: #{file}",
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+ "sheet: #{sheet}",
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+ "row: #{row}",
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+ "column: #{column}"
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+ ].join(' ')
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+ end
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+ end
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  def initialize(file, sheet, row, column)
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  @position = Position.new(file, sheet, row, column)
@@ -10,6 +10,7 @@ require 'facets/kernel/not_nil'
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  require 'facets/method/curry' unless Method.public_method_defined?(:curry)
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  require 'facets/module/attr_class_accessor'
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  require 'facets/module/attr_setter'
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+ require 'facets/module/lastname'
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  require 'facets/numeric/positive'
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  require 'facets/object/itself' unless Object.public_method_defined?(:itself)
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  require 'facets/pathname/to_path'
@@ -5,18 +5,24 @@ module RgGen
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  class BuilderError < RgGenError
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  end
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- class LoadError < RgGenError
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+ class RuntimeError < RgGenError
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  end
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- class ConfigurationError < RgGenError
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+ class LoadError < RgGen::RuntimeError
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  end
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- class RegisterMapError < RgGenError
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- def initialize(message, position)
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+ class ConfigurationError < RgGen::RuntimeError
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+ end
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+
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+ class RegisterMapError < RgGen::RuntimeError
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+ def initialize(message, position = nil)
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  super(message)
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  @position = position
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  end
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- attr_reader :position
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+ def to_s
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+ return super.to_s unless @position
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+ "#{super.to_s} -- #{@position}"
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+ end
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  end
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  end
@@ -140,9 +140,11 @@ module RgGen
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  parse_options(argv, context)
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  load_setup(context)
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  load_configuration(context)
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- load_register_map(context, argv.first)
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+ load_register_map(context, argv)
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  write_files(context)
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  end
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+ rescue RgGen::RuntimeError, OptionParser::ParseError => e
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+ abort "[#{e.class.lastname}] #{e.message}"
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  end
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  private
@@ -167,7 +169,12 @@ module RgGen
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  end
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  def load_setup(context)
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- load(context.options[:setup])
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+ context.options[:setup].tap do |setup|
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+ File.exist?(setup) || (
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+ raise RgGen::LoadError, "cannot load such file -- #{setup}"
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+ )
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+ load(setup)
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+ end
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  end
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  def build_factory(component_name)
@@ -179,9 +186,10 @@ module RgGen
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  build_factory(:configuration).create(context.options[:configuration])
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  end
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- def load_register_map(context, file)
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+ def load_register_map(context, argv)
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+ raise RgGen::LoadError, 'no register map is specified' if argv.empty?
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  context.register_map =
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- build_factory(:register_map).create(context.configuration, file)
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+ build_factory(:register_map).create(context.configuration, argv.first)
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  end
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  def write_files(context)
@@ -45,13 +45,13 @@ module RgGen
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  end
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  def load_file(file)
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- find_loader(file).load_file(file)
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+ find_loader(file).load(file)
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  end
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  def find_loader(file)
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- loader = @loaders && @loaders.find { |l| l.acceptable?(file) }
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- return loader.new unless loader.nil?
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- fail RgGen::LoadError, "unsupported file type: #{File.ext(file)}"
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+ @loaders.find { |l| l.acceptable?(file) } || (
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+ raise RgGen::LoadError, "unsupported file type -- #{file}"
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+ )
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  end
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  end
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  end
@@ -4,10 +4,19 @@ module RgGen
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  class << self
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  attr_writer :supported_types
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- def acceptable?(file_name)
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- ext = File.ext(file_name).to_sym
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+ def acceptable?(file)
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+ ext = File.ext(file).to_sym
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  @supported_types.any? { |type| type.casecmp(ext) == 0 }
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  end
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+
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+ def load(file)
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+ new.load(file)
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+ end
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+ end
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+
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+ def load(file)
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+ return load_file(file) if File.exist?(file)
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+ raise RgGen::LoadError, "cannot load such file -- #{file}"
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  end
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  end
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  end
@@ -1,6 +1,6 @@
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  module RgGen
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  MAJOR = 0
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  MINOR = 6
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- TEENY = 1
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+ TEENY = 2
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  VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
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  end
@@ -9,29 +9,16 @@ module rggen_bus_splitter #(
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  );
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  import rggen_rtl_pkg::*;
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- localparam INDEX_WIDTH = $clog2(TOTAL_REGISTERS+1);
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+ localparam int STATUS_WIDTH = $bits(rggen_status);
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- typedef struct packed {
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- logic [DATA_WIDTH-1:0] read_data;
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- rggen_status status;
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- } s_response;
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-
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- logic [TOTAL_REGISTERS:0] select;
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- logic [TOTAL_REGISTERS:0] ready;
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- s_response response[TOTAL_REGISTERS+1];
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+ logic [TOTAL_REGISTERS-1:0] select;
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+ logic [TOTAL_REGISTERS-1:0] ready;
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  logic response_ready;
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- logic no_register_selected;
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+ logic register_selected;
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  logic done;
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- logic read_done;
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- logic write_done;
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- s_response selected_response;
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- genvar g_i;
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-
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- assign bus_if.done = done;
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- assign bus_if.read_done = read_done;
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- assign bus_if.write_done = write_done;
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- assign bus_if.read_data = selected_response.read_data;
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- assign bus_if.status = selected_response.status;
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+ logic [DATA_WIDTH-1:0] selected_read_data;
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+ rggen_status selected_status;
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+ genvar g_i, g_j;
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  generate for (g_i = 0;g_i < TOTAL_REGISTERS;++g_i) begin : g
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  assign register_if[g_i].request = bus_if.request;
@@ -41,47 +28,59 @@ module rggen_bus_splitter #(
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  assign register_if[g_i].write_strobe = bus_if.write_strobe;
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  assign select[g_i] = register_if[g_i].select;
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  assign ready[g_i] = register_if[g_i].ready;
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- assign response[g_i].read_data = register_if[g_i].read_data;
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- assign response[g_i].status = register_if[g_i].status;
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  end endgenerate
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- // dummy response
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- assign no_register_selected = ~|select[TOTAL_REGISTERS-1:0];
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- assign select[TOTAL_REGISTERS] = no_register_selected;
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- assign ready[TOTAL_REGISTERS] = no_register_selected;
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- assign response[TOTAL_REGISTERS] = '{read_data: '0, status: RGGEN_SLAVE_ERROR};
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-
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- assign response_ready = |ready;
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+ assign bus_if.done = done;
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+ assign response_ready = |ready;
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+ assign register_selected = |select;
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  always_ff @(posedge clk, negedge rst_n) begin
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  if (!rst_n) begin
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  done <= '0;
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- read_done <= '0;
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- write_done <= '0;
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- selected_response <= '{read_data: '0, status: RGGEN_OKAY};
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+ bus_if.read_done <= '0;
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+ bus_if.write_done <= '0;
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+ bus_if.read_data <= '0;
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+ bus_if.status <= RGGEN_OKAY;
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  end
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- else if (bus_if.request && response_ready && (!done)) begin
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+ else if (bus_if.request && (response_ready || (!register_selected)) && (!done)) begin
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  done <= '1;
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- write_done <= (bus_if.direction == RGGEN_WRITE) ? '1 : '0;
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- read_done <= (bus_if.direction == RGGEN_READ ) ? '1 : '0;
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- selected_response <= response[calc_index()];
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+ bus_if.read_done <= (bus_if.direction == RGGEN_READ ) ? '1 : '0;
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+ bus_if.write_done <= (bus_if.direction == RGGEN_WRITE) ? '1 : '0;
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+ if (register_selected) begin
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+ bus_if.read_data <= selected_read_data;
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+ bus_if.status <= selected_status;
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+ end
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+ else begin
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+ bus_if.read_data <= '0;
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+ bus_if.status <= RGGEN_SLAVE_ERROR;
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+ end
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  end
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  else begin
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  done <= '0;
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- read_done <= '0;
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- write_done <= '0;
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- selected_response <= '{read_data: '0, status: RGGEN_OKAY};
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+ bus_if.read_done <= '0;
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+ bus_if.write_done <= '0;
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+ bus_if.read_data <= '0;
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+ bus_if.status <= RGGEN_OKAY;
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  end
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  end
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- function automatic logic [INDEX_WIDTH-1:0] calc_index();
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- logic [INDEX_WIDTH-1:0] index;
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- for (int i = 0;i < INDEX_WIDTH;++i) begin
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- logic [TOTAL_REGISTERS:0] temp;
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- for (int j = 0;j <= TOTAL_REGISTERS;++j) begin
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- temp[j] = j[i] & select[j];
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+ // Response Selection
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+ generate if (1) begin : read_data_selection
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+ for (g_i = 0;g_i < DATA_WIDTH;++g_i) begin : g
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+ logic [TOTAL_REGISTERS-1:0] temp;
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+ assign selected_read_data[g_i] = |temp;
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+ for (g_j = 0;g_j < TOTAL_REGISTERS;++g_j) begin : g
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+ assign temp[g_j] = register_if[g_j].read_data[g_i] & register_if[g_j].select;
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+ end
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+ end
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+ end endgenerate
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+
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+ generate if (1) begin : status_selection
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+ for (g_i = 0;g_i < STATUS_WIDTH;++g_i) begin : g
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+ logic [TOTAL_REGISTERS-1:0] temp;
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+ assign selected_status[g_i] = |temp;
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+ for (g_j = 0;g_j < TOTAL_REGISTERS;++g_j) begin : g
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+ assign temp[g_j] = register_if[g_j].status[g_i] & register_if[g_j].select;
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83
  end
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- index[i] = |temp;
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84
  end
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- return index;
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- endfunction
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+ end endgenerate
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  endmodule
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: rggen
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  version: !ruby/object:Gem::Version
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- version: 0.6.1
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+ version: 0.6.2
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  platform: ruby
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  authors:
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  - Taichi Ishitani
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2017-05-31 00:00:00.000000000 Z
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+ date: 2017-06-02 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: baby_erubis