rggen 0.6.1 → 0.6.2
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- checksums.yaml +4 -4
- data/README.md +2 -2
- data/lib/rggen/core_components/register_map/generic_map.rb +10 -1
- data/lib/rggen/core_extensions/facets.rb +1 -0
- data/lib/rggen/exceptions.rb +11 -5
- data/lib/rggen/generator.rb +12 -4
- data/lib/rggen/input_base/component_factory.rb +4 -4
- data/lib/rggen/input_base/loader.rb +11 -2
- data/lib/rggen/version.rb +1 -1
- data/rtl/rggen_bus_splitter.sv +47 -48
- metadata +2 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA1:
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-
metadata.gz:
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-
data.tar.gz:
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3
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metadata.gz: 19195a9804097d391d2ee4c629922ef49a1d1d82
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4
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data.tar.gz: 7052fa9b494b2948f452649797f5280bef883af2
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 59827fbc8e93f033570dd65f7bfaaeb0123c977bc095d0b7d835c80b2f21f263058b880408fc840ed8a7a1da77e05da4e40884462526ade82824336d3ede4014
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7
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+
data.tar.gz: f31b881ee297b1915fbfe6b60266b8eed027f73d7eb2f0161fe3fb15bddc2a5df4c64304051b2964d3dee59664abe3a0c52e158f2078014f5e498b9cae197a0d
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data/README.md
CHANGED
@@ -8,8 +8,8 @@
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9
9
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# RgGen
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10
10
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|
11
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-
RgGen is a code
|
12
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-
It will automatically generate source code for control registers
|
11
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+
RgGen is a code generator tool for SoC/IP/FPGA/RTL engineers.
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12
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+
It will automatically generate source code for control/status registers, e.g. RTL, UVM RAL model, C header file, from its register map document.
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Also RgGen is customizable so you can build your specific generate tool.
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## Ruby
|
@@ -2,7 +2,16 @@ module RgGen
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module RegisterMap
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3
3
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class GenericMap
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4
4
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class Cell
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5
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-
Position = Struct.new(:file, :sheet, :row, :column)
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5
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+
Position = Struct.new(:file, :sheet, :row, :column) do
|
6
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+
def to_s
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7
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+
[
|
8
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+
"file: #{file}",
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9
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"sheet: #{sheet}",
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10
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"row: #{row}",
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11
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"column: #{column}"
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].join(' ')
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13
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end
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14
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end
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6
15
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7
16
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def initialize(file, sheet, row, column)
|
8
17
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@position = Position.new(file, sheet, row, column)
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@@ -10,6 +10,7 @@ require 'facets/kernel/not_nil'
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10
10
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require 'facets/method/curry' unless Method.public_method_defined?(:curry)
|
11
11
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require 'facets/module/attr_class_accessor'
|
12
12
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require 'facets/module/attr_setter'
|
13
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+
require 'facets/module/lastname'
|
13
14
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require 'facets/numeric/positive'
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14
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require 'facets/object/itself' unless Object.public_method_defined?(:itself)
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require 'facets/pathname/to_path'
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data/lib/rggen/exceptions.rb
CHANGED
@@ -5,18 +5,24 @@ module RgGen
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5
5
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class BuilderError < RgGenError
|
6
6
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end
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7
7
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|
8
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-
class
|
8
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+
class RuntimeError < RgGenError
|
9
9
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end
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10
10
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|
11
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-
class
|
11
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+
class LoadError < RgGen::RuntimeError
|
12
12
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end
|
13
13
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|
14
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-
class
|
15
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-
|
14
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+
class ConfigurationError < RgGen::RuntimeError
|
15
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+
end
|
16
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+
|
17
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+
class RegisterMapError < RgGen::RuntimeError
|
18
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+
def initialize(message, position = nil)
|
16
19
|
super(message)
|
17
20
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@position = position
|
18
21
|
end
|
19
22
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|
20
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-
|
23
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+
def to_s
|
24
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+
return super.to_s unless @position
|
25
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+
"#{super.to_s} -- #{@position}"
|
26
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+
end
|
21
27
|
end
|
22
28
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end
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data/lib/rggen/generator.rb
CHANGED
@@ -140,9 +140,11 @@ module RgGen
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|
140
140
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parse_options(argv, context)
|
141
141
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load_setup(context)
|
142
142
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load_configuration(context)
|
143
|
-
load_register_map(context, argv
|
143
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+
load_register_map(context, argv)
|
144
144
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write_files(context)
|
145
145
|
end
|
146
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+
rescue RgGen::RuntimeError, OptionParser::ParseError => e
|
147
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+
abort "[#{e.class.lastname}] #{e.message}"
|
146
148
|
end
|
147
149
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|
148
150
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private
|
@@ -167,7 +169,12 @@ module RgGen
|
|
167
169
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end
|
168
170
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|
169
171
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def load_setup(context)
|
170
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-
|
172
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+
context.options[:setup].tap do |setup|
|
173
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+
File.exist?(setup) || (
|
174
|
+
raise RgGen::LoadError, "cannot load such file -- #{setup}"
|
175
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+
)
|
176
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+
load(setup)
|
177
|
+
end
|
171
178
|
end
|
172
179
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|
173
180
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def build_factory(component_name)
|
@@ -179,9 +186,10 @@ module RgGen
|
|
179
186
|
build_factory(:configuration).create(context.options[:configuration])
|
180
187
|
end
|
181
188
|
|
182
|
-
def load_register_map(context,
|
189
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+
def load_register_map(context, argv)
|
190
|
+
raise RgGen::LoadError, 'no register map is specified' if argv.empty?
|
183
191
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context.register_map =
|
184
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-
build_factory(:register_map).create(context.configuration,
|
192
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+
build_factory(:register_map).create(context.configuration, argv.first)
|
185
193
|
end
|
186
194
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|
187
195
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def write_files(context)
|
@@ -45,13 +45,13 @@ module RgGen
|
|
45
45
|
end
|
46
46
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|
47
47
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def load_file(file)
|
48
|
-
find_loader(file).
|
48
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+
find_loader(file).load(file)
|
49
49
|
end
|
50
50
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|
51
51
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def find_loader(file)
|
52
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-
|
53
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-
|
54
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-
|
52
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+
@loaders.find { |l| l.acceptable?(file) } || (
|
53
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+
raise RgGen::LoadError, "unsupported file type -- #{file}"
|
54
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+
)
|
55
55
|
end
|
56
56
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end
|
57
57
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end
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@@ -4,10 +4,19 @@ module RgGen
|
|
4
4
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class << self
|
5
5
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attr_writer :supported_types
|
6
6
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|
7
|
-
def acceptable?(
|
8
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-
ext = File.ext(
|
7
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+
def acceptable?(file)
|
8
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+
ext = File.ext(file).to_sym
|
9
9
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@supported_types.any? { |type| type.casecmp(ext) == 0 }
|
10
10
|
end
|
11
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+
|
12
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+
def load(file)
|
13
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new.load(file)
|
14
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+
end
|
15
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+
end
|
16
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+
|
17
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+
def load(file)
|
18
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+
return load_file(file) if File.exist?(file)
|
19
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+
raise RgGen::LoadError, "cannot load such file -- #{file}"
|
11
20
|
end
|
12
21
|
end
|
13
22
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end
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data/lib/rggen/version.rb
CHANGED
data/rtl/rggen_bus_splitter.sv
CHANGED
@@ -9,29 +9,16 @@ module rggen_bus_splitter #(
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9
9
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);
|
10
10
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import rggen_rtl_pkg::*;
|
11
11
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12
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-
localparam
|
12
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+
localparam int STATUS_WIDTH = $bits(rggen_status);
|
13
13
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|
14
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-
|
15
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-
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16
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-
rggen_status status;
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17
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-
} s_response;
|
18
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-
|
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-
logic [TOTAL_REGISTERS:0] select;
|
20
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-
logic [TOTAL_REGISTERS:0] ready;
|
21
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-
s_response response[TOTAL_REGISTERS+1];
|
14
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+
logic [TOTAL_REGISTERS-1:0] select;
|
15
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logic [TOTAL_REGISTERS-1:0] ready;
|
22
16
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logic response_ready;
|
23
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-
logic
|
17
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+
logic register_selected;
|
24
18
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logic done;
|
25
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-
logic
|
26
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-
|
27
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-
|
28
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-
genvar g_i;
|
29
|
-
|
30
|
-
assign bus_if.done = done;
|
31
|
-
assign bus_if.read_done = read_done;
|
32
|
-
assign bus_if.write_done = write_done;
|
33
|
-
assign bus_if.read_data = selected_response.read_data;
|
34
|
-
assign bus_if.status = selected_response.status;
|
19
|
+
logic [DATA_WIDTH-1:0] selected_read_data;
|
20
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+
rggen_status selected_status;
|
21
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+
genvar g_i, g_j;
|
35
22
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|
36
23
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generate for (g_i = 0;g_i < TOTAL_REGISTERS;++g_i) begin : g
|
37
24
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assign register_if[g_i].request = bus_if.request;
|
@@ -41,47 +28,59 @@ module rggen_bus_splitter #(
|
|
41
28
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assign register_if[g_i].write_strobe = bus_if.write_strobe;
|
42
29
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assign select[g_i] = register_if[g_i].select;
|
43
30
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assign ready[g_i] = register_if[g_i].ready;
|
44
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-
assign response[g_i].read_data = register_if[g_i].read_data;
|
45
|
-
assign response[g_i].status = register_if[g_i].status;
|
46
31
|
end endgenerate
|
47
32
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|
48
|
-
|
49
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-
assign
|
50
|
-
assign
|
51
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-
assign ready[TOTAL_REGISTERS] = no_register_selected;
|
52
|
-
assign response[TOTAL_REGISTERS] = '{read_data: '0, status: RGGEN_SLAVE_ERROR};
|
53
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-
|
54
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-
assign response_ready = |ready;
|
33
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+
assign bus_if.done = done;
|
34
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assign response_ready = |ready;
|
35
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+
assign register_selected = |select;
|
55
36
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always_ff @(posedge clk, negedge rst_n) begin
|
56
37
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if (!rst_n) begin
|
57
38
|
done <= '0;
|
58
|
-
read_done
|
59
|
-
write_done
|
60
|
-
|
39
|
+
bus_if.read_done <= '0;
|
40
|
+
bus_if.write_done <= '0;
|
41
|
+
bus_if.read_data <= '0;
|
42
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+
bus_if.status <= RGGEN_OKAY;
|
61
43
|
end
|
62
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-
else if (bus_if.request && response_ready && (!done)) begin
|
44
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+
else if (bus_if.request && (response_ready || (!register_selected)) && (!done)) begin
|
63
45
|
done <= '1;
|
64
|
-
|
65
|
-
|
66
|
-
|
46
|
+
bus_if.read_done <= (bus_if.direction == RGGEN_READ ) ? '1 : '0;
|
47
|
+
bus_if.write_done <= (bus_if.direction == RGGEN_WRITE) ? '1 : '0;
|
48
|
+
if (register_selected) begin
|
49
|
+
bus_if.read_data <= selected_read_data;
|
50
|
+
bus_if.status <= selected_status;
|
51
|
+
end
|
52
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+
else begin
|
53
|
+
bus_if.read_data <= '0;
|
54
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+
bus_if.status <= RGGEN_SLAVE_ERROR;
|
55
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+
end
|
67
56
|
end
|
68
57
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else begin
|
69
58
|
done <= '0;
|
70
|
-
read_done
|
71
|
-
write_done
|
72
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-
|
59
|
+
bus_if.read_done <= '0;
|
60
|
+
bus_if.write_done <= '0;
|
61
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+
bus_if.read_data <= '0;
|
62
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+
bus_if.status <= RGGEN_OKAY;
|
73
63
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end
|
74
64
|
end
|
75
65
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|
76
|
-
|
77
|
-
|
78
|
-
for (
|
79
|
-
logic [TOTAL_REGISTERS:0] temp;
|
80
|
-
|
81
|
-
|
66
|
+
// Response Selection
|
67
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+
generate if (1) begin : read_data_selection
|
68
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+
for (g_i = 0;g_i < DATA_WIDTH;++g_i) begin : g
|
69
|
+
logic [TOTAL_REGISTERS-1:0] temp;
|
70
|
+
assign selected_read_data[g_i] = |temp;
|
71
|
+
for (g_j = 0;g_j < TOTAL_REGISTERS;++g_j) begin : g
|
72
|
+
assign temp[g_j] = register_if[g_j].read_data[g_i] & register_if[g_j].select;
|
73
|
+
end
|
74
|
+
end
|
75
|
+
end endgenerate
|
76
|
+
|
77
|
+
generate if (1) begin : status_selection
|
78
|
+
for (g_i = 0;g_i < STATUS_WIDTH;++g_i) begin : g
|
79
|
+
logic [TOTAL_REGISTERS-1:0] temp;
|
80
|
+
assign selected_status[g_i] = |temp;
|
81
|
+
for (g_j = 0;g_j < TOTAL_REGISTERS;++g_j) begin : g
|
82
|
+
assign temp[g_j] = register_if[g_j].status[g_i] & register_if[g_j].select;
|
82
83
|
end
|
83
|
-
index[i] = |temp;
|
84
84
|
end
|
85
|
-
|
86
|
-
endfunction
|
85
|
+
end endgenerate
|
87
86
|
endmodule
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: rggen
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.6.
|
4
|
+
version: 0.6.2
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Taichi Ishitani
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date: 2017-
|
11
|
+
date: 2017-06-02 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: baby_erubis
|