rggen 0.33.3 → 0.34.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 9a8a3395b42669e670ad735557574882fdebfc82c05150e1d907fbc0cc9ba486
-  data.tar.gz: 2cb62bcb274010a9a0a71cf34b8dd12bafa72a7f383191045d418ba716481315
+  metadata.gz: b0a434b9c6cf22b9887224b337c03d238866bef6f1410fb4f730e46283545e1d
+  data.tar.gz: 377ca51eb31e196aa16938a1a85cad32a97629a9cf688dbd6ff8bb8563fc7901
 SHA512:
-  metadata.gz: 14686d40e0696b6c771bfcd1b444f8e739a0c02e9a8d87ba413c4e5cf76497dcf7772551f29845de6fc5bbb24ad252776df5fb7516730f47b81316bd0017fc9d
-  data.tar.gz: 81c2d4e4878025e2c4ef20a4b600b1a17aa6d6df50dab6fc6f0e3f1f65ce2d23f883ad6e1d58b1b4b3b16e768dd3fc0bad561407490881c45571f642b6e3dd09
+  metadata.gz: b1e367fc5c3e24bbd725b5411779fc3368347e0549399288326a14a4e5b179fc1201371ebd749cfd831a01529795c88fa9aa412a722b048e95ee7e205710e758
+  data.tar.gz: 5d5277a109d56e2c3c7b0847bf3b7760e19741808187d02b08d299b315d3db00fbbafb2481abdc3f9b71d224addbad0a4db6809a3262c0b3cb3a775b45779847

data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2024 Taichi Ishitani
+Copyright (c) 2019-2025 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -19,6 +19,8 @@ RgGen has following features:
         * SystemVerilog
         * Verilog
             * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
+        * [Veryl](https://veryl-lang.org)
+            * Need [rggen-veryl](https://github.com/rggen/rggen-veryl) plugin
         * VHDL
             * Need [rggen-vhdl](https://github.com/rggen/rggen-vhdl) plugin
         * Supports standard bus protocols
@@ -45,7 +47,7 @@ RgGen has following features:
 
 ### Ruby
 
-RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 3.0 or later. You need to install  any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/documentation/installation/).
+RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 3.1 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/documentation/installation/).
 
 ### Installatin Command
 
@@ -112,7 +114,7 @@ Following EDA tools can accept the generated source files.
     * Synopsys VCS
     * Cadence Xcelium
     * Metrics DSim
-    * Xilinx Vivado Simulator
+    * AMD Vivado Simulator
     * Verilator
         * Need `-Wno-unoptflat` switch for Verilog RTL
     * Icarus Verilog
@@ -120,7 +122,7 @@ Following EDA tools can accept the generated source files.
 * Synthesis tools
     * Synopsys Design Compiler
     * Intel Quartus
-    * Xilinx Vivado
+    * AMD Vivado
     * [Yosys](http://www.clifford.at/yosys/)
         * Verilog RTL
 
@@ -145,20 +147,22 @@ $ rggen -c config.yml -o out uart_csr.yml
 
 Then, generated files will be written to the `out` directory.
 
-If you want to generate Verilog RTL and/or VHDL RTL then you need to instll optional plugins listed below.
+If you want to generate Verilog RTL, Veryl RTL and VHDL RTL then you need to instll optional plugins listed below.
 
 * Verilog writer plugin: [rggen-verilog](https://github.com/rggen/rggen-verilog)
+* Veryl writer plugin: [rggen-veryl](https://github.com/rggen/rggen-veryl)
 * VHDL writer plugin: [rggen-vhdl](https://github.com/rggen/rggen-vhdl)
 
 ```
 $ gem install rggen-verilog
+$ gem install rggen-veryl
 $ gem install rggen-vhdl
 ```
 
 In addition, you need to tell RgGen to use these plugins by using the `--plugin` option switch:
 
 ```
-rggen -c config.yml --plugin rggen-verilog --plugin rggen-vhdl uart_csr.yml
+$ rggen -c config.yml --plugin rggen-verilog --plugin rggen-veryl --plugin rggen-vhdl uart_csr.yml
 ```
 
 RgGen will generate following source files from the [`uart_csr.yml`](https://github.com/rggen/rggen-sample/blob/master/uart_csr.yml) register map specification:
@@ -169,6 +173,8 @@ RgGen will generate following source files from the [`uart_csr.yml`](https://git
 * Verilog RTL
     * https://github.com/rggen/rggen-sample/blob/master/uart_csr.v
     * https://github.com/rggen/rggen-sample/blob/master/uart_csr.vh
+* Veryl RTL
+    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.veryl
 * VHDL RTL
     * https://github.com/rggen/rggen-sample/blob/master/uart_csr.vhd
 * UVM register model
@@ -202,12 +208,13 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 * https://github.com/rggen/rggen-spreadsheet-loader
 * https://github.com/rggen/rggen-duh
 * https://github.com/rggen/rggen-verilog
+* https://github.com/rggen/rggen-veryl
 * https://github.com/rggen/rggen-vhdl
 * https://github.com/rggen/rggen-docker
 
 ## Copyright & License
 
-Copyright © 2019-2024 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
+Copyright © 2019-2025 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
 
 ## Code of Conduct
 

data/lib/rggen/default.rb

@@ -6,3 +6,10 @@ RgGen.load_plugin 'rggen-systemverilog/ral'
 RgGen.load_plugin 'rggen-c-header'
 RgGen.load_plugin 'rggen-markdown'
 RgGen.load_plugin 'rggen-spreadsheet-loader'
+
+RgGen.update_plugin :'rggen-spreadsheet-loader' do |plugin|
+  plugin.setup_loader :register_map, :spreadsheet do |entry|
+    entry.ignore_value :register_block, :comment
+    entry.ignore_value :register, :comment
+  end
+end

data/lib/rggen/version.rb

@@ -1,5 +1,5 @@
 # frozen_string_literal: true
 
 module RgGen
-  VERSION = '0.33.3'
+  VERSION = '0.34.0'
 end

metadata

@@ -1,14 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.33.3
+  version: 0.34.0
 platform: ruby
 authors:
 - Taichi Ishitani
-autorequire: 
 bindir: bin
 cert_chain: []
-date: 2024-07-20 00:00:00.000000000 Z
+date: 2025-01-23 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-c-header
@@ -16,84 +15,84 @@ dependencies:
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.5.0
+        version: 0.6.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.5.0
+        version: 0.6.0
 - !ruby/object:Gem::Dependency
   name: rggen-core
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.33.1
+        version: 0.34.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.33.1
+        version: 0.34.0
 - !ruby/object:Gem::Dependency
   name: rggen-default-register-map
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.33.1
+        version: 0.34.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.33.1
+        version: 0.34.0
 - !ruby/object:Gem::Dependency
   name: rggen-markdown
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.26.0
+        version: 0.27.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.26.0
+        version: 0.27.0
 - !ruby/object:Gem::Dependency
   name: rggen-spreadsheet-loader
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.25.3
+        version: 0.26.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.25.3
+        version: 0.26.0
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.33.0
+        version: 0.34.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.33.0
+        version: 0.34.0
 description: |
   RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
   It will automatically generate source code related to control and status registers (CSR),
@@ -121,7 +120,6 @@ metadata:
   rubygems_mfa_required: 'true'
   source_code_uri: https://github.com/rggen/rggen
   wiki_uri: https://github.com/rggen/rggen/wiki
-post_install_message: 
 rdoc_options: []
 require_paths:
 - lib
@@ -129,15 +127,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '3.0'
+      version: '3.1'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.5.5
-signing_key: 
+rubygems_version: 3.6.2
 specification_version: 4
 summary: Code generation tool for control and status registers
 test_files: []