rggen 0.33.1 → 0.33.3

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -10,7 +10,7 @@
 
 # RgGen
 
-RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL/uvm_reg), C header file, Wiki documents, from human readable register map specifications.
+RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to control and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL/uvm_reg), C header file, Wiki documents, from human readable register map specifications.
 
 RgGen has following features:
 
@@ -33,11 +33,13 @@ RgGen has following features:
     * YAML
     * JSON
     * TOML
-    * Spreadsheet (XLSX, XLS, ODS, CSV)
+    * Spreadsheet (XLSX, ODS, CSV)
     * [SiFive DUH](https://github.com/sifive/duh)
         * Need [rggen-duh](https://github.com/rggen/rggen-duh) plugin
-* Customize RgGen for you environment
-    * E.g. add special bit field types
+* Plugin feature
+    * Allow you to customize RgGen for your environment
+        * Add your own special bit field types
+        * Add your own host bus protocol
 
 ## Installation
 
@@ -64,11 +66,12 @@ $ gem install rggen
 
 RgGen and dependencies will be installed on your system root.
 
-If you want to install them on other location, you need to specify install path and set the `GEM_PATH` environment variable:
+If you want to install them on other location, you need to specify install path and set `GEM_PATH` and `PATH` environment variables:
 
 ```
-$ gem install --install-dir YOUR_INSTALL_DIRECTORY rggen
-$ export GEM_PATH=YOUR_INSTALL_DIRECTORY
+$ gem install --install-dir /path/to/your/install/directory rggen
+$ export GEM_PATH=/path/to/your/install/directory
+$ export PATH=$GEM_PATH/bin:$PATH
 ```
 
 You would get the following error message duaring installation if you have the old RgGen (version < 0.9).
@@ -108,6 +111,7 @@ Following EDA tools can accept the generated source files.
 * Simulation tools
     * Synopsys VCS
     * Cadence Xcelium
+    * Metrics DSim
     * Xilinx Vivado Simulator
     * Verilator
         * Need `-Wno-unoptflat` switch for Verilog RTL

data/lib/rggen/version.rb

@@ -1,5 +1,5 @@
 # frozen_string_literal: true
 
 module RgGen
-  VERSION = '0.33.1'
+  VERSION = '0.33.3'
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.33.1
+  version: 0.33.3
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2024-01-23 00:00:00.000000000 Z
+date: 2024-07-20 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-c-header
@@ -30,28 +30,28 @@ dependencies:
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.33.0
+        version: 0.33.1
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.33.0
+        version: 0.33.1
 - !ruby/object:Gem::Dependency
   name: rggen-default-register-map
   requirement: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.33.0
+        version: 0.33.1
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.33.0
+        version: 0.33.1
 - !ruby/object:Gem::Dependency
   name: rggen-markdown
   requirement: !ruby/object:Gem::Requirement
@@ -72,14 +72,14 @@ dependencies:
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.25.2
+        version: 0.25.3
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.25.2
+        version: 0.25.3
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
   requirement: !ruby/object:Gem::Requirement
@@ -96,7 +96,7 @@ dependencies:
         version: 0.33.0
 description: |
   RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
-  It will automatically generate source code related to configuration and status registers (CSR),
+  It will automatically generate source code related to control and status registers (CSR),
   e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
 email:
 - rggen@googlegroups.com
@@ -139,5 +139,5 @@ requirements: []
 rubygems_version: 3.5.5
 signing_key: 
 specification_version: 4
-summary: Code generation tool for configuration and status registers
+summary: Code generation tool for control and status registers
 test_files: []