rggen 0.30.0 → 0.30.2

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -82,6 +82,17 @@ ERROR:  Error installing rggen:
 To resolve the above error, there are three solutions.
 See [this page](https://github.com/rggen/rggen/wiki/Resolve-Confliction-of-Installed-Executable)
 
+### Docker Image
+
+The [rggen-docker](https://hub.docker.com/r/rggendev/rggen-docker) is a Docker image to simplify installation and use of RgGen.
+You can also execute RgGen by using this image:
+
+```
+$ docker run -ti --rm -v ${PWD}:/work --user $(id -u):$(id -g) rggendev/rggen-docker:latest -c config.yml -o out block_0.yml
+```
+
+See the [rggen-docker repository](https://github.com/rggen/rggen-docker) for further details.
+
 ## Usage
 
 See [Wiki documents](https://github.com/rggen/rggen/wiki).
@@ -100,7 +111,7 @@ Following EDA tools can accept the generated source files.
     * Cadence Xcelium
     * Xilinx Vivado Simulator
     * Verilator
-        * Need `-Wno-fatal` switch
+        * Need `-Wno-unoptflat` switch for Verilog RTL
     * Icarus Verilog
         * Verilog RTL only
 * Synthesis tools
@@ -112,39 +123,57 @@ Following EDA tools can accept the generated source files.
 
 ## Example
 
-You can get an example configuration file and register map specifications listed below:
+You can get sample configuration file and register map specification from the [rggen-sample](https://github.com/rggen/rggen-sample) repository.
+This register map specification is for a UART IP.
 
 * Configuration file
     * https://github.com/rggen/rggen-sample/blob/master/config.yml
-* Register map specifications
-    * https://github.com/rggen/rggen-sample/blob/master/block_0.yml
-    * https://github.com/rggen/rggen-sample/blob/master/block_1.yml
+* Register map specification
+    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.yml
 
 You can try to use RgGen by uisng these example files. Hit command below:
 
 ```
-$ rggen -c config.yml -o out block_0.yml block_1.yml
+$ rggen -c config.yml -o out uart_csr.yml
 ```
 
 * `-c`: Specify path to your configuration file
 * `-o`: Specify path to the directory where generated files will be written to
 
-Then, generated files listed below will be written to `out` directory.
+Then, generated files will be written to the `out` directory.
+
+If you want to generate Verilog RTL and/or VHDL RTL then you need to instll optional plugins listed below.
+
+* Verilog writer plugin: [rggen-verilog](https://github.com/rggen/rggen-verilog)
+* VHDL writer plugin: [rggen-vhdl](https://github.com/rggen/rggen-vhdl)
+
+```
+$ gem install rggen-verilog
+$ gem install rggen-vhdl
+```
+
+In addition, you need to tell RgGen to use these plugins by using the `--plugin` option switch:
+
+```
+rggen -c config.yml --plugin rggen-verilog --plugin rggen-vhdl uart_csr.yml
+```
+
+RgGen will generate following source files from the [`uart_csr.yml`](https://github.com/rggen/rggen-sample/blob/master/uart_csr.yml) register map specification:
 
 * SystemVerilog RTL
-    * https://github.com/rggen/rggen-sample/blob/master/block_0.sv
-    * https://github.com/rggen/rggen-sample/blob/master/block_0_rtl_pkg.sv
-    * https://github.com/rggen/rggen-sample/blob/master/block_1.sv
-    * https://github.com/rggen/rggen-sample/blob/master/block_1_rtl_pkg.sv
+    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.sv
+    * https://github.com/rggen/rggen-sample/blob/master/uart_csr_rtl_pkg.sv
+* Verilog RTL
+    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.v
+    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.vh 
+* VHDL RTL
+    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.vhd 
 * UVM register model
-    * https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv
-    * https://github.com/rggen/rggen-sample/blob/master/block_1_ral_pkg.sv
+    * https://github.com/rggen/rggen-sample/blob/master/uart_csr_ral_pkg.sv
 * C header file
-    * https://github.com/rggen/rggen-sample/blob/master/block_0.h
-    * https://github.com/rggen/rggen-sample/blob/master/block_1.h
+    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.h
 * Markdown document
-    * https://github.com/rggen/rggen-sample/blob/master/block_0.md
-    * https://github.com/rggen/rggen-sample/blob/master/block_1.md
+    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.md
 
 ## Contributing
 
@@ -171,6 +200,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 * https://github.com/rggen/rggen-duh
 * https://github.com/rggen/rggen-verilog
 * https://github.com/rggen/rggen-vhdl
+* https://github.com/rggen/rggen-docker
 
 ## Copyright & License
 

data/lib/rggen/version.rb

@@ -1,5 +1,5 @@
 # frozen_string_literal: true
 
 module RgGen
-  VERSION = '0.30.0'
+  VERSION = '0.30.2'
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.30.0
+  version: 0.30.2
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-04-28 00:00:00.000000000 Z
+date: 2023-08-08 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-c-header
@@ -86,14 +86,14 @@ dependencies:
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.30.0
+        version: 0.30.2
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.30.0
+        version: 0.30.2
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -150,7 +150,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.4.10
+rubygems_version: 3.4.17
 signing_key: 
 specification_version: 4
 summary: Code generation tool for configuration and status registers