rggen 0.3.0 → 0.3.1
Sign up to get free protection for your applications and to get access to all the features.
- checksums.yaml +4 -4
- data/README.md +94 -3
- data/lib/rggen/version.rb +1 -1
- data/rggen.gemspec +3 -2
- metadata +4 -4
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
---
|
2
2
|
SHA1:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: 9611e480b9eff4632912dfa604681ad9c6d47acb
|
4
|
+
data.tar.gz: b2e6bed99859b78f9f1f37ac0dcc81fc27e76625
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: 8a4f1de7b40b716eb50556b652fbb0df751e890784c6379d789dd13b95423aa6af42486197d5a4ebe6dba2fef8913c57453b4f4b02069b0d5d1e0445516d8eb8
|
7
|
+
data.tar.gz: 787b94fa2320624585fda53028cd9b0bfc5bdeaf85288bb2113bf52541e0c811dd583d95b2f460e0363fe7a0bee6ab5da308e626147152fb949b69b8f9d84696
|
data/README.md
CHANGED
@@ -1,18 +1,109 @@
|
|
1
|
+
[![Gem Version](https://badge.fury.io/rb/rggen.svg)](https://badge.fury.io/rb/rggen)
|
1
2
|
[![Build Status](https://travis-ci.org/taichi-ishitani/rggen.svg?branch=master)](https://travis-ci.org/taichi-ishitani/rggen)
|
2
3
|
[![Code Climate](https://codeclimate.com/github/taichi-ishitani/rggen/badges/gpa.svg)](https://codeclimate.com/github/taichi-ishitani/rggen)
|
3
4
|
[![Test Coverage](https://codeclimate.com/github/taichi-ishitani/rggen/badges/coverage.svg)](https://codeclimate.com/github/taichi-ishitani/rggen/coverage)
|
4
5
|
|
5
6
|
# RgGen
|
6
7
|
|
7
|
-
RgGen is a code generation tool for SoC designers.
|
8
|
+
RgGen is a code generation tool for SoC designers.
|
9
|
+
It will automatically generate source code for control registers in a SoC design, e.g. RLT, UVM RAL model, from its register map document.
|
10
|
+
Also RgGen is customizable so you can build your specific generate tool.
|
8
11
|
|
9
12
|
## Installation
|
10
13
|
|
11
|
-
|
14
|
+
To install RgGen and required libraries, use the following command:
|
15
|
+
|
16
|
+
$ gem install rggen
|
17
|
+
|
18
|
+
RgGen will be installed under your system root.
|
19
|
+
|
20
|
+
If you want to install them on other location, you need to specify the install directory and set the **GEM_PATH** environment variable like below:
|
21
|
+
|
22
|
+
$ gem install --install-dir YOUR_INSTALL_DIRECTORY rggen
|
23
|
+
$ export GEM_PATH=YOUR_INSTALL_DIRECTORY
|
24
|
+
|
12
25
|
|
13
26
|
## Usage
|
14
27
|
|
15
|
-
|
28
|
+
### Write Configuration File
|
29
|
+
|
30
|
+
A configuration file is to describe attributes of your design, e.g. data bus width, address bus width, host interface protocol.
|
31
|
+
RgGen supports YAML and JSON for its file format and allows to use Hash notation to describe attributes of your design like below.
|
32
|
+
|
33
|
+
- YAML
|
34
|
+
~~~YAML
|
35
|
+
address_width: 16
|
36
|
+
data_width: 32
|
37
|
+
host_if: apb
|
38
|
+
~~~
|
39
|
+
- JSON
|
40
|
+
~~~JSON
|
41
|
+
{
|
42
|
+
"address_width": 16,
|
43
|
+
"data_width": 32,
|
44
|
+
"host_if": "apb"
|
45
|
+
}
|
46
|
+
~~~
|
47
|
+
|
48
|
+
These attributes have default values. If you use a default value, you don't specify its value.
|
49
|
+
In addition, if you use default values for all of attributes, you don't need to write a configuration file.
|
50
|
+
|
51
|
+
### Write Register Map Document
|
52
|
+
|
53
|
+
RgGen allows to use a spreadsheet to input the register map of your design so you can directly input your register map document to RgGen.
|
54
|
+
To do this, you need to write your register map document according to below table format.
|
55
|
+
|
56
|
+
| |A |B |C |D |E |F |G |H |I |
|
57
|
+
|:---|:---|:-------------|:------------|:--------------|:--------------------------------|:-------------|:---------|:---|:-----------|
|
58
|
+
|1 | |Block Name |block_0 | | | | | | |
|
59
|
+
|2 | |Byte Size |256 | | | | | | |
|
60
|
+
|3 | | | | | | | | | |
|
61
|
+
|4 | |Offset Address|Register Name|Array Dimension|Shadow Index |Bit Assignment|Field Name|Type|Iitial Value|
|
62
|
+
|5 | |0x00 |register_0 | | |[31:16] |field_0_0 |rw |0 |
|
63
|
+
|6 | | | | | |[15:0] |field_0_1 |rw |0 |
|
64
|
+
|7 | |0x04 |register_1 | | |[16] |field_1_0 |rw |0 |
|
65
|
+
|8 | | | | | |[0] |field_1_1 |ro | |
|
66
|
+
|9 | |0x10 - 0x1F |register_2 |[4] | |[7:0] |field_2_0 |rw |0 |
|
67
|
+
|10 | |0x20 |register_3 |[2, 4] |field_1_0:1, field_0_0, field_0_1|[7:0] |field_3_0 |rw |0 |
|
68
|
+
|
69
|
+
By default, RgGen supports CSV, ODS, XLS and XLSX sparedsheet file types.
|
70
|
+
|
71
|
+
### Generate Source Code
|
72
|
+
|
73
|
+
To generate soruce code from your register map document, use the following command:
|
74
|
+
|
75
|
+
$ rggen your_register_map.xls
|
76
|
+
|
77
|
+
If you have a configuration file, you need to use `-c/--configuration` option:
|
78
|
+
|
79
|
+
$ rggen -c your_configuration.yml your_register_map.xls
|
80
|
+
|
81
|
+
By default, RgGen will generate RTL SV code under `rtl` directory and UVM RAL model under `ral` dicrectory.
|
82
|
+
In addition, file name of generated files is accoding to below rule.
|
83
|
+
- RTL
|
84
|
+
- `your_block_name`.sv
|
85
|
+
- RAL model
|
86
|
+
- `your_block_name`_ral_pkg.sv
|
87
|
+
|
88
|
+
### Compile Your Design
|
89
|
+
|
90
|
+
RgGen has base RTL modules and RAL model classes to build RTL and UVM RAL model.
|
91
|
+
Therefore, when you compile your design, you need to add these base modules and classes like below.
|
92
|
+
|
93
|
+
$ simulator \
|
94
|
+
+libext+.sv \
|
95
|
+
-y $RGGEN_INSTALL_DIRECTORY/rtl/register_block \
|
96
|
+
-y $RGGEN_INSTALL_DIRECTORY/rtl/register \
|
97
|
+
-y $RGGEN_INSTALL_DIRECTORY/rtl/bit_field \
|
98
|
+
-f $RGGEN_INSTALL_DIRECTORY/ral/compile.f \
|
99
|
+
rtl/your_register_block.sv \
|
100
|
+
ral/your_register_block_ral_pkg.sv \
|
101
|
+
your_design.v
|
102
|
+
|
103
|
+
### Note
|
104
|
+
|
105
|
+
Contents of configuration file and register map document and structure of genrerated RTL and RAL model described above are default.
|
106
|
+
Also you can change these by customizing RgGen.
|
16
107
|
|
17
108
|
## Development
|
18
109
|
|
data/lib/rggen/version.rb
CHANGED
data/rggen.gemspec
CHANGED
@@ -9,12 +9,13 @@ Gem::Specification.new do |spec|
|
|
9
9
|
spec.required_ruby_version = '>= 2.0'
|
10
10
|
spec.authors = ['Taichi Ishitani']
|
11
11
|
spec.email = ['taichi730@gmail.com']
|
12
|
+
spec.homepage = 'https://github.com/taichi-ishitani/rggen'
|
12
13
|
|
13
14
|
spec.summary = 'Code generation tool for control registers in a SoC design.'
|
14
15
|
spec.description = <<-EOS
|
15
16
|
RgGen is a code generation tool for SoC designers.
|
16
|
-
|
17
|
-
|
17
|
+
It will automatically generate source code for control registers in a SoC design, e.g. RLT, UVM RAL model, from its register map document.
|
18
|
+
Also RgGen is customizable so you can build your specific generate tool.
|
18
19
|
EOS
|
19
20
|
spec.homepage = ''
|
20
21
|
spec.license = 'MIT'
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: rggen
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.3.
|
4
|
+
version: 0.3.1
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Taichi Ishitani
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date: 2016-04-
|
11
|
+
date: 2016-04-14 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: baby_erubis
|
@@ -110,8 +110,8 @@ dependencies:
|
|
110
110
|
version: '0.35'
|
111
111
|
description: |2
|
112
112
|
RgGen is a code generation tool for SoC designers.
|
113
|
-
|
114
|
-
|
113
|
+
It will automatically generate source code for control registers in a SoC design, e.g. RLT, UVM RAL model, from its register map document.
|
114
|
+
Also RgGen is customizable so you can build your specific generate tool.
|
115
115
|
email:
|
116
116
|
- taichi730@gmail.com
|
117
117
|
executables:
|