rggen 0.3.0 → 0.3.1
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/README.md +94 -3
- data/lib/rggen/version.rb +1 -1
- data/rggen.gemspec +3 -2
- metadata +4 -4
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data/README.md
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[](https://badge.fury.io/rb/rggen)
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[](https://travis-ci.org/taichi-ishitani/rggen)
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[](https://codeclimate.com/github/taichi-ishitani/rggen)
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[](https://codeclimate.com/github/taichi-ishitani/rggen/coverage)
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# RgGen
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RgGen is a code generation tool for SoC designers.
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RgGen is a code generation tool for SoC designers.
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It will automatically generate source code for control registers in a SoC design, e.g. RLT, UVM RAL model, from its register map document.
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Also RgGen is customizable so you can build your specific generate tool.
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## Installation
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To install RgGen and required libraries, use the following command:
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$ gem install rggen
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RgGen will be installed under your system root.
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If you want to install them on other location, you need to specify the install directory and set the **GEM_PATH** environment variable like below:
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$ gem install --install-dir YOUR_INSTALL_DIRECTORY rggen
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$ export GEM_PATH=YOUR_INSTALL_DIRECTORY
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## Usage
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### Write Configuration File
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A configuration file is to describe attributes of your design, e.g. data bus width, address bus width, host interface protocol.
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RgGen supports YAML and JSON for its file format and allows to use Hash notation to describe attributes of your design like below.
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- YAML
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~~~YAML
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address_width: 16
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data_width: 32
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host_if: apb
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~~~
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- JSON
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~~~JSON
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{
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"address_width": 16,
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"data_width": 32,
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"host_if": "apb"
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}
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~~~
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These attributes have default values. If you use a default value, you don't specify its value.
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In addition, if you use default values for all of attributes, you don't need to write a configuration file.
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### Write Register Map Document
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RgGen allows to use a spreadsheet to input the register map of your design so you can directly input your register map document to RgGen.
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To do this, you need to write your register map document according to below table format.
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| |A |B |C |D |E |F |G |H |I |
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|:---|:---|:-------------|:------------|:--------------|:--------------------------------|:-------------|:---------|:---|:-----------|
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|1 | |Block Name |block_0 | | | | | | |
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|2 | |Byte Size |256 | | | | | | |
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|3 | | | | | | | | | |
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|4 | |Offset Address|Register Name|Array Dimension|Shadow Index |Bit Assignment|Field Name|Type|Iitial Value|
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|5 | |0x00 |register_0 | | |[31:16] |field_0_0 |rw |0 |
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|6 | | | | | |[15:0] |field_0_1 |rw |0 |
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|7 | |0x04 |register_1 | | |[16] |field_1_0 |rw |0 |
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|8 | | | | | |[0] |field_1_1 |ro | |
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|9 | |0x10 - 0x1F |register_2 |[4] | |[7:0] |field_2_0 |rw |0 |
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|10 | |0x20 |register_3 |[2, 4] |field_1_0:1, field_0_0, field_0_1|[7:0] |field_3_0 |rw |0 |
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By default, RgGen supports CSV, ODS, XLS and XLSX sparedsheet file types.
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### Generate Source Code
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To generate soruce code from your register map document, use the following command:
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$ rggen your_register_map.xls
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If you have a configuration file, you need to use `-c/--configuration` option:
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$ rggen -c your_configuration.yml your_register_map.xls
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By default, RgGen will generate RTL SV code under `rtl` directory and UVM RAL model under `ral` dicrectory.
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In addition, file name of generated files is accoding to below rule.
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- RTL
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- `your_block_name`.sv
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- RAL model
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- `your_block_name`_ral_pkg.sv
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### Compile Your Design
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RgGen has base RTL modules and RAL model classes to build RTL and UVM RAL model.
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Therefore, when you compile your design, you need to add these base modules and classes like below.
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$ simulator \
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+libext+.sv \
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-y $RGGEN_INSTALL_DIRECTORY/rtl/register_block \
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-y $RGGEN_INSTALL_DIRECTORY/rtl/register \
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-y $RGGEN_INSTALL_DIRECTORY/rtl/bit_field \
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-f $RGGEN_INSTALL_DIRECTORY/ral/compile.f \
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rtl/your_register_block.sv \
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ral/your_register_block_ral_pkg.sv \
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your_design.v
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### Note
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Contents of configuration file and register map document and structure of genrerated RTL and RAL model described above are default.
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Also you can change these by customizing RgGen.
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## Development
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data/lib/rggen/version.rb
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data/rggen.gemspec
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@@ -9,12 +9,13 @@ Gem::Specification.new do |spec|
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spec.required_ruby_version = '>= 2.0'
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spec.authors = ['Taichi Ishitani']
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spec.email = ['taichi730@gmail.com']
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spec.homepage = 'https://github.com/taichi-ishitani/rggen'
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spec.summary = 'Code generation tool for control registers in a SoC design.'
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spec.description = <<-EOS
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RgGen is a code generation tool for SoC designers.
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It will automatically generate source code for control registers in a SoC design, e.g. RLT, UVM RAL model, from its register map document.
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Also RgGen is customizable so you can build your specific generate tool.
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EOS
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spec.homepage = ''
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spec.license = 'MIT'
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metadata
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--- !ruby/object:Gem::Specification
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name: rggen
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version: !ruby/object:Gem::Version
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version: 0.3.
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version: 0.3.1
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platform: ruby
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authors:
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- Taichi Ishitani
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2016-04-
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date: 2016-04-14 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: baby_erubis
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version: '0.35'
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description: |2
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RgGen is a code generation tool for SoC designers.
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-
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-
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It will automatically generate source code for control registers in a SoC design, e.g. RLT, UVM RAL model, from its register map document.
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Also RgGen is customizable so you can build your specific generate tool.
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email:
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- taichi730@gmail.com
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executables:
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