rggen 0.28.0 → 0.29.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +5 -5
- data/lib/rggen/version.rb +1 -1
- metadata +17 -17
checksums.yaml
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@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 004f643d9fbfddecd1332c887eef0b9c2672359c83428b78e45b94d456fdbd65
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data.tar.gz: 485a2634d551be0c81884d47c39d863a165afbc1756c6bc6c913a06dc1f78104
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 4bdf4058626ca30aa08f2ac5a16cde93794bb6789fb5405849aa48327683b52563c1956561eb9cdc8cf742e01cc6e75dfbc93f21dce6e98f4fb38d5f4f147757
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data.tar.gz: 4ef22b5b7ee1123daaccc7ad3295ad816d4aa0f1cf33db77964b0312503eeeeb6bd19b0f321c396f8934f919c23c975cf3a8ae2aadfca29bb0f86455da85979d
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data/LICENSE
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The MIT License (MIT)
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Copyright (c) 2019-
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Copyright (c) 2019-2023 Taichi Ishitani
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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data/README.md
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# RgGen
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RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate
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RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL/uvm_reg), C header file, Wiki documents, from human readable register map specifications.
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RgGen has following features:
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@@ -44,7 +44,7 @@ RgGen has following features:
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### Ruby
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RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.
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RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.7 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
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### Installatin Command
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@@ -101,13 +101,11 @@ Following EDA tools can accept the generated source files.
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* Xilinx Vivado Simulator
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* Verilator
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* Need `-Wno-fatal` switch
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* Need to define `RGGEN_NAIVE_MUX_IMPLEMENTATION` macro
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* Icarus Verilog
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* Verilog RTL only
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* Synthesis tools
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* Synopsys Design Compiler
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* Intel Quartus
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* Need to define `RGGEN_NAIVE_MUX_IMPLEMENTATION` macro
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* Xilinx Vivado
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* [Yosys](http://www.clifford.at/yosys/)
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* Verilog RTL
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@@ -135,7 +133,9 @@ Then, generated files listed below will be written to `out` directory.
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* SystemVerilog RTL
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* https://github.com/rggen/rggen-sample/blob/master/block_0.sv
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* https://github.com/rggen/rggen-sample/blob/master/block_0_rtl_pkg.sv
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* https://github.com/rggen/rggen-sample/blob/master/block_1.sv
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* https://github.com/rggen/rggen-sample/blob/master/block_1_rtl_pkg.sv
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* UVM register model
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* https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv
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* https://github.com/rggen/rggen-sample/blob/master/block_1_ral_pkg.sv
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@@ -174,7 +174,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
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## Copyright & License
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Copyright © 2019-
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Copyright © 2019-2023 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
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## Code of Conduct
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data/lib/rggen/version.rb
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metadata
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--- !ruby/object:Gem::Specification
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name: rggen
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version: !ruby/object:Gem::Version
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version: 0.
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version: 0.29.0
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platform: ruby
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authors:
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- Taichi Ishitani
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autorequire:
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bindir: bin
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cert_chain: []
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date:
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date: 2023-01-02 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: rggen-c-header
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.3.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.3.0
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- !ruby/object:Gem::Dependency
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name: rggen-core
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.29.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.29.0
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- !ruby/object:Gem::Dependency
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name: rggen-default-register-map
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.29.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.29.0
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- !ruby/object:Gem::Dependency
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name: rggen-markdown
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.24.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.24.0
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- !ruby/object:Gem::Dependency
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name: rggen-spreadsheet-loader
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.24.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.24.0
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- !ruby/object:Gem::Dependency
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name: rggen-systemverilog
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requirement: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.29.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - "~>"
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.29.0
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- !ruby/object:Gem::Dependency
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name: bundler
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requirement: !ruby/object:Gem::Requirement
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@@ -110,7 +110,7 @@ dependencies:
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version: '0'
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description: |
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RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
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-
It will automatically generate
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+
It will automatically generate source code related to configuration and status registers (CSR),
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e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
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email:
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- rggen@googlegroups.com
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@@ -143,14 +143,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
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requirements:
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- - ">="
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- !ruby/object:Gem::Version
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version: '2.
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version: '2.7'
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required_rubygems_version: !ruby/object:Gem::Requirement
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requirements:
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- - ">="
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- !ruby/object:Gem::Version
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version: '0'
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requirements: []
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rubygems_version: 3.
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rubygems_version: 3.4.1
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signing_key:
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specification_version: 4
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summary: Code generation tool for configuration and status registers
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