rggen 0.27.1 → 0.28.0

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Files changed (4) hide show
  1. checksums.yaml +4 -4
  2. data/README.md +2 -0
  3. data/lib/rggen/version.rb +1 -1
  4. metadata +11 -11
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data/README.md CHANGED
@@ -101,11 +101,13 @@ Following EDA tools can accept the generated source files.
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  * Xilinx Vivado Simulator
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  * Verilator
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  * Need `-Wno-fatal` switch
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+ * Need to define `RGGEN_NAIVE_MUX_IMPLEMENTATION` macro
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  * Icarus Verilog
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  * Verilog RTL only
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  * Synthesis tools
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  * Synopsys Design Compiler
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  * Intel Quartus
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+ * Need to define `RGGEN_NAIVE_MUX_IMPLEMENTATION` macro
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  * Xilinx Vivado
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  * [Yosys](http://www.clifford.at/yosys/)
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  * Verilog RTL
data/lib/rggen/version.rb CHANGED
@@ -1,5 +1,5 @@
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  # frozen_string_literal: true
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  module RgGen
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- VERSION = '0.27.1'
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+ VERSION = '0.28.0'
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  end
metadata CHANGED
@@ -1,14 +1,14 @@
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  --- !ruby/object:Gem::Specification
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  name: rggen
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  version: !ruby/object:Gem::Version
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- version: 0.27.1
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+ version: 0.28.0
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  platform: ruby
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  authors:
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  - Taichi Ishitani
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2022-08-21 00:00:00.000000000 Z
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+ date: 2022-10-10 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: rggen-c-header
@@ -30,28 +30,28 @@ dependencies:
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.27.0
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+ version: 0.28.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.27.0
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+ version: 0.28.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-default-register-map
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.27.0
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+ version: 0.28.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.27.0
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+ version: 0.28.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-markdown
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  requirement: !ruby/object:Gem::Requirement
@@ -72,28 +72,28 @@ dependencies:
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.22.1
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+ version: 0.23.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.22.1
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+ version: 0.23.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-systemverilog
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.27.0
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+ version: 0.28.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.27.0
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+ version: 0.28.0
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  - !ruby/object:Gem::Dependency
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  name: bundler
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  requirement: !ruby/object:Gem::Requirement
@@ -111,7 +111,7 @@ dependencies:
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  description: |
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  RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
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  It will automatically generate soruce code related to configuration and status registers (CSR),
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- e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
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+ e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
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  email:
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  - rggen@googlegroups.com
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  executables: []